ST STNRG011A User manual

Introduction
This user manual provides information for developing applications with the STNRG011A digital combo multi-mode PFC and
time-shift LLC resonant controller.
The STNRG011A is a STMicroelectronics® digital device tailored for SMPS applications. It embodies a multi-mode (transition-
mode and DCM) PFC controller, a high voltage doubleended controller for the LLC resonant half-bridge, an 800 V-rated startup
generator and a sophisticated digital engine, that manages optimal operation of the three blocks.
All the key application parameter of the device are stored into an internal NVM (non-volatile memory), allowing wide
configurability and calibration.
This user manual goes in detail through all the NVM parameters and explains how to set them in a real application. For any
other information about STNRG011A product, please refer to the STNRG011A datasheet.
STNRG011A NVM parameters description
UM3002
User manual
UM3002 - Rev 1 - April 2022
For further information contact your local STMicroelectronics sales office.
www.st.com

1Notes
1.1 Parameters packing
The parameters in the NVM are packed starting from the first one at the address 0x00, going through the
boundaries between bytes if required.
1.2 NVM configuration
The NVM is divided into 4 parts called bank0, bank1, bank2 and bank3. Each bank size is 8 bytes.
Bank0 contains mainly trimming and traceability information. For this reason, users cannot modify it.
Bank1, 2 and 3 contain the parameters described in this document. The user can modify them to adapt the
STNRG011A algorithms to his application.
1.3 GUI application
In order to easily program the NVM during the development of a new application, a graphical user interface (GUI)
has been developed. The GUI strictly works with a communication interface board and allows real time monitoring
of the device, NVM and EEPROM contents checking and programming. For more information about the GUI and
the interface board, please refer to the user manual on www.st.com: Getting started with the STEVAL-PCC020V2:
USB to I²C UART interface board and associated GUI for STNRG products.
UM3002
Notes
UM3002 - Rev 1 page 2/42

2Equations to set the parameters
2.1 PFC
2.1.1 PFC power calculation
The device uses an internal numerical representation of the power delivered. The relationship between the
internal value and the true power is as follows:
Equation 1
pinn = P L
128 ∙LSBVin2∙Tck
(1)
Where:
•pinn is the internal numerical power estimation
•P is the real power level
•L is the PFC choke inductance value
•LSBVin = 1.89 V
•Tck = 16.66 ns
Note that this relation is a loose approximation due to the PFC parasitics, which offset the true power level.
2.1.2 PFC compensation parameters
The PFC compensation is calculated at each line valley (i.e. input mains zero crossing). The device uses the
following formula to calculate the power
Equation 2
pinn = 2 ∙Kp + Ki 1
1−z−1err (2)
where err is equal to the voltage error (target output voltage - real output voltage) divided by VerrLSB = 0.473 V.
2.2 LLC
The LLC compensation is based on an analog circuitry at the secondary side.
The time shift value applied by the controller is calculated using the sampled value on the LLC_FB pin.
Equation 3
TS = 0.5 ∙VFB
LSBVFB −FBOS (3)
where:
• TS = time shift value applied to LLC SMEDs (in 60 MHz clock ticks)
• VFB = Voltage on the LLC_FB pin
• LSBVFB = 2.44 mV (used to convert the LLC_FB voltage value in the internal numerical format)
• FBos = fixed offset (68)
UM3002
Equations to set the parameters
UM3002 - Rev 1 page 3/42

3Parameters description
3.1 General system configuration
3.1.1 Shutdown feature
Size: 1 bit
Enables / disables the shutdown comparator connected to the LLC_FB pin.
Available values are:
• Disabled
• Enabled
The shutdown comparator is connected to the LLC_FB pin. Its threshold is 125 mV. If the pin is brought below this
threshold, and the comparator is enabled, the system will shut down as long as the pin's voltage remains below
the threshold.
This feature can be used to realize extra protections (e.g. OTP protection for power stage).
Use
It is suggested to disable the shutdown comparator if it is not used.
3.1.2 Patch upload from EEPROM
Size:1 bit
Enables / disables the patching feature. Available values are:
• Disabled
• Enabled
If patching is disabled the STNRG011A will not upload the patch from the external EEPROM.
Use
The default value is disabled (i.e. patching disabled). The user has to maintain the patching feature disabled if no
EEPROM is installed on the application.
3.1.3 ATE mode
Size:1 bit
Enables / disables the ATE mode. Available values are:
• Enabled
• Disabled
Use
The ATE mode is required to read/write the NVM. Therefore, this parameter should be set to “Enabled”.
In case, after the correct programming of all NVM parameters, the user wants to keep such information protected,
he can disable the ATE mode.
Warning: Once the bit will be set to disabled, it will be impossible to access the NVM.
3.1.4 System monitoring
Size:1 bit
Enables / disables the system monitoring. Available values are:
• Enabled
• Disabled
Monitoring is the periodic unidirectional communication through the UART interface used by the STNRG011A to
send out information (including the power estimation, PFC operating mode, etc.). If this feature is not requested,
the user can disable it and stop the activity on the UART interface.
UM3002
Parameters description
UM3002 - Rev 1 page 4/42

3.1.5 VAC reading improvement
Size:1 bit
Enables / disables the VAC reading improvement feature. Available values are:
• Disabled
• Enabled
If the feature is enabled, the IC will sink from the VAC pin IVAC_HV_SINK current during line synchronization at
the start-up and IXCD current for about 5 ms in case of the brown-out event, to avoid false brown-in. This allows
having a voltage on the VAC pin that has a good shape and compensate the effect of an unbalanced Y-cap in the
AC input (such unbalance generates a charge pump effect that increases the VAC voltage).
Use
It is suggested to keep the feature enabled.
3.1.6 Early warning feature
Size:1 bit
Enables / disables the early warning (EW) pulse generation. This pulse is used to manage the “Power OK” signal.
Available values are:
• Enabled
• Disabled
The EW pulse is generated on the PFC_FB pin. This pin, normally the input for sensing the PFC output voltage, in
case of device shutdown becomes an output and goes to 5 V.
The duration of the pulse depends on the shut-down cause.
For the normal shutdown (i.e. mains removal, brown-out event, OLP and PFC UVP faults) the pulse is 5 ms long
(normal pulse). During this time, the PFC is stopped while the LLC is still working keeping the output voltage
regulated.
In case of a dangerous fault, both PFC and LLC stages are immediately stopped and the EW pulse is about 270
μs long (quick pulse).
3.1.7 EW signal in burst mode
Size:1 bit
Selects the duration of the early warning pulse in the burst mode.
Available values are:
• Quick
• Normal
Use
The selection will force the system to use the quick pulse without any LLC activity in the burst mode also during
the normal shutdown. This is useful in case the LLC tank is not designed to keep the output voltage regulated at
no-load, avoiding the overshoot of the output.
3.1.8 Non latched faults timer
Size:2 bits
Sets the time between retries in the non-latched (auto restart) mode.
Available values are:
• 546 ms
• 1.09 s
• 2.18 s
• 4.37 s
UM3002
General system configuration
UM3002 - Rev 1 page 5/42

3.2 Faults parameters
3.2.1 Surge detection
Size:1 bit
Enable / disable the surge comparator.
Available values are:
• Disabled
• Enabled
The surge comparator is connected to the VAC pin and its threshold is 430 V.
3.2.2 PFC OC2 detection
Size:1 bit
Enables / disables the PFC OC2 comparator.
Available values are:
• Disabled
• Enabled
The PFC OC2 comparator is connected to the PFC_CS pin and its threshold is 900 mV.
3.2.3 Max number of PFC OC2
Size:2 bits
Sets the number of consecutive PFC OC2 events before shutting down.
Available values are:
• 1
• 2
• 4
• 8
Use
The suggested value is “2”, since it is a good compromise between the noise rejection and protection
reactiveness.
The value “1” can be used if minimum intervention time is required: in this case, pay attention because some
noise could trigger the protection. Higher values can be used in case of noisy boards (in this case, the reaction to
real OCP2 events will be slower).
3.2.4 PFC HW OVP detection
Size: 1 bit
Enable / disable the hardware PFC OVP comparator.
Available values are:
• Disabled
• Enabled
The PFC OVP comparator is the hardware protection against the bulk overvoltage. It is connected to the PFC_FB
pin and its threshold is set at 2.3 V.
The fault is always immediate and shuts down the system.
Use
It is suggested to leave the PFC OVP comparator enabled.
3.2.5 LLC OC2 detection
Size: 1 bit
Enables / disables the LLC OC2 comparator.
Available values are:
• Disabled
UM3002
Faults parameters
UM3002 - Rev 1 page 6/42

• Enabled
The LLC OC2 comparator is connected to the LLC_CS pin and its threshold is 700 mV.
3.2.6 Max number of LLC OC2
Size: 2 bits
Sets the number of consecutive LLC OC2 events before shutting down.
Available values are:
• 1
• 2
• 4
• 8
Use
The suggested value is “2”, since it is a good compromise between the noise rejection and protection
reactiveness.
The value “1” can be used if minimum intervention time is required: in this case, pay attention because some
noise could trigger the protection.
3.2.7 LLC OVP detection
Size: 1 bit
Enables / disables the LLC OVP comparator.
Available values are:
• Disabled
• Enabled
The LLC OVP comparator is connected to the LLC_AUX pin and its threshold is 2.5 V.
3.2.8 Disconnection faults detection
Size: 1 bit
Enables / disables the feedback disconnections faults detection.
Available values are:
• Disabled
• Enabled
Use
It is suggested to enable the feedback disconnection faults detection.
Note: Disconnection faults have always “latched” behavior.
3.2.9 PFC OC2 behavior
Size: 1 bit
Sets the behavior of PFC OC2 protection.
Available values are:
• Not latched
• Latched
If the fault is set as “Not latched” the system will try to restart after the time defined by the “Non latched faults
timer” parameter.
If the fault is set as “Latched” the switching activity will remain off and the VCC will remain between 15 V and 17 V
using the HV start-up generator (as long as there is the mains connected).
3.2.10 PFC HW OVP behavior
Size: 1 bit
Sets the behavior of the PFC OVP.
Available values are:
UM3002
Faults parameters
UM3002 - Rev 1 page 7/42

• Not latched
• Latched
If the fault is set as “Not latched” the system will try to restart after the time defined by the “Non latched faults
timer” parameter.
If the fault is set as “Latched” the switching activity will remain off and the VCC will remain between 15 V and 17 V
using the HV start-up generator (as long as there is the mains connected).
3.2.11 PFC UVP behavior
Size: 1 bit
Sets the behavior of the PFC UVP.
Available values are:
• Slow
• Adaptive
When the UVP threshold is detected, if this parameter is set “Slow”, the device will shut down the power supply if
the PFC UVP is still present for at least 100 ms.
If the behavior is set to “Adaptive”, the device will shut down the power supply if the PFC UVP is triggered and the
mains voltage is detected below the brown-out threshold. If both conditions are not true, the system will manage
the fault as if the selection is set “Slow”. This selection enables large capacitive loads to be connected through
the OR-Ing FET. The “Slow” timing could be helpful in some case, when the designer would like to let the system
work with a low bulk voltage.
Please remember that, because of the LLC OC2 protection and the ACP feature, the system is still protected
against overstresses.
3.2.12 LLC SS timeout behavior
Size: 1 bit
Sets the behavior of the LLC soft-start timeout protection.
Available values are:
• Not latched
• Latched
If the fault is set as “Not latched” the system will try to restart after the time defined by the “Non latched faults
timer” parameter.
If the fault is set as “Latched” the switching activity will remain off and the VCC will remain between 15 V and 17 V
using the HV start-up generator (as long as there is the mains connected).
3.2.13 LLC ACP behavior
Size: 1 bit
Sets the behavior of the LLC ACP (both “Soft” and “Hard”).
Available values are:
• Not latched
• Latched
If the fault is set as “Not latched” the system will try to restart after the time defined by the “Non latched faults
timer” parameter.
If the fault is set as “Latched” the switching activity will remain off and the VCC will remain between 15 V and 17 V
using the HV start-up generator (as long as there is the mains connected).
3.2.14 LLC OC2 behavior
Size: 1 bit
Sets the behavior of the LLC OC2 protection.
Available values are:
• Not latched
• Latched
UM3002
Faults parameters
UM3002 - Rev 1 page 8/42

If the fault is set as “Not latched” the system will try to restart after the time defined by the “Non latched faults
timer” parameter.
If the fault is set as “Latched” the switching activity will remain off and the VCC will remain between 15 V and 17 V
using the HV start-up generator (as long as there is the mains connected).
3.2.15 LLC OLP behavior
Size: 1 bit
Sets the behavior of the LLC overload protection (OLP).
Available values are:
• Not latched
• Latched
If the fault is set as “Not latched” the system will try to restart after the time defined by the “Non latched faults
timer”.
If the fault is set as “Latched” the switching activity will remain off and the VCC will remain between 15 V and 17 V
using the HV start-up generator (as long as there is the mains connected).
3.2.16 LLC OVP behavior
Size: 1 bit
Sets the behavior of the LLC OVP.
Available values are:
• Not latched
• Latched
If the fault is set as “Not latched” the system will try to restart after the time defined by the “Non latched faults
timer” parameter.
If the fault is set as “Latched” the switching activity will remain off and the VCC will remain between 15 V and 17 V
using the HV start-up generator (as long as there is the mains connected).
3.3 PFC parameters
3.3.1 PFC Ki
Size:3 bits
Sets the integral constant of the PFC compensation filter.
Available values are:
• 4
• 6
• 8
• 12
• 16
• 24
• 32
• 48
3.3.2 PFC Kp
Size:3 bits
Sets the proportional constant of the PFC compensation filter.
Available values are:
• 8
• 12
• 16
• 24
• 32
UM3002
PFC parameters
UM3002 - Rev 1 page 9/42

• 48
• 64
• 96
Note: The device uses 2 * Kp for calculations (see Section 2.1.2 PFC compensation parameters)
3.3.3 PFC MOSFET LEB
Size: 3 bits
Sets the PFC MOSFET minimum on-time (also called LEB, i.e. “Leading Edge Blanking”).
Available values are:
• 133 ns
• 167 ns
• 200 ns
• 233 ns
• 267 ns
• 333 ns
• 400 ns
• 467 ns
This time is used to filter the spike on the PFC_CS pin at the PFC MOSFET turn-on. During this time the PFC_CS
comparator output (THD improver) is ignored.
Use
Adjust the blanking time according to design requirements.
The middle value 267 ns can be used as a starting point and then, after looking at the PFC_CS waveform during
the PFC operation it can be adjusted.
3.3.4 PFC THD improver base
Size: 3 bits
Sets the base value for the ReCOT functionality (THD improver).
Available values are:
• 0 mV
• 2 mV
• 4 mV
• 6 mV
• 8 mV
• 10 mV
• 12 mV
• 14 mV
The parameter sets the PFC_CS comparator threshold.
Use
This parameter can be tuned to improve the THD of the system. Together with the “PFC THD improver gain”, this
parameter can be used to improve the distortion and power factor of the PFC observing the current waveform and
THD/PF measurements.
UM3002
PFC parameters
UM3002 - Rev 1 page 10/42

3.3.5 PFC THD improver gain
Size: 3 bits
Sets the slope of the ReCOT functionality (THD improver) to compensate for the current in the input capacitors.
Available values are:
• 0 - gain disabled
• 1
• 2
• 3
• 4
• 5
• 6
• 7
The threshold level difference between the beginning and the end of the line cycle is
Equation 4
Vramp = igain ∙2Vin ∙3.9mV
256 ∙484.5V/256 (4)
i.e.
Equation 5
Vramp = igain ∙Vin ∙11.38 ∙10−6(5)
Which will act as a negative capacitance of the value
Equation 6
Cneg = 2 ∙10−6gain
πflineRsense (6)
Use
Together with the “PFC THD improver base”, this parameter can be used to improve the distortion and power
factor of the PFC.
The value can be initially calculated with Equation 6 to compensate for the capacitance at the PFC input and EMI
filter and then tune it by observing the current waveform at the converter input and THD/PF measurements to find
the optimum point.
3.3.6 PFC maximum power
Size: 4 bits
Sets the upper clamp of the PI filter, i.e. the maximum power that the PFC can provide.
Available values are:
• 4096
• 4608
• 5120
• 5632
• 6144
• 6656
• 7168
• 7680
• 8192
• 9216
• 10240
• 11264
• 12288
• 13312
• 14336
• 15360
UM3002
PFC parameters
UM3002 - Rev 1 page 11/42

Use
Select a value higher than the nominal power in order to be able to respond to transients.
To initially setup this value, set it to twice the maximum power estimation using Equation 1 in Section 2.1.1 PFC
power calculation.
Then fine-tune it by
• Turning on the board with the maximum load
• Reading the input power raw value using the GUI (see Figure 1 for details)
• Setting the parameter to input power raw value + 30%
The value can be further adjusted by looking at the PFC stage transient response.
Figure 1. STNRG011A GUI; circled in red the raw value of the input power
3.3.7 PFC pss
Size: 3 bits
Sets the PFC power during the soft-start.
Available values are:
• 640
• 1280
• 1920
• 2560
• 3200
• 3840
• 4480
• 5120
The higher the value, the higher the on-time of the PFC MOSFET during the soft-start phase.
Use
Choose the value that allows reaching the required PFC soft-start time.
The faster the soft-start time required the higher the PFC current will be.
Using a high value can lead to overshoots (the bulk voltage increases at every line cycle increase).
3.3.8 PFC pcc
Size: 2 bits
Sets the PFC reference the power during burst mode operation.
Available values are:
• 3218
UM3002
PFC parameters
UM3002 - Rev 1 page 12/42

• 5558
• 7898
• 10238
The higher the value, the higher the maximum on-time of the PFC MOSFET during the burst mode operation.
This means that the transferred power will be also higher.
The algorithm will adjust the on-time of the PFC MOSFET according to the required power, in order to reduce the
acoustic noise.
Use
Select the lowest value that allows correct bulk voltage regulation at the no-load and minimum AC voltage
condition.
3.3.9 PFC Min Pin Vskip
Size: 5 bits
Sets the internal power threshold at which the mode is changed towards DCM (i.e. one more valley is skipped).
Available values are:
• 1280
• 1344
• 1408
• 1472
• 1536
• 1600
• 1664
• 1728
• 1792
• 1856
• 1920
• 1984
• 2048
• 2112
• 2176
• 2240
• 2304
• 2368
• 2432
• 2496
• 2560
• 2624
• 2688
• 2752
• 2816
• 2880
• 2944
• 3008
• 3072
• 3136
• 3200
• 3264
Use
This parameter is mainly used to guarantee a fast reaction to transients, forcing the PFC to increase the number
of valleys or switch to DCM when the internal power value plus nValleys * “PFC Delta Pin Vskip” is lower than this
parameter.
The frequency based mode change measures the frequency at each half line cycle, then if the frequency is out
of the “PFC Min Tsw Vskip” or “PFC Max Tsw Vskip” values it increments or decrements the number of valleys
by one. By only relying on the frequency it would require 4 half-line cycles to change from TM to DCM, potentially
causing an overshoot on the Vbus.
The threshold should be kept low enough so that in steady state the frequency dominates the mode change.
3.3.10 PFC Max Pin Vskip (delta)
Size: 5 bits
Sets the internal power threshold at which the mode is changed toward TM (i.e. one less valley is skipped).
Available values are:
• 1280
• 1408
• 1536
• 1664
• 1792
• 1920
• 3328
• 3456
• 3584
• 3712
• 3840
• 3968
UM3002
PFC parameters
UM3002 - Rev 1 page 13/42

• 2048
• 2176
• 2304
• 2432
• 2560
• 2688
• 2816
• 2944
• 3072
• 3200
• 4096
• 4224
• 4352
• 4480
• 4608
• 4736
• 4864
• 4992
• 5120
• 5248
The parameter in the NVM is a positive delta with respect to the “PFC Min Tsw Vskip”. The real value used during
the code execution is therefore
Equation 7
"PFCMaxPinVskip" = "PFCMinPinVskip" + "PFCMaxPinVskip delta " (7)
Use
This parameter is mainly used to guarantee a fast reaction to transients, forcing the PFC to reduce the number of
valleys or to switch to the transition mode when the internal power value plus nValleys * “PFC Delta Pin Vskip” is
greater than this parameter.
The frequency based mode change measures the frequency at each half line cycle, then if the frequency is out
of the “PFC Min Tsw Vskip” or “PFC Max Tsw Vskip” values it increments or decrements the number of valleys
by one. By only relying on the frequency it would require 4 half-line cycles to change from DCM to TM, potentially
causing a dip on the Vbus.
The threshold should be kept high enough so that in the steady state the frequency dominates the mode change.
3.3.11 PFC Delta Pin Vskip
Size: 5 bits
Sets a correction factor used when switching between valley-skipping modes.
Available values are:
• 160
• 176
• 192
• 208
• 224
• 240
• 252
• 272
• 288
• 304
• 320
• 336
• 352
• 368
• 384
• 400
• 416
• 432
• 448
• 464
• 480
• 496
• 512
• 528
• 544
• 560
• 576
• 592
• 608
• 624
• 640
• 656
Use
This parameter should be approximately set to the reduction of output power determined by the addition of one
valley.
The device uses this parameter to reduce the discontinuity on the output power when changing the number of
valleys skipped.
UM3002
PFC parameters
UM3002 - Rev 1 page 14/42

3.3.12 PFC maximum DCM power
Size: 4 bits
Sets the power threshold to switch from the DCM to the valley-skipping mode. Sets also the on-time duration of
the PFC gate drive while in the DCM mode.
Available values are:
• 1024
• 1152
• 1280
• 1408
• 1536
• 1664
• 1792
• 1920
• 2048
• 2304
• 2560
• 2816
• 3072
• 3328
• 3584
• 3840
In the DCM mode, the MOSFET on-time is calculated with the following formula
Equation 8
Ton = "PFCMaximumDCMpower" ∙2
Vin2(8)
3.3.13 PFC Min Tsw Vskip
Size: 5 bits
Sets the minimum switching period (i.e. the maximum switching frequency) for the valley skipping mode.
Available values are:
• 234 kHz
• 221 kHz
• 208 kHz
• 197 kHz
• 188 kHz
• 179 kHz
• 170 kHz
• 163 kHz
• 156 kHz
• 150 kHz
• 144 kHz
• 139 kHz
• 134 kHz
• 129 kHz
• 125 kHz
• 121 kHz
• 117 kHz
• 110 kHz
• 104 kHz
• 99 kHz
• 94 kHz
• 89 kHz
• 85 kHz
• 82 kHz
• 78 kHz
• 75 kHz
• 72 kHz
• 69 kHz
• 67 kHz
• 65 kHz
• 63 kHz
• 60 kHz
The period is measured at the peak of the mains sinusoidal voltage. If the measured period is lower than this
value, the system increases the number of valleys, towards DCM.
The corresponding frequency values are shown above.
Use
UM3002
PFC parameters
UM3002 - Rev 1 page 15/42

This value, together with the “PFC Max Tsw Vskip”, is used to set the range of PFC switching frequency;
therefore, it is important to optimize the efficiency of the PFC.
The max. value should be at least 1.5 times the min. value to avoid the system continuously switching between
different modes.
3.3.14 PFC Max Tsw Vskip
Size: 5 bits
Sets the maximum switching period (i.e. the minimum switching frequency) for the valley-skipping mode.
Available values are:
• 101 kHz
• 96 kHz
• 91 kHz
• 87 kHz
• 83 kHz
• 80 kHz
• 77 kHz
• 74 kHz
• 71 kHz
• 68 kHz
• 66 kHz
• 64 kHz
• 61 kHz
• 60 kHz
• 58 kHz
• 56 kHz
• 54 kHz
• 51 kHz
• 49 kHz
• 46 kHz
• 44 kHz
• 42 kHz
• 40 kHz
• 39 kHz
• 37 kHz
• 36 kHz
• 34 kHz
• 33 kHz
• 32 kHz
• 31 kHz
• 30 kHz
• 29 kHz
The period is measured at the peak of the mains sinusoidal voltage. If the measured period is higher than this
value, the system decreases the number of valleys, towards TM.
The corresponding frequency values are shown above.
Use
This value, together with the “PFC Min Tsw Vskip”, is used to set the range of PFC switching frequency; therefore,
it is important to optimize the efficiency of the PFC.
The max. value should be at least 1.5 times the min. value to avoid the system continuously switching between
different modes.
3.3.15 Skipping area threshold
Size: 4 bits
Sets the power level at which the PFC will start reducing the conduction phase to a part of the AC line half-cycle
(skipping area feature).
UM3002
PFC parameters
UM3002 - Rev 1 page 16/42

Available values are:
• 0
• 320
• 384
• 448
• 512
• 640
• 768
• 896
• 1024
• 1280
• 1536
• 1792
• 2048
• 2560
• 3072
• 3584
Use
This parameter can be used to improve efficiency at the power levels at which harmonic contents are not subject
to regulation (e.g. below 75 W).
To tune the parameter, run the system at the desired threshold level and Vac value, read the input power raw
value from the GUI and use it as the threshold (see Figure 1 for details).
It is suggested to keep a 20% margin to take into account variations from unit to unit (e.g. set the threshold to 60
W to assure it is out of this mode at 75 W).
Test the exit point from the skipping area mode at the nominal mains voltages to check that the system returns in
the continuous switching mode below 75 W.
Setting this parameter to “0” disables the skipping area feature, in case good THD and PF are required even at
very low loads.
3.3.16 PFC Vout target
Size: 3 bits
Sets the nominal PFC output voltage.
Available values are:
• 1.946 V - 377 V
• 1.965 V - 381 V
• 1.985 V - 385 V
• 2.004 V - 388 V
• 2.024 V - 392 V
• 2.063 V - 400 V
• 2.102 V - 407 V
• 2.141 V - 415 V
This is the voltage level at which the PFC stage regulates its output, in all operating conditions.
Use
Set the PFC output voltage according to the application specs.
The values on the left are referred to the PFC_FB pin, that corresponds to values on theright if the bulk voltage
divider is designed with the standard ratio k = 5.16 · 10-3 (i.e. 484.5 V on the bulk voltage correspond to 2.5 V on
the PFC_FB pin).
If other bulk voltage dividers are used, the values on the left can be used to set the outputvoltage. In this case,
consider that the PFC HW OVP comparator has a fixed threshold of 2.3 V.
UM3002
PFC parameters
UM3002 - Rev 1 page 17/42

3.3.17 PFC Vout SS end (delta)
Size:2 bits
Sets the voltage at which the PFC terminates the soft-start and the system begins the LLC soft-start.
Available values are:
• 19.5 mV - 3.8 V
• 29.3 mV - 5.7 V
• 39.1 mV - 7.6 V
• 58.6 mV - 11.4 V
Use
The above values are intended as a negative delta with respect to the “PFC Vout target” parameter.
The PFC soft-start end voltage will be therefore:
Equation 9
"PFCVoutSSend" = "PFCVouttarget" −"PFCVoutSSend delta " (9)
The values on the left are referred to the PFC_FB pin, that corresponds to values on the right if the bulk voltage
divider is designed with the standard ratio k = 5.16 · 10-3 (i.e. 484.5 V on the bulk voltage correspond to 2.5 V on
the PFC_FB pin).
If other bulk voltage dividers are used, the values on the left can be used to set the output voltage.
3.3.18 PFC UVP threshold (delta)
Bits: 3
Sets the UVP level for PFC output voltage.
Available values are:
• 0.156 V - 30 V
• 0.234 V - 45 V
• 0.313 V - 61 V
• 0.391 V - 76 V
• 0.469 V - 91 V
• 0.547 V - 106 V
• 0.625 V - 121 V
• 0.703 V - 136 V
Use
The above values are intended as a negative delta with respect to the “PFC Vout target” parameter.
In fact, the UVP threshold is defined as
Equation 10
"PFCUVPthreshold" = "PFCVouttarget" −"PFCUVPthreshold delta " (10)
The values on the left are referred to the PFC_FB pin, that corresponds to values on the right if the bulk voltage
divider is designed with the standard ratio k = 5.16 · 10-3 (i.e. 484.5 V on the bulk voltage correspond to 2.5 V on
the PFC_FB pin).
If other bulk voltage dividers are used, the values on the left can be used to set the output voltage.
3.3.19 PFC SW OVP threshold (delta)
Size: 2 bits
Sets the PFC SW OVP level.
Available values are:
• 51.3 mV - 10 V
• 78.1 mV - 15 V
• 105 mV - 20 V
• SW OVP disabled
UM3002
PFC parameters
UM3002 - Rev 1 page 18/42

Use
The above values are intended as a positive delta with respect to the “PFC Vout target” parameter.
In fact, the SW OVP threshold is defined as:
Equation 11
"PFCSWOVPthreshold" = "PFCVouttarget" −"PFCSWOVPthreshold delta " (11)
The values on the left are referred to the PFC_FB pin, that corresponds to values on the right if the bulk voltage
divider is designed with the standard ratio k = 5.16 · 10-3 (i.e. 484.5 V on the bulk voltage correspond to 2.5 V on
the PFC_FB pin).
If other bulk voltage dividers are used, the values on the left can be used to set the output voltage. It is suggested
to keep the SW OVP enabled with the maximum value 105 mV - 20 V, especially if the “PFC boost exiting burst”
feature is enabled.
3.4 LLC parameters
3.4.1 Soft ACP feature
Size: 1 bit
Enables / disables the soft ACP management.
Available values are:
• Enabled
• Disabled
Soft ACP is the protection that is triggered when the system is approaching the capacitive mode (i.e. the time
between the MOSFET turn-on and tank current zero crossing becomes smaller than the value programmed with
the parameter “Soft ACP entering threshold”).
The feature will try to recover the capacitive mode, reducing the LLC time shift value of a quantity defined by
the “Soft ACP TS decrement”, every time the protection is triggered, for a maximum number of occurrences of
“Maximum soft ACP occurrences”.
Every time the system triggers the soft ACP feature, the STNRG011A will move to the softstart state, to smoothly
recover the regulation.
The system will shut down for the soft ACP fault if the minimum time shift or the maximum number of soft ACP
occurrences is reached. The fault can be latched or not latched depending on the “LLC ACP behavior”.
3.4.2 LLC HVG first Ton
Size: 4 bits
Sets the total on-time of the first LLC HVG.
Available values are:
• 133.3 ns
• 200 ns
• 266.7 ns
• 333.3 ns
• 400 ns
• 466.7 ns
• 533.3 ns
• 600 ns
• 666.7 ns
• 800 ns
• 933.3 ns
• 1067 ns
• 1200 ns
• 1333 ns
• 1467 ns
• 1600 ns
UM3002
LLC parameters
UM3002 - Rev 1 page 19/42

At the LLC turn-on, during the safe-start phase, this is the total on-time of the first pulse of the high-side gate
drive. Typically, higher values have to be used with high Llk resonant tanks.
3.4.3 LLC LVG first TS
Size: 4 bits
Sets the time shift value of the first LLC LVG.
Available values are:
• 166.7 ns
• 200 ns
• 233.3 ns
• 266.7 ns
• 300 ns
• 333.3 ns
• 366.7 ns
• 400 ns
• 433.3 ns
• 500 ns
• 566.7 ns
• 633.3 ns
• 700 ns
• 766.7 ns
• 833.3 ns
• 900 ns
This parameter defines the time shift for the first low side gate drive pulse, during the safe start.
Such time shift value is then used as the first one for the LLC soft-start.
3.4.4 LLC dead time
Size: 2 bits
Sets the LLC half-bridge dead time.
Available values are:
• 266.7 ns
• 333.3 ns
• 400 ns
• 466.7 ns
Use this parameter to select the dead time duration (for both transitions) according to
resonant tank needs.
3.4.5 LLC soft-start speed
Size: 3 bits
Sets the speed of the LLC soft-start.
Available values are:
• 8.3 ns
• 16.7 ns
• 25 ns
• 33.3 ns
• 41.7 ns
• 50 ns
• 58.3 ns
• 66.7 ns
This parameter is the time shift increment applied every 30 μs during the LLC soft-start.
UM3002
LLC parameters
UM3002 - Rev 1 page 20/42