ST STR71xF User manual

August 2006 Rev 9 1/74
74
STR71xF
ARM7TDMI™ 32-bit MCU with Flash, USB, CAN
5 timers, ADC, 10 communications interfaces
■Core
– ARM7TDMI 32-bit RISC CPU
– 59 MIPS @ 66 MHz from SRAM
– 45 MIPS @ 50 MHz from Flash
■Memories
– Up to 256Kbytes Flash program memory
(10 kcycles endurance, 20 yrs retention @
85° C)
– 16K bytes Flash data memory
(100 kcycles endurance, 20 yrs retention@
85° C)
– Up to 64 Kbytes RAM
– External Memory Interface (EMI) for up to 4
banks of SRAM, Flash, ROM
– Multi-boot capability
■Clock, Reset and Supply Management
– 3.0 to 3.6V application supply and I/Os
– Internal 1.8V regulator for core supply
– Clock input from 0 to 16.5 MHz
– Embedded RTC oscillator running from
external 32 kHz crystal
– Embedded PLL for CPU clock
– Realtime Clock for clock-calendar function
– 5 power saving modes: SLOW, WAIT,
LPWAIT, STOP and STANDBY modes
■Nested interrupt controller
– Fast interrupt handling with multiple vectors
– 32 vectors with 16 IRQ priority levels
– 2 maskable FIQ sources
■Up to 48 I/O ports
– 30/32/48 multifunctional bidirectional I/Os
– Up to 14 ports with interrupt capability
■5 Timers
– 16-bit watchdog timer
– 3 16-bit timers with 2 input captures, 2
output compares, PWM and pulse counter
– 16-bit timer for timebase functions
■10 Communications Interfaces
–2I
2C interfaces (1 multiplexed with SPI)
– 4 UART asynchronous serial interfaces
– Smart Card ISO7816-3 interface on UART1
– 2 BSPI synchronous serial interfaces
– CAN interface (2.0B Active)
– USB Full Speed (12Mbit/s) Device Function
with Suspend and Resume
– HDLC synchronous communications
■4-channel 12-bit A/D Converter
– Sampling frequency up to 1kHz
– Conversion range: 0 to 2.5V
■Development Tools support
LQFP64
10 x 10 LQFP144
20 x 20
LFBGA64 8 x 8 x 1.7 LFBGA144 10 x 10 x 1.7
LFBGA64 8 x 8 x 1.7
Table 1. Device summary
Features STR710
FZ1
STR710
FZ2
STR710
RZ
STR711
FR0
STR711
FR1
STR711
FR2
STR712
FR0
STR712
FR1
STR712
FR2
STR715
FRx
Flash - Kbytes 128+16 256+16 0 64+16 128+16 256+16 64+16 128+16 256+16 64+16
RAM - Kbytes 32 64 64 16 32 64 16 32 64 16
Peripheral Functions CAN, EMI, USB, 48 I/Os USB, 30 I/Os CAN, 32 I/Os 32 I/Os
Operating Voltage 3.0 to 3.6V
Operating Temp. -40 to +85°C
Packages T=LQFP144 20 x 20
H=LFBGA144 10 x10 T=LQFP64 10 x10 / H=LFBGA64 8 x 8 x 1.7
www.st.com

Contents STR71xF
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Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4 Pin Description for 144-Pin Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5 Pin description for 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.6 External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.7 I/O Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.8 Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.3.1 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.3.2 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.3.3 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.3.4 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.3.5 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.3.6 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.3.7 EMI - Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.3.8 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.9 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.1 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

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4 Product history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Note: For detailed information on the STR710 Microcontroller memory, registers and peripherals,
please refer to the STR710 Reference Manual.

Introduction STR71xF
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1 Introduction
This datasheet provides the STR71x Ordering Information, Mechanical and Electrical
Device Characteristics.
For complete information on the STR710 Microcontroller memory, registers and peripherals.
please refer to the STR710 Reference Manual.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STR7 Flash Programming Reference Manual
For information on the ARM7TDMI core please refer to the ARM7TDMI Technical Reference
Manual.
1.1 Overview
ARM®core with embedded Flash & RAM
The STR710 series is a family of ARM-powered 32-bit Microcontrollers with embedded
Flash and RAM. It combines the high performance ARM7TDMI CPU with an extensive
range of peripheral functions and enhanced I/O capabilities. STR71xF devices have on-chip
high-speed single voltage FLASH memory and high-speed RAM. STR710R devices have
high-speed RAM but no internal Flash. The STR710 family has an embedded ARM core
and is therefore compatible with all ARM tools and software.
Extensive tools support
STMicroelectronics’ 32-bit, ARM core-based microcontrollers are supported by a complete
range of high-end and low-cost development tools to meet the needs of application
developers. This extensive line of hardware/software tools includes starter kits and complete
development packages all tailored for ST’s ARM core-based MCUs. The range of
development packages includes third-party solutions that come complete with a graphical
development environment and an in-circuit emulator/programmer featuring a JTAG
application interface. These support a range of embedded operating systems (OS), while
several royalty-free OSs are also available.
For more information, please refer to ST MCU site http://www.st.com/mcu
Package Choice: Low Pin-Count 64-pin or Feature-Rich 144-pin LQFP or BGA
The STR710 family is available in 5 main versions.
The 144-pin versions have the full set of all features including CAN, USB and External
Memory Interface (EMI).
●STR710F: 144-pin BGA or LQFP with CAN, USB and EMI
●STR710R: Flashless 144-pin BGA or LQFP with CAN, USB and EMI (no internal Flash
memory)

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The three 64-pin versions (BGA or LQFP) do not include External Memory Interface.
●STR715F: 64-pin BGA or LQFP without CAN or USB
●STR711F: 64-pin BGA or LQFP with USB
●STR712F: 64-pin BGA or LQFP with CAN
High Speed Flash Memory (STR71xF)
The Flash program memory is organized in two banks of 32-bit wide Burst Flash memories
enabling true read-while-write (RWW) operation. Device Bank 0 is up to 256 Kbytes in size,
typically for the application program code. Bank 1 is 16K bytes, typically used for storing
data constants. Both banks are accessed by the CPU with zero wait states @ 33 MHz
Bank 0 memory endurance is 10K write/erase cycles and Bank 1 endurance is 100K
write/erase cycles. Data retention is 20 years at 85°C on both banks. The two banks can be
accessed independently in read or write. Flash memory can be accessed in two modes:
●Burst mode: 64-bit wide memory access at up to 50 MHz.
●Direct 32-bit wide memory access for deterministic operation at up to 33 MHz.
The STR7 embedded Flash memory can be programmed using In-Circuit Programming or
In-Application programming.
IAP (In-Application Programming): The IAP is the ability to re-program the Flash memory
of a microcontroller while the user program is running.
ICP (In-Circuit Programming): The ICP is the ability to program the Flash memory of a
microcontroller using JTAG protocol while the device is mounted on the user application
board.
The Flash memory can be protected against different types of unwanted access
(read/write/erase). There are two types of protection:
●Sector Write Protection
●Flash Debug Protection (locks JTAG access)
Refer to the STR7 Flash Programming Reference manual for details.
Optional External Memory (STR710)
The non-multiplexed 16-bit data/24-bit address bus available on the STR710 (144-pin)
supports four 16-Mbyte banks of external memory. Wait states are programmable
individually for each bank allowing different memory types (Flash, EPROM, ROM, SRAM
etc.) to be used to store programs or data.
Figure 1 shows the general block diagram of the device family.
Flexible Power Management
To minimize power consumption, you can program the STR710 to switch to SLOW, WAIT,
LPWAIT (low power wait), STOP or STANDBY mode depending on the current system
activity in the application.
Flexible Clock Control
Two external clock sources can be used, a main clock and a 32 kHz backup clock. The
embedded PLL allows the internal system clock (up to 66 MHz) to be generated from a main
clock frequency of 16 MHz or less. The PLL output frequency can be programmed using a
wide selection of multipliers and dividers. The microcontroller core, APB1 and APB2
peripherals are in separate clock domains and can be programmed to run at different
frequencies during application runtime. The clock to each peripheral is gated with an

Introduction STR71xF
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individual control bit to optimize power usage by turning off peripherals any time they are not
required.
Voltag e Regulators
The STR710 requires an external 3.0-3.6V power supply. There are two internal Voltage
Regulators for generating the 1.8V power supply for the core and peripherals. The main VR
is switched off during low power operation.
Low Voltage Detectors
Each voltage regulator has an embedded LVD that monitors the internal 1.8V supply. If the
regulated voltage drops below a certain threshold, the LVD will reset the STR710. This
enhances the security of the system by preventing the MCU from going into an
unpredictable state.
An external reset circuit must be used to provide the RESET at V33 power-up. It is not
sufficient to rely on the RESET generated by the LVD in this case. This is because LVD
operation is guaranteed only when V33 is within the specification.
1.2 On-Chip Peripherals
CAN Interface (STR710 and STR712)
The CAN module is compliant with the CAN specification V2.0 part B (active). The bit rate
can be programmed up to 1 MBaud.
USB Interface (STR710 and STR711)
The full-speed USB interface is USB V2.0 compliant and provides up to 16 bidirectional/32
unidirectional endpoints, up to 12 Mb/s (full-speed), support for bulk transfer, isochronous
transfers and USB Suspend/Resume functions.
Standard Timers
Each of the four timers have a 16-bit free-running counter with 7-bit prescaler
Three timers each provide up to two input capture/output compare functions, a pulse
counter function, and a PWM channel with selectable frequency.
The fourth timer is not connected to the I/O ports. It can be used by the application software
for general timing functions.
Realtime Clock (RTC)
The RTC provides a set of continuously running counters driven by the 32 kHz external
crystal. The RTC can be used as a general timebase or clock/calendar/alarm function.
When the STR710 is in Standby mode the RTC can be kept running, powered by the low
power voltage regulator and driven by the 32 kHz external crystal.
UARTs
The 4 UARTs allow full duplex, asynchronous, communications with external devices with
independently programmable TX and RX baud rates up to 1.25 Mb/s.
Smart Card Interface
UART1 is configurable to function either as a general purpose UART or as an asynchronous
Smart Card interface as defined by ISO 7816-3. It includes Smart Card clock generation and
provides support features for synchronous cards.

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Buffered Serial Peripheral Interfaces (BSPI)
Each of the two SPIs allow full duplex, synchronous communications with external devices,
master or slave communication at up to 5.5Mb/s in Master mode and 4 Mb/s in Slave mode.
I2C Interfaces
The two I2C Interfaces provide multi-master and slave functions, support normal and fast
I2C mode (400 kHz) and 7 or 10-bit addressing modes.
One I2C Interface is multiplexed with one SPI, so either 2xSPI+1x I2C or 1xSPI+2x I2C may
be used at a time.
HDLC interface
The High Level Data Link Controller (HDLC) unit supports full duplex operation and NRZ,
NRZI, FM0 or MANCHESTER protocols. It has an internal 8-bit baud rate generator.
A/D Converter
The Analog to Digital Converter, converts in single channel or up to 4 channels in single-
shot or round robin mode. Resolution is 12-bit with a sampling frequency of up to 1 kHz. The
input voltage range is 0-2.5V.
Watchdog
The 16-bit Watchdog Timer protects the application against hardware or software failures
and ensures recovery by generating a reset.
I/O Ports
The 48 I/O ports are programmable as Inputs or Outputs.
External Interrupts
Up to 14 external interrupts are available for application use or to wake-up the application
from STOP mode.

Introduction STR71xF
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Figure 1. STR710 Block Diagram
APB BUS
USBDP
USBDN
P0[15:0] I/O PORT 0
FLASH*
Program Memory
64/128/256K
I2C0
I2C1
BSPI0
BSPI1
UART0
UART1 /
UART2
UART3
USB
CAN
HDLC
APB
BRIDGE 1
APB
BRIDGE 2
APB BUS
TIMER1
TIMER2
TIMER3
RTC
EXT INT (XTI)
WATCHDOG
INTERRUPT CTL(EIC)
A/D
POWER SUPPLY
PRCCU/PLL
RAM
16/32/64K
JTAG
ARM7TDMI
CPU
EXT. MEM.
STDBY
2 AF
4 AF
4 AF
2 AF
3 AF
2 AF
2 AF
2 AF
3 AF
4 AF
4 AF
2 AF
4 AF
A[19:0]
D[15:0]
RDN
WEN[1:0]
RTCXTO
RTCXTI
WAKEUP
JTDI
JTCK
JTMS
JTRST
JTDO
CK
CKOUT
RSTIN
V18[1:0]
V33[6:0]
VSS[9:0]
V18BKP
14 AF
OSC
DBGRQS
BOOTEN
VREG
AVDD
AVSS
P1[15:0] I/O PORT 1
P2[15:0] I/O PORT 2
TIMER0
ARM7 NATIVE BUS
CS[3:0)
2 AF
1 AF
AF: alternate function on I/O port pin
INTERFACE (EMI)
A[23:20] (AF)
SMARTCARD
16K Data FLASH*
*Flash present in STR710F, not in STR710R

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1.3 Related Documentation
Available from www.arm.com:
ARM7TDMI Technical Reference Manual
Available from http://www.st.com:
STR71x Reference Manual
STR7 Flash Programming Reference Manual
AN1774 - STR710 Software development getting started
AN1775 - STR710 Hardware development getting started
AN1776 - STR710 Enhanced Interrupt Controller
AN1777 - STR710 Memory Mapping
AN1780 - Real Time Clock with STR710
AN1781 - Four 7 Segment Display Drive Using the STR710
The above is a selected list only, a full list STR71x application notes can be viewed at
http://www.st.com.

Introduction STR71xF
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1.4 Pin Description for 144-Pin Packages
Figure 2. STR710 LQFP Pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
P0.10/U1.RX/U1.TX/SCDATA
RDn
P0.11/U1.TX/BOOT.1
P0.12/SCCLK
VSS
V33
P2.0/CSn.0
P2.1/CSn.1
P0.13/U2.RX/T2.OCMPA
P0.14/U2.TX/T2.ICAPA
P2.2/CSn.2
P2.3/CSn.3
P2.4/A.20
P2.5/A.21
P2.6/A.22
BOOTEN
P2.7/A.23
P2.8
N.C.
N.C.
VSS
V33
P2.9
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
JTDI
JTMS
JTCK
JTDO
JTRSTn
NU
TEST
P1.14/HRXD/I0.SDA
P1.13/HCLK/I0.SCL
P1.10/USBCLK
P1.9
V33
VSS
A.4
A.3
A.2
A.1
A.0
D.1 5
D.1 4
D.1 3
D.1 2
D.1 1
D.1 0
USBDN
USBDP
P1.12/CANTX
P1.11/CANRX
N.C.
P1.8
P1.7/T1.OCMPA
VSSIO-PLL
V33IO-PLL
D.9
D.8
D.7
D.6
D.5
P1.6/T1.OCMPB
P1.5/T1.ICAPB
P1.4/T1.ICAPA
P1.3/T3.ICAPB/AIN.3
P1.2/T3.OCMPA/AIN.2
N.C.
TEST
N.C.
V33IO-PLL
N.C.
VSSIO-PLL
N.C.
DBGRQS
CKOUT
CK
P0.15/WAKEUP
N.C.
RTCXTI
RTCXTO
STDBY
RSTIN
N.C.
VSSBKP
V18BKP
N.C. N.C.
V18
VSS18
N.C.
D.0 D.1 D.2 D.3 D.4
AVDD
AVS S
N.C. N.C. N.C.
P1.0/T3.OCMPB/AIN.0
P1.1/T3.ICAPA/AIN.1
P0.9/U0.TX/BOOT.0 P0.8/U0.RX/U0.TX P0.7/S1.SSN P0.6/S1.SCLK P0.5/S1.MOSI VSS V33 WEn.0 WEn.1 A.19 A.18 A.17 A.16 A.15 A.14 V18 VSS18 P0.4/S1.MISO P0.3/S0.SSN/I1.SDA P0.2/S0.SCLK/I1.SCL P0.1/S0.MOSI/U3.RX P0.0/S0.MISO/U3.TX A.13 A.12 A.11 A.10 A.9 A.8 A.7 A.6 A.5 V33 VSS P1.15/HTXD N.C. N.C.
LQFP144