ST SPC570S Series Installation and operating instructions

February 2017 DocID030311 Rev 1 1/44
1
AN5010
Application note
SPC570Sx Getting Started
Introduction
The SPC570Sx devices family is built on Power Architecture®technology and is targeted for
ABS and airbag applications that require a high safety integrity level (ISO 26262 for ASIL-D
safety integrity).
In order to minimize additional software and module level features to reach this target, an
on-chip redundancy is offered for the critical components (see Functional Safety chapter of
RM) of the microcontroller by an e200z0Hn2p core, a DMA controller and an interrupt
controller in a delayed lockstep configuration, a crossbar bus system, a memory protection
unit, a fault collection and control unit (FCCU), Flash and SRAM with end-to-end error
correction coding (ECC) and End to end (E2E) protection on the data path and memory
ECC.
This family operates up to 80MHz and offers a high performance processing power specially
if compared with the previous family (SPC56) within a similar power envelope.
Some hardware in the new family also helps to prevent and control critical electronics
system faults and protects against harmful hacks.
This application note details the steps required to properly initialize the SPC570Sx devices
family from power-up to the code execution.
A development flow is described throughout the application note to explain the steps.
It is intended that this application note is read along with the SPC570Sx reference manual,
that can be obtained from the STMicroelectronics website at http://www.st.com (see
Section D.1: Reference documents).
www.st.com

Contents AN5010
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Contents
1 Application example description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Family architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Differences across sub-family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Reset and boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Boot from internal flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.1 Boot Header format and Boot search locations . . . . . . . . . . . . . . . . . . . 14
3.1.2 HW boot record search (SSCM search) . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.3 SW boot record search (BAF search) . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 SPC570Sx initialization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 Initialization steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 A valid Boot Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 Software Watchdog handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4 Core registers initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4.1 EABI Register initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4.2 Core Register initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5 Enable Branch Target Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.6 SRAM ECC Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.7 Environment Initializations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.8 XBAR Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.8.1 XBAR Registers configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.8.2 Flash Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.9 Memory Controllers configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.9.1 Flash Controller configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.9.2 SRAM wait State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.10 Mode Entry Module: Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.11 Clock and PLL configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5 Blink LED application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

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AN5010 Contents
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Appendix A Copy Initialized Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Appendix B Core registers initialization code . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Appendix C Clocks and PLLs Initialization example. . . . . . . . . . . . . . . . . . . . . . 39
Appendix D Further Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
D.1 Reference documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
D.2 Acronyms and abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

List of tables AN5010
4/44 DocID030311 Rev 1
List of tables
Table 1. Sub-Family features comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. Flash Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Boot record structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Boot record search locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Power Architecture EABI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Flash memory port assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 7. Acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 8. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

DocID030311 Rev 1 5/44
AN5010 List of figures
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List of figures
Figure 1. SPC570Sx Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. e200z0h block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Modules involved in Reset and Boot process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4. Processor Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. Core Execution flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6. e200z0h SUPERVISOR mode program model SPRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7. SRAM ECC Initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 8. Booting flow using GHS startup libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 9. Crossbar switch integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 10. 2-way, 4-entry mini-cache organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 11. Mode Entry Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 12. SPC570Sx Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 13. Blink LED application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Application example description AN5010
6/44 DocID030311 Rev 1
1 Application example description
This application note describes the necessary steps to configure the device in order to boot-
up from the Flash and run independent codes out of internal Flash.
This family (SPC57x) superseded the previous one (SPC56x): It is built on 55nm technology
and indeed apart from the technological point of view (55nm versus the older 90nm) it has
been designed to help the user to obtain an ISO26262 ASIL-D compliance for his
applications (see Section D.1: Reference documents).
SPC570Sx by default is configured so to replicate its safety-relevant processing elements
(Core, DMA/DMAMUX, Interrupt Controller) and compares its operation in lockstep (see
Section D.1: Reference documents).
Even if device works in lockstep (LockStep Mode or LSM), from an application perspective
the device behaves as a single core but the user has to take care of its initialization (core
registers, SRAM) to take into account safety architecture peculiarities.
The user can do these initialization by scratch or by using compilers support (through the
compiler property libraries) (see Figure 8: Booting flow using GHS startup libraries) that
allows the user to avoid some core register initializations (see also Section 4.4: Core
registers initialization) as well as the data copy of initialized data from the Flash to SRAM
(see Section 4.7: Environment Initializations) before the user code execution starts.
Note: Even if there are no limitations on the use of whatever compiler/toolchain, in this document
the GHS (Green Hills) syntax has been used where the code has been inserted as an
example.
1.1 Limitations
Since the scope of this document is an introduction on how to start to work with this devices
family, the initialization flow described doesn’t include any safety/security topics as well as it
doesn’t include any special memory handling like memory protection configurations (see
Section D.1: Reference documents).

DocID030311 Rev 1 7/44
AN5010 Family architecture
43
2 Family architecture
Two identical e200z0Hn2p processors (see Figure 1: SPC570Sx Block diagram) are used:
the main core, which executes the software application, and the safety core, linked to the
main core in delayed lock-step mode for ASIL-D safety requirements.
The e200z0h processor family is a CPU core that it implement cost-efficient versions of the
Power Architecture®. 
These processors are designed for deeply embedded control applications which require low
cost solutions rather than maximum performance (see Figure 2: e200z0h block diagram).
CPU is compatible with the Power Architecture VLE (Variable Length Encoding) instruction
set, that allows a mix of 16-bit and 32-bit instructions, for code size footprint reduction.
The processor interface to the external memory space is based on AMBA AHB2.v6
definition, with separate 32-bit data and instruction busses.
These memory busses are connected to the system memories and peripherals through a
32-bit crossbar (XBAR). The two e200z0h processors, the DMA and RAM run up to 80 MHz.
From a software perspective, every bus master (CPU and DMA) sees every memory and
peripheral (SRAM, Flash and peripherals) in a consistent, flat memory address space.
Figure 1.SPC570Sx Block diagram
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Family architecture AN5010
8/44 DocID030311 Rev 1
Figure 2. e200z0h block diagram
CPU
Control Logic
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Instruction Unit
Branch
Unit
PC
Unit
Instruction Buffer
GPR
CR
SPR
Multiply
Unit
Data Bus Interface Unit
Control
32 32 N
OnCE/Nexus
Control Logic
Interface
Control
Data
(MTSPR/MFSPR)
Integer
Execution
Unit
External
SPR
CTR
XER
LR
Data Address
Instruction Bus Interface Unit
Control
3232N
Nexus
Debug Unit

DocID030311 Rev 1 9/44
AN5010 Family architecture
43
2.1 Differences across sub-family
Table 1. Sub-Family features comparison
SPC570S40x SPC570S50x
Flash 256KB(1)
1. 128KB Block 0 and 128KB Block 1 excluded on SPC570S40x.
512KB
SRAM 32KB(2)
2. [0x4000_8000 - 0x4000_BFFF] out of complete [0x4000_0000 - 0x4000_BFFF] System RAM only
available on SPC570S50.
48KB
FlexCAN 1(3)
3. FlexCAN1 excluded on SPC570S40x.
2
Other aligned to Superset
Table 2. Flash Memory Map
Start Address End address Field RWW partition ID
0x0040_0000 0x0040_1FFF Flash 8 KB UTest block 1
0x0040_2000 0x0040_3FFF Reserved
0x0040_4000 0x0040_5FFF Flash 8 KB BAF block 1
0x0040_6000 0x0040_7FFF Reserved
0x0040_8000 0x0040_BFFF Flash 16 KB Test block(1) 1
0x0040_C000 0x007F_FFFF Reserved
0x0080_0000 0x0080_1FFF Flash 8 KB Data Block 0 2
0x0080_2000 0x0080_3FFF Flash 8 KB Data Block 1 2
0x0080_4000 0x0080_5FFF Flash 8 KB Data Block 2 2
0x0080_6000 0x0080_7FFF Flash 8 KB Data Block 3 2
0x0080_8000 0x00FB_FFFF Reserved
0x00FC_0000 0x00FC_3FFF Flash 16 KB Code Block 0 1
0x00FC_4000 0x00FC_7FFF Flash 16 KB Code Block 1 1

Family architecture AN5010
10/44 DocID030311 Rev 1
0x00FC_8000 0x00FC_BFFF Flash 16 KB Code Block 2 1
0x00FC_C000 0x00FC_FFFF Flash 16 KB Code Block 3 1
0x00FD_0000 0x00FD_7FFF Flash 32KB Code Block 0 1
0x00FD_8000 0x00FD_FFFF Flash 32KB Code Block 1 1
0x00FE_0000 0x00FE_FFFF Flash 64 KB Code Block 0 1
0x00FF_0000 0x00FF_FFFF Flash 64 KB Code Block 1 1
0x0100_0000 0x101_FFFF Flash 128 KB Code Block 0(2) 1
0x0102_0000 0x0103_FFFF Flash 128 KB Code Block 1(3) 1
0x0104_0000 0x3FFF_FFFF Reserved
1. The Test Flash Block is not accessible directly through the Flash controller. It can be accessed only
through a private bus by the SSCM module during the reset and by PASS module when a password match
comparison is requested. The table reports the test Flash Block address, as it were visible from the Flash
controller. In reality, the SSCM and PASS modules access the Test Flash block using the real Flash block
address, which is 0x80_0000 till 0x80_BFFF.
2. Flash Block excluded on SPC570Sx40.
3. Flash Block excluded on SPC570Sx40.
Table 2. Flash Memory Map (continued)
Start Address End address Field RWW partition ID