Teledyne Lecroy PXP500 PCI Express User manual

Introduction
Teledyne LeCroy's PXP500 PCI Express Test Platform x16 Link Width up to 32.0 GT/s provides a convenient, powerful and
flexible test platform for PCI Express devices at data rates up to 32.0 GT/s and link widths up to x16. The PXP500 Test
Platform allows the Summit Z5 Exercisers to act as a host system, enabling extensive protocol-level testing of PCIe®
devices at Gen5 speeds on the left side of the test platform. For use as a host emulator, the Summit Z5 Exerciser is
plugged into any slot and connected to an external power source. The DUT is plugged into the remaining available slot, the
PXP500 PCI Express Test Platform provides the necessary power up to 75W per slot. In addition to using the PXP500 Test
Platform with the Teledyne LeCroy Summit Z5, the user can connect two of their own devices and use the Test Platform as
a PCIe backplane by adding an interposer that will allow an analyzer to capture protocol traffic between the devices. The
right side of the PXP500 Test Platform can be used as a backplane for GenZ applications.
PXP500 PCI Express Test Platform


PXP500 PCI Express®Test Platform
x16 Link Width up to 32.0 GT/s
User Manual and Quick Start Guide
Use this document for quick installation and setup. If you
experience problems or need more information, see the
Summit Z5 User Manual at the Teledyne LeCroy web site.
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Components
The package includes the following components:
•PXP500 PCI Express Test Platform
•Stabilization bracket for DUTs and 2 thumbscrews
•Mounting bracket for Summit Z5 Controller module and
4 screws (optional installation)
•User Manual and Quick Start Guide (this document)
•AC power cord
•DUT bracket extension and 4 thumbscrews (optional
installation)
•GenZ bracket support and thumbscrews (optional
installation)
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Installation for PCIe Applications
Follow the procedure below when installing a Summit Z5 Exerciser and a Summit Z5 Controller for PCIe applications:
If you are testing a device other than a CEM based DUT, the installation steps are similar but the support bracket, controller,
exerciser and DUT face to the right.
1. Remove six large thumbscrews attached to the left side of the PXP500 Test Platform and position the PCIe Device
Support Bracket over the left side of the test platform. Then install and secure the Support bracket using six large
thumbscrews.
2. Install and secure the controller bracket into the PXP500 Test Platform using 4 Phillips head screws.
3. Position the Summit Z5 Controller, the Summit Z5 Exerciser and the DUT over the PXP500 Test Platform.
4. Plug the Summit Z5 Controller board into its bracket, plug the Summit Z5 Exerciser board into its slot near the control-
ler and plug the DUT board into the CEM slot. Secure the Exerciser and the DUT boards with a small thumbscrew to
attach it to the PCIe Device Support Bracket.
5. Attach the ribbon cable between the Summit Z5 Controller board and the Summit Z5 Exerciser board.
Note: See the Summit Z5 Exerciser documentation for more details on installation and connectivity.
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Unpacking the Test Platform
Inspect the received shipping container for any damage. Unpack the container and account for each of the system
components listed on the accompanying packing list. Visually inspect each component for absence of damage.
In the event of damage, notify the shipper and Teledyne LeCroy. Retain all shipping materials for shipper’s inspection.
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5
2

6
3
Summit Z5 Controller
module
Summit Z5 Exerciser
plug in card
PCIe DUT

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5
See note
below
Note: PCIe Device Support Bracket removed for clarity.
Summit Z5 Controller
cable

Installation of Bracket Extension
Install the bracket extension according to the illustration below. Adjust the height according to the requirements of the DUT
bracket.
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Installation for GenZ Applications
Follow the steps below when using the PXP500 Platform with GenZ devices applications.
1. Install the bracket on the side of the platform where the GenZ connectors are.
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2. Attach the GenZ bracket to the PXP500. This will allow to secure the GenZ DUT.

Switch Configuration and Connections
Clock Source Diagram
Table 1: 100MHz SSC Internal Clock Configuration
Table 2: Z5 Slot / DUT Slot Clock Source
Table 3: Z5 Slot / DUT Slot Clock Mode Configuration
SEL1 SEL0 Clock downspread amount (%)
Off Off No SSC (Default setting)
Off On -0.1 (1000 ppm)
On Off -0.3 (3000 ppm)
On On -0.5 (5000 ppm)
Z5 Slot External Clock for Z5 Slot comes from Ref Clk In connector
Internal Clock for Z5 Slot comes from Internal Clock (default setting)
DUT Slot External Clock for DUT Slot comes from Ref Clk In connector
Internal Clock for DUT Slot comes from Internal Clock (default setting)
Common Clock for Z5 Slot and DUT Slot are the same (default setting)
Separate (SRIS) Clock for Z5 Slot and the DUT Slot are separate and per source switch
(see Table 2)
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Table 6: Other Switches
DUT Power On Turn ON power to the DUT slot.
Off Turn OFF power to the DUT slot. Default setting. When the switch is OFF, an I2C
device with address 0x82 can be controlled from a Summit Exerciser through SMBus
to toggle the power in the DUT PCIe Connector. When the switch is ON, the I2C
device is disabled and will not interfere in the SMBus.
CLKREQ# Enable Allows CLKREQ# to control (turn on or off) the reference clock. If the switch is
enabled, the CLKREQ# signal must be asserted to have the clock turned on. If the
switch is enabled and the CLKREQ# signal is deasserted the clock is turned off (low
power mode).
Disable When the switch is in Disable position, the RefClk is always ON regardless of the
state of CLKREQ# signal on the bus.Default setting.
PWRDIS Enable Power Disable signal: Active high. When set to Enable the signal notifies the device
to turn off all systems connected to 12V power.
Disable When set to Disable, the PWRDIS signal has no effect on the system. Default setting.
Dual Port Enable Dual Port Enable signal: Active low. This signal indicates if dual port mode is
supported by the host.
Disable When set to Disable, the Dual Port signal has no effect on the system. Default
setting.
PERST# Momentary switch: When pressed causes PERST# signal to go low, resetting the system.
SMBRST# Momentary switch: When pressed causes SMBRST# signal to go low, resetting the SMBus
Table 4: Clock Input Specification
Table 5: Clock Output Specification
Parameter Specification
Peak to peak voltage level 300mV (Min), 500mV (Max)
Input interface level accepted To drive the 100MHz clock input the following sources can be used: 
CML, HCSL, LVPECL and LVDS. You should feed only one of the differential pair signals to
the input or they should convert the differential to single ended.
Nominal frequency 100 MHz
Parameter Specification
Peak to peak voltage level 400mV
Interface level LVDS
Nominal frequency 100 MHz