Teledyne Kibra DDR User manual

KibraDDR
ProtocolAnalyzerSuite
UserManual
SoftwareVersion2.40
DocumentVersion2.40
November2013

KibraDDRProtocolAnalyzerUserManual ii
TeledyneLeCroyProtocolSolutionsGroup
TrademarksandServicemarks
TeledyneLeCroy,KibraandBusEnginearetrademarksofTeledyneLeCroy,Inc.
MicrosoftandWindowsareregisteredtrademarksofMicrosoftCorporation.
IntelandPentiumareregisteredtrademarksofIntelCorporation.
Allothertrademarksandregisteredtrademarksarepropertyoftheirrespectiveowners.
THESPECIFICATIONSANDINFORMATIONREGARDINGTHEPRODUCTSINTHISMANUALARESUBJECTTOCHANGE
WITHOUTNOTICE.ALLINFORMATION,EXAMPLESANDRECOMMENDATIONSINTHISMANUALAREBELIEVEDTOBE
ACCURATEBUTAREREPRESENTEDWITHOUTWARRANTYOFANYKIND,EXPRESSORIMPLIED.USERSAREFULLY
RESPONSIBLEFORTHEIRAPPLICATIONOFANYPRODUCTS.
THESOFTWARELICENSEANDLIMITEDWARRANTYFORTHEACCOMPANYINGPRODUCTARESETFORTHIN
INFORMATIONTHATSHIPPEDWITHTHEPRODUCTANDAREINCORPORATEDHEREINBYTHISREFERENCE.IFYOUARE
UNABLETOLOCATETHESOFTWARELICENSEORLIMITEDWARRANTY,CONTACTTeledyneLeCroyFORACOPY.
©2011TeledyneLeCroy,Inc.Allrightsreserved.
Thisdocumentmaybeprintedandreproducedwithoutadditionalpermission,butallcopiesshouldcontainthiscopyright
notice.
WEEEProgram
TeledyneLeCroy
3385ScottBlvd.
SantaClara,CA95054
TEL:800‐909‐7112(USAandCanada)
TEL:408‐653‐1260(worldwide)

KibraDDRProtocolAnalyzerUserManual 1
Contents
Chapter 1: Introduction...........................................................................................9
1.1 Kibra 380 or Kibra 480 Overview........................................................................................... 9
1.1.1 Receiving Your Kibra 380 or Kibra 480 .......................................................................................................9
1.1.2 Unpacking the Kibra 380 or Kibra 480 ......................................................................................................10
1.1.3 Kibra 380 or Kibra 480 Features ................................................................................................................10
1.1.4 Difference between Kibra 380 or Kibra 480 ..............................................................................................11
CMD/ADD/CNTRL Bus and Process JEDEC Protocol ..................................................................... 11
Clock-Based Timing............................................................................................................................ 11
DIMM Slot Protocol ............................................................................................................................. 11
1.1.5 Trigger..........................................................................................................................................................11
1.1.6 Kibra 380 or Kibra 480 Front Panel ...........................................................................................................12
1.2 Specifications ....................................................................................................................... 13
1.2.1 Package........................................................................................................................................................13
1.2.2 Power Requirements ..................................................................................................................................13
1.2.3 EnvironmentalConditions .........................................................................................................................13
1.2.4 Switches.......................................................................................................................................................13
1.2.5 LEDs.............................................................................................................................................................13
1.2.6 Recording Memory Size .............................................................................................................................13
1.3 Installing Your Kibra 380 or Kibra 480 Protocol Analyzer................................................ 14
Software Installation........................................................................................................................... 14
System Restart.................................................................................................................................... 14
Error Message ..................................................................................................................................... 14
1.4 Hardware Setup .................................................................................................................... 14
1.4.1 Connecting in General................................................................................................................................14
Power on Procedure ........................................................................................................................... 17
1.5 DDR Interposer ..................................................................................................................... 17
1.5.1 Kibra 380 or Kibra 480 Slot 1 Interposer...................................................................................................18
1.5.2 Kibra 380 or Kibra 480 Slot 2 Interposer...................................................................................................19
1.5.3 External Trigger Out ...................................................................................................................................19
1.5.4 External Trigger In ......................................................................................................................................20
1.5.5 Low Latency Read/Write Trigger Out........................................................................................................20

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1.5.6 Daisy Chaining............................................................................................................................................21
Daisy Chaining.................................................................................................................................... 22
1.6 CrossSync Control Panel.....................................................................................................23
1.7 Launching Your Kibra 380 or Kibra 480 Software............................................................. 24
1.7.1 Establish Interface......................................................................................................................................25
1.7.2 About............................................................................................................................................................27
1.8 Using the Software............................................................................................................... 28
1.9 Protocol Analyzer................................................................................................................. 29
1.9.1 Viewing Captured Data...............................................................................................................................29
1.9.2 JEDEC Triggers...........................................................................................................................................30
Chapter 2: Protocol Analysis...............................................................................31
2.1 Main Window......................................................................................................................... 31
2.2 Software Menus and Toolbar............................................................................................... 32
2.3 Application Menu Options................................................................................................... 34
2.4 File.......................................................................................................................................... 34
2.5 Setup...................................................................................................................................... 35
2.6 Recording Options Setup .................................................................................................... 36
2.6.1 Recording Options - General Tab..............................................................................................................38
Product................................................................................................................................................. 38
Recording Type: Trigger Mode.......................................................................................................... 38
Snapshot Mode ................................................................................................................................... 38
Manual Trigger Mode.......................................................................................................................... 38
Event Trigger Mode............................................................................................................................. 39
Buffer Size ........................................................................................................................................... 39
Trigger Position................................................................................................................................... 39
Note...................................................................................................................................................... 40
Trace Filename & Path........................................................................................................................ 40
Capture................................................................................................................................................. 40
2.6.2 Recording Options - Basic Settings Tab ..................................................................................................42
DRAM Type.......................................................................................................................................... 45
LRDIMM Support................................................................................................................................. 45
Mirrored................................................................................................................................................ 45
ECC....................................................................................................................................................... 45
Encoded............................................................................................................................................... 45
Follow MRS Settings........................................................................................................................... 46
Memory Controller.............................................................................................................................. 47
Active Ranks........................................................................................................................................ 49
Active Banks........................................................................................................................................ 49

 KibraDDRProtocolAnalyzerUserManual 3
Contents  TeledyneLeCroy
Command Filter Out............................................................................................................................ 51
Timing Violation Trigger..................................................................................................................... 52
Handling Timing Violation in MPR states (DDR4)............................................................................ 57
Protocol Violation Trigger.................................................................................................................. 58
Alert Trigger (DDR4) ........................................................................................................................... 59
2.6.3 Recording Options - Advanced Triggers Tab...........................................................................................59
Command Trigger............................................................................................................................... 61
RCW/BCW Commands Trigger.......................................................................................................... 61
Read/Write Trigger.............................................................................................................................. 62
Sequence Trigger................................................................................................................................ 63
Clock Present...................................................................................................................................... 65
2.6.4 Recording Options - Memory Address Mapping Tab..............................................................................66
Read/Write on Specific Address Trigger .......................................................................................... 67
Decoding Read/Write Commands in Waveform/Listing View......................................................... 69
Search on System Address................................................................................................................ 70
2.7 Devices.................................................................................................................................. 70
2.8 CrossSync Control Panel.....................................................................................................71
2.8.1 Launching the CrossSync Control Panel .................................................................................................71
2.9 Preferences........................................................................................................................... 72
2.9.1 General.........................................................................................................................................................73
2.9.2 DDR3 Lines Properties...............................................................................................................................75
2.9.3 DDR4 Lines Properties...............................................................................................................................76
2.9.4 Symbol Coloring .........................................................................................................................................77
2.9.5 Waveform View ...........................................................................................................................................78
2.9.6 Listing View.................................................................................................................................................79
2.9.7 Bank State View ..........................................................................................................................................80
2.9.8 RTS View......................................................................................................................................................82
2.10 Reset Interposers ............................................................................................................... 83
2.11 Init Phy................................................................................................................................. 83
2.12 Session................................................................................................................................ 83
2.13 Analysis............................................................................................................................... 84
2.14 Waveform View................................................................................................................... 85
2.15 Listing View......................................................................................................................... 86
2.16 Bank State View.................................................................................................................. 87
2.17 Traffic Summary ................................................................................................................. 88
2.18 Timing Calculator View...................................................................................................... 88
2.19 Last MRS Values................................................................................................................. 89
2.20 Row Usage Report.............................................................................................................. 89
2.21 Timing Violation Analysis..................................................................................................90

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2.22 Trace Info............................................................................................................................. 93
2.22.1 Recording Options Summary ..................................................................................................................94
2.23 Navigation ........................................................................................................................... 94
2.24 View...................................................................................................................................... 95
2.25 Window................................................................................................................................ 95
2.26 Help...................................................................................................................................... 96
Tell Teledyne LeCroy.......................................................................................................................... 96
User Manual (F1)................................................................................................................................. 96
Video Tutorials.................................................................................................................................... 96
Display License Information .............................................................................................................. 96
Update License.................................................................................................................................... 97
Register Product Online..................................................................................................................... 97
Check for Updates .............................................................................................................................. 97
Shortcut List........................................................................................................................................ 97
About.................................................................................................................................................... 97
2.27 Example Files.................................................................................................................... 100
Run a Sample Analysis..................................................................................................................... 100
Saving a Trace................................................................................................................................... 102
Chapter 3: Viewer Display..................................................................................103
3.1 Window Management......................................................................................................... 103
3.2 Waveform View................................................................................................................... 103
3.2.1 Clock Position Selection..........................................................................................................................103
3.2.2 Viewport Slider in Navigation Bar ...........................................................................................................104
3.2.3 Snap to Edge.............................................................................................................................................105
3.2.4 Placing Cursors ........................................................................................................................................105
3.2.5 Zoom In and Zoom Out.............................................................................................................................106
3.2.6 Overlay Signals Mode...............................................................................................................................106
3.2.7 Zoom Box ..................................................................................................................................................107
3.2.8 Context Sensitive Menu ...........................................................................................................................109
3.2.9 Choosing Chip Select Color Highlighting...............................................................................................110
3.2.10 Timing and Protocol Violations.............................................................................................................111
3.2.11 Right-Click Functionality in Waveform View........................................................................................113
Go to Next Gap.................................................................................................................................. 114
Goes to the next gap (see See “Gap Markers” on page 129)........................................................ 114
Go to Previous Gap........................................................................................................................... 114
Go to Marker...................................................................................................................................... 114
Go to Cursor...................................................................................................................................... 114
Go to Trigger ..................................................................................................................................... 114
Go to Time ......................................................................................................................................... 114

 KibraDDRProtocolAnalyzerUserManual 5
Contents  TeledyneLeCroy
Go to Selection.................................................................................................................................. 114
Set New Marker ................................................................................................................................. 114
Set and Edit New Marker.................................................................................................................. 114
Place Marker...................................................................................................................................... 114
Edit This Marker................................................................................................................................ 114
Edit Marker......................................................................................................................................... 114
Go to Next Transition [Alert]............................................................................................................ 114
Go to Previous Transition [Alert]..................................................................................................... 114
Delete This Marker............................................................................................................................ 115
Delete Marker..................................................................................................................................... 115
Delete All Markers............................................................................................................................. 115
Add Lines........................................................................................................................................... 115
Delete Line [Alert] ............................................................................................................................. 115
Show/Hide Sub Signals.................................................................................................................... 115
Preferences........................................................................................................................................ 116
3.2.12 Markers ....................................................................................................................................................116
Creating Markers............................................................................................................................... 118
Signal Names Column...................................................................................................................... 119
Cursors .............................................................................................................................................. 119
3.3 Viewport Slider/Navigation Bar......................................................................................... 127
3.3.1 Traces Captured with Filtering Enabled .................................................................................................127
3.3.2 Gap Markers ..............................................................................................................................................129
3.4 Listing View......................................................................................................................... 130
3.5 Bank State View.................................................................................................................. 131
3.5.1 Supported States in the Bank View State...............................................................................................131
Legend Display.................................................................................................................................. 132
Active States...................................................................................................................................... 133
Configuring Visible Banks ............................................................................................................... 134
Common Features of Bank State View and Waveform View ........................................................ 134
3.5.2 Views..........................................................................................................................................................135
Maximum Zoomed In View............................................................................................................... 135
Default Zoom Level........................................................................................................................... 136
Maximum Zoomed Out View............................................................................................................ 136
3.6 Traffic Summary ................................................................................................................. 137
Traffic Summary - Toolbar Tools..................................................................................................... 137
Traffic Summary - Commands......................................................................................................... 138
Traffic Summary - Performance....................................................................................................... 140
Traffic Summary - Violations ........................................................................................................... 141
3.7 Timing Calculator View......................................................................................................142
3.8 Last MRS Values................................................................................................................. 143

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3.9 Row Usage Report............................................................................................................. 144
Defining Target Row(s)..................................................................................................................... 145
Define Analysis Detail Parameters.................................................................................................. 146
Define Report Boundary................................................................................................................... 147
Cyclic Row Usage Report................................................................................................................. 147
3.10 Timing Violation Reanalysis............................................................................................ 147
Chapter 4: Real Time Statistics .........................................................................149
4.1 Devices Dashboard ............................................................................................................ 149
4.2 Real-Time Statistics View .................................................................................................. 150
4.2.1 Real-Time Statistics Buttons ...................................................................................................................152
4.2.2 RTS Preferences .......................................................................................................................................153
4.2.3 RTS Print....................................................................................................................................................154
Appendix A: Application Note ...........................................................................155
5.1 DDR3 and DDR4 JEDEC Timing Violations Summary .................................................... 155
5.1.1 V01 - tRAS ACTIVATE to PRECHARGE command period (Min)...........................................................155
5.1.2 V02 - tRAS ACTIVATE to PRECHARGE command period (Max)..........................................................155
5.1.3 V03 - tRRD ACTIVATE to ACTIVATE command period (DDR3 different bank, same rank) (DDR4 - same bank group) ......156
5.1.4 V04 - tFAW Four Activate Window ..........................................................................................................156
5.1.5 V05 - tRCDx ACTIVATE to internal read or write delay (same bank) ...................................................156
5.1.6 V06 - tWTP WRITE to PRECHARGE delay..............................................................................................157
5.1.7 V07 - tRTPx READ to PRECHARGE delay ..............................................................................................157
5.1.8 V08 - tRP PRECHARGE to a Valid Command.........................................................................................157
5.1.9 V09 - tWRA WRA to a Valid Command....................................................................................................157
5.1.10 V10 - t RFC REFRESH to a Valid Command.........................................................................................158
5.1.11 V11 - tREFI REFRESH Interval...............................................................................................................158
5.1.12 V12 - tRTR READ to READ delay (DDR3 - same rank) (DDR4 - same bank group)...........................158
5.1.13 V13 - tdrRTR READ to READ delay (different rank - same DIMM)......................................................158
5.1.14 V14 - tddRTR READ to READ delay (different DIMM)..........................................................................158
5.1.15 V15 - tRTW READ to WRITE delay (same rank)....................................................................................159
5.1.16 V16 - tdrRTW READ to WRITE delay (different rank, same DIMM).....................................................159
5.1.17 V17 - tddRTW READ to WRITE delay (different DIMM)........................................................................159
5.1.18 V18 - tWTR WRITE to READ delay ( DDR3 - same rank) (DDR4 - same bank group) .......................159
5.1.19 V19 - tdrWTR WRITE to READ delay (different rank, same DIMM).....................................................159
5.1.20 V20 - tddWTR WRITE to READ delay (different DIMM)........................................................................159
5.1.21 V21 - tWTW WRITE to WRITE delay ( DDR3 - same rank) (DDR4 - same bank group).....................159
5.1.22 V22 - tddWTW WRITE to WRITE delay (different rank, same DIMM)..................................................160
5.1.23 V23 - tddWTW WRITE to WRITE delay (different DIMM)......................................................................160
5.1.24 V24 - tXS SELF REFRESH EXIT to a Valid Command (without DLL) .................................................160
5.1.25 V25 - tXSDLL SELF REFRESH EXIT to a Valid Command (with DLL)................................................160

 KibraDDRProtocolAnalyzerUserManual 7
Contents  TeledyneLeCroy
5.1.26 V26 - tCKESR SELF REFRESH ENTRANCE to SELF REFRESH EXIT................................................160
5.1.27 V27 - tACTPDEN ACTIVE to POWER DOWN ENTRY...........................................................................160
5.1.28 V28 - REFPDEN REFRESH to POWER DOWN ENTRY.........................................................................160
5.1.29 V30 - tPRPDEN PRECHARGE / PRECHARGE ALL to POWER DOWN ENTRY..................................161
5.1.30 V31 - tRDPDEN READ / READ AUTO to POWER DOWN ENTRY........................................................161
5.1.31 V32 - tWRPDEN WRITE to POWER DOWN ENTRY..............................................................................161
5.1.32 V33 - tWRAPDEN WRITE AUTO to POWER DOWN ENTRY ................................................................161
5.1.33 V34 - tXP POWER DOWN EXIT to a Valid Command without DLL.....................................................161
5.1.34 V35 - tXPDLL POWER DOWN EXIT to a Valid Command with DLL - DDR3.......................................161
5.1.35 V36 - tCKE Clock Enable minimum pulse width ..................................................................................162
5.1.36 V37 - tPD POWER DOWN ENTRY to POWER DOWN EXIT..................................................................162
5.1.37 V38 - tZQCS SHORT Calibration Sequence to a Valid Command ......................................................162
5.1.38 V39 - tZQOper ZQCL to a Valid Command............................................................................................162
5.1.39 V40 - tZQinit First ZQCL after Reset to a Valid Command..................................................................162
5.1.40 V41 - tMRD MODE Register Set to Mode Register Set.........................................................................162
5.1.41 V42 - tMOD Mode Register Set Command to a Valid Command ........................................................163
5.1.42 V43 - tXPR First Clock Enable High after Reset to MRS......................................................................163
5.1.43 V44 - CCD-S Read to Read Delay (short) Different bank group, same rank DDR4..........................163
5.1.44 V45 - tWTW-DBGWrite to Write Delay (short) Different bank group; same rankDDR4....................163
5.1.45 V46 - tWTR- DBGWrite to Read Delay (short) Different bank group; same rank DDR4...................163
5.1.46 V47 - tRRD-SActivate to Activate Delay (short) Different bank group; same rankDDR4 ................163
5.1.47 V48 - tXS-FAST SRX to a Valid Command with DLL- DDR4................................................................164
5.2 Supplemental Timing Information..................................................................................... 164
5.2.1 tWR WR (write recovery for auto-precharge).........................................................................................164
Appendix B: China Restriction of Hazardous Substances Table...................165
Appendix C: How to Contact Teledyne LeCroy................................................167
Index:.................................................................................................................. 169

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8KibraDDRProtocolAnalyzerUserManual

KibraDDRProtocolAnalyzerUserManual 9
Chapter1
Introduction
DDR3andDDR4arethethirdandfourthgenerationofDoubleDataRate(DDR)SDRAM
memory.ItisacontinuationoftheDDRmemorytechnologythatdelivershigherspeeds,
lowerpowerconsumptionandheatdissipation.Itisanidealmemorysolutionfor
bandwidthhungrysystemsequippedwithdualandquadcoreprocessors.
MemoryisutilizedinvirtuallyeveryelectronicdeviceandDDRmemoryhasbecomethe
memoryofchoice.EachgenerationofDDRmemoryhasdoubledthedataratewhile
reducingpowerrequirements.
1.1 Kibra 380 or Kibra 480 Overview
TheKibra380orKibra480ProtocolAnalyzerprovidesaplatformfordevelopingand
debuggingprotocolissuesinenvironmentswhichallowDDR3andDDR4probingusingthe
interposersconnectedtothefrontoftheKibrabox.
Currently,theInterposerProbestargetDIMMandSODIMMsocketsofvarioustypes.
ContactTeledyneLeCroyforthemostrecentofferingsofInterposers.
DDRCommand,controlsignalsandaddressvaluesarecaptured.NoactualDDRdata
signalsarecaptured.
1.1.1 Receiving Your Kibra 380 or Kibra 480
Theanalyzerpackageincludesthefollowingcomponents:
Kibra380orKibra480identifiedinthepackinglist
KibraQuickStartGuide
USBA‐B2.0cable,2meters
DDR3orDDR4Slot1Interposercableassemblywithpowerconnector,soldsepa‐
rately(UDIMMDDR3versionshownbelowasanexample)

TeledyneLeCroy Kibra380orKibra480Overview
10KibraDDRProtocolAnalyzerUserManual
DDR3orDDR4Slot2Interposercableassembly,soldseparately(UDIMMDDR3
versionshownbelowasanexample)
Three‐ProngAC12V,5Amppowerbrick
CATCSyncCable(DB‐9MaletoDB‐9F)
InstallationCD‐ROMwithsoftwareanddocumentation
1.1.2 Unpacking the Kibra 380 or Kibra 480
Inspectthereceivedshippingcontainerforanydamage.Unpackthecontainerand
accountforeachofthesystemcomponentslistedontheaccompanyingpackinglist.
Visuallyinspecteachcomponentforabsenceofdamage.Intheeventofdamage,notify
theshipperandTeledyneLeCroyCorporation.Retainallshippingmaterialsforshipper’s
inspection.
1.1.3 Kibra 380 or Kibra 480 Features
SupportstheJEDECspecification(JEDECdefinestheDDRspecification)
RecordsCMD/ADD/CNTRLbus
Clockbasedtimingdisplays
Fastupload
Largesamplecapture–4GBofRecordingMemory
~500MillionSamples
TriggersforJEDECtimingviolations
TriggersforJEDECprotocolviolations
Userselectablecommandtriggers
Userdefinabletriggersequence
DDR3andDDR4Analysis
Clockspeedsof400‐800MHz(Kibra380),400‐1200MHz(Kibra480)
DDR3andDDR4Transferspeedsof800‐1600MT/s(Kibra380),800‐2400MT/s
(Kibra480)
UDIMM/RDIMM/LRDIMM/SODIMMpassiveInterposer
Metricsonperformance,observederrors
ExternalTriggerIn&Out
ExternalRead/WriteTriggerOut
TeledyneLeCroyCrossSyncsupport

 KibraDDRProtocolAnalyzerUserManual 11
Kibra380orKibra480Overview TeledyneLeCroy
1.1.4 Difference between Kibra 380 or Kibra 480
1. Kibra480supportsbothDDR3andDDR4Interposers.Kibra380onlysupportsDDR3
interposers.
2. TheKibra380versionoftheinterposersrequiresastableDIMM_CLKtoproperly
sampletheDIMMsignals.IftheDIMM_CLKisnotrunning,theprobewillrequire
6usaftertheDIMM_CLKresumesbeforepropercaptureoccurs.Thiscanoccur
whenrecordingDDRtrafficduringplatformbootorduringselfrefreshmode.This
limitationcancauseRCandMRScommandstobemissed.
TheKibra480doesnothavethislimitation.
CMD/ADD/CNTRL Bus and Process JEDEC Protocol
TheAnalyzerobservesCMD/ADD/CNTRLbusandprocessesJEDECprotocolrequirements
inreal‐time.
ErrorscanbeseenintheWaveformviewortheListingsviewaswellasintheTraffic
Summary.ErrorslistedintheTrafficSummaryhaveaHyperlinkdirectlytotheWaveform
andListingviewtoallowquickviewingoferrors.
Clock-Based Timing
TheAnalyzerfeaturesclock‐basedtiming.Theclocktimesarebasedonthenominal
DIMMspeedselectedintheRecordingOptionsandsamplesaresynchronizedtothe
DIMMclock.
DIMM Slot Protocol
TheKibra380orKibra480areabletotracktheDIMMslotprotocol.Theyalsohavethe
optiontogathercontrolsignalsfromasecondDIMMslot.
1.1.5 Trigger
ProvidestriggersforCommandOrderingViolationsandStateViolationsaswellasuser
selectablecommandsorcommandsequences.Triggermarkersareaccurateto
clocksofthetriggeredevent.

TeledyneLeCroy Kibra380orKibra480Overview
12KibraDDRProtocolAnalyzerUserManual
1.1.6 Kibra 380 or Kibra 480 Front Panel
TheKibra380andKibra480havethefollowingfeaturesonthefrontpanel:
PowerLED
StatusLED
TriggerLED
Slots1and2forInterposers
InterposerPowerConnector
ReadandWriteSMAConnectors
Figure 1.1: Front Panel
OnthebacktheAnalyzershave:
ExternalTriggerInputandOutput
ReferenceClockIn
SyncInandOutConnectors
USBPortforhostmachineconnectivity
DCInput12‐volt,5Amps
PowerSwitch
Figure 1.2: Back Panel

 KibraDDRProtocolAnalyzerUserManual 13
Specifications TeledyneLeCroy
1.2 Specifications
1.2.1 Package
1.2.2 Power Requirements
1.2.3 Environmental Conditions
1.2.4 Switches
1.2.5 LEDs
TheLEDsilluminateasfollows:
1.2.6 Recording Memory Size
4GigabyteDRAMfortrafficdatacapture,timing,stateandotherdata
Dimensions 10.0x8.5x1.9inches
(25.5x21.5x4.8cm)
Connectors DCpowerconnection
TriggerIN/OUTinput(BNC)
hostmachineconnection(USB,typeB)
Dataconnector(DataIn/Out,9‐pinDB)
Weight 2.6lbs.(1.1kg)
InputPower 90to254VAC,47to63Hz(universal
input),100Wmaximum
Operating
Temperature
0to55°C(32to131°F)
StorageRange ‐20to80°C(‐4to176°F)
OperatingHumidity 10to90%,non‐condensing
OperatingAltitude Upto6560feet(2000meters)
Power on/off
LEDs Illumination Status
Power (Green) Analyzerispoweredon
Status (Red) Analyzerfailedtoboot
(SolidBlue) Analyzerisready
(FlashingBlue) Downloadingbusengine
Trigger (Yellow) Triggeroccurred

TeledyneLeCroy InstallingYourKibra380orKibra480ProtocolAnalyzer
14KibraDDRProtocolAnalyzerUserManual
1.3 Installing Your Kibra 380 or Kibra 480 Protocol Analyzer
Software Installation
ThesoftwareworksonsystemsusingtheWindows®XP,Windows8,andWindows732‐
or64‐bitoperatingsystems.
1. InserttheInstallationCD‐ROMintotheCDdriveonthehostmachine.
2. Theinstallationautomaticallystartssetup,unlessAutoRunisoff.Inthatcase,select
theCD‐ROMfrom“MyComputer”andclickSetup.
3. Afterthewarningtocloseallotherprogramsandbeforestartingtheinstallation,
theInstallcomponentselectionopens.
4. Selectcomponentsforinstallation.
5. ClickNexttocompletetheinstallation.
System Restart
ItisrecommendedthatyourestartyourhostmachinebeforeyouuseyourAnalyzer
software.
Error Message
IfyougetanerrormessageduringinstallationofthedriversforWindow,consultyour
systemadministrator.Yoursystemmayallowonlyadministrator‐leveluserstocopysuch
driverfiles.
1.4 Hardware Setup
1.4.1 Connecting in General
Note:Youmustinstallthesoftwarebeforeconnectingtheanalyzertothehostmachineforthefirst
time.
Tosetuptheanalyzer:
1. Connecttheanalyzertoa100V–240V,50Hz–60Hz,poweroutlet,usingthesupplied
12‐voltpowerbrick,andturnonthePowerswitch.
Atpoweron,theanalyzerwillgothroughinitializationasshownontheapplication
screen.
2. ConnecttheUSBcablebetweentheKibra380orKibra480andaUSBportonthe
hostmachine.Thehostmachine’soperatingsystemdetectstheanalyzeranddriver
files.

 KibraDDRProtocolAnalyzerUserManual 15
HardwareSetup TeledyneLeCroy
Figure 1.3: Analyzer Connections
3. Turnoffthehostmachine,protocolanalyzer,andHostUnderTest(HUT).
4. InserttheDDRSDRAMmemoryintotheDIMMsocketontheinterposertop(s).
12
3
3
44
55
6
67

TeledyneLeCroy HardwareSetup
16KibraDDRProtocolAnalyzerUserManual
5. InserttheDDRSlot1Interposer,and(ifdesired)DDRSlot2Interposer,intotheHUT
DIMM‐socketslot(s)farthestfromtheCPU.Onlyonechannelwithuptotwoslotsis
supportedwithasingleKibraDDRanalyzer.NormallytheDIMMconnectorsfortwo
slotsinthesamechannelonaPChavethesamecolor.
6. FortheSlot1Interposer,connecttheribboncabletoSlot1andthepowercableto
InterposerPower,bothonthefrontoftheprotocolanalyzer.
FortheSlot2Interposer,connecttheribboncabletoSlot2onthefrontofthe
protocolanalyzer.
IMPORTANT! Pleaseseethe“PoweronProcedure”onpage17beforeperformingstep
7.
7. Turnonthehostmachineandtheprotocolanalyzer.OpentheDDRProtocolSuite.
8. SelectRecordingOptionsunderSetupontheMenuBar.
9. SelecttheGeneraltabtodisplaythefactorydefaultsettings,suchasSnapshotand
30‐MBbuffersize.Usethedefaultsettings.
10. SelecttheDIMMParametersandViolationTriggerstab.IntheMemoryController
section,selectthepropertiesoftheDIMMtoanalyze,includingtheDIMMSpeed
andCASLatencies.UnchecktheTimingViolationTriggercheckboxtocancel
triggers.UnchecktheProtocolViolationTriggercheckboxtocanceltriggers.Click
OKtousethedefaultsforallothersettings.
11. TheHUTcanbeturnedoneithernoworafterrecordingstarts.
12. ClickStartRecording ontheToolBar.ThesystemstartstocaptureDDR
command,control,andaddresssignals.After30MBoftrafficarerecorded,the
Analyzeruploadsthedataanddisplaysthepackets.
13. Toterminaterecordingbeforethesnapshotautomaticallycompletes,clickStop
RecordingontheToolBar.
14. Whentherecordingsessionisfinished,thetrafficisautomaticallyuploadedfrom
theAnalyzertotheharddriveonyourhostmachineasafilenameddata.ddrt(or
thenameyouassignedasthedefaultfilename).Whilethefileisbeinguploaded,
youshouldseeaprogressbaratthebottomofthescreen.Whenthebar
disappears,itindicatesthatthedatahasbeenuploadedtodisk.
15. Tosaveacurrentrecordingforfuturereference,selectFile>SaveAs,orclick
ontheToolBar,todisplaythestandardSaveAsscreen.Givetherecordingaunique
nameandsaveittotheappropriatedirectory.

 KibraDDRProtocolAnalyzerUserManual 17
DDRInterposer TeledyneLeCroy
Power on Procedure
1. StarttheDDRProtocolSuiteapplication.
2. MakesuretheDDRInterposer(s)is/areattachedsecurelytotheKibraunit.
3. Verifythateither:
Interposersarenotinsertedintothesystemundertest.
OR
InterposersareinsertedintothesystemundertestANDpowerisOFFonthesystem
undertest.
4. PowerOntheKibraunitandwaituntilthePhy'shavecompletedinitialization.
5. PowerOnthesystemundertest.
1.5 DDR Interposer
TheKibraInterposerssitbetweentheHostUnderTest(HUT)DIMMslotsandtheDIMMS
undertest.Theinterposersaddlessthan1inchoftracelengthandaresistivetapto
minimizeeffectsonsignalqualitywhileensuringanadequatesignalfortheAnalyzer.
Figure 1.4: DDR Interposer
DIMM
Cable to Analyzer
DIMM Interposer

TeledyneLeCroy DDRInterposer
18KibraDDRProtocolAnalyzerUserManual
1.5.1 Kibra 380 or Kibra 480 Slot 1 Interposer
ProtocolCheckingisperformedonupto4ranks,inasingleslot.
Moderegistercaptureissupportedonupto8ranks,in1or2slots.TheKibra380Slot1
Interposerisshownbelow.
Figure 1.5: Slot 1 Interposer
Figure 1.6: Slot 1 Interposer with DIMM