Texas Instruments DLP Discovery 4100 User manual

User’s Guide
DLP® Discovery™ 4100 Development Platform
ABSTRACT
The DLP Discovery 4100 Development Platform, or D4100 Platform, is an evaluation platform to experiment
and develop with the DLP650LNIR, DLP7000, DLP9500, DLP7000UV, DLP9500UV, DLPC410, DLPR410 and
DLPA200 chips.
This platform targets applications needing:
• Fast binary pattern refresh rates up to 32 kHz
• High speed data rates up to 48Gbps
• Ultraviolet (UV) imaging from 363 nm to 420 nm
• Near infrared (NIR) imaging from 850 nm to 2000 nm
• Visible imaging from 400 nm to 700 nm
• Resolutions up to 1080p (approximately 2.1 megapixels)
Table of Contents
1 Introduction.............................................................................................................................................................................4
1.1 Welcome............................................................................................................................................................................ 4
2 Overview..................................................................................................................................................................................5
2.1 The DLP Discovery 4100 Development Platform...............................................................................................................6
2.2 DLP Discovery 4100 Development Platform Photo........................................................................................................... 8
2.3 Key Components................................................................................................................................................................9
3 Hardware Overview and Setup............................................................................................................................................ 12
3.1 Getting Started................................................................................................................................................................. 12
3.2 User Connectors and I/O................................................................................................................................................. 12
3.3 Configuration Jumpers..................................................................................................................................................... 26
3.4 Switches...........................................................................................................................................................................27
3.5 Power and Status LEDs................................................................................................................................................... 29
3.6 Test Points........................................................................................................................................................................30
4 Software.................................................................................................................................................................................31
4.1 Overview.......................................................................................................................................................................... 32
4.2 DLP Discovery 4100 Operation........................................................................................................................................33
4.3 Graphical User Interface.................................................................................................................................................. 39
4.4 Script and Status Operations........................................................................................................................................... 51
4.5 DLPC410 Control Window............................................................................................................................................... 53
4.6 Test Patterns Window...................................................................................................................................................... 54
4.7 About Box.........................................................................................................................................................................56
4.8 Links.................................................................................................................................................................................56
5 Related Documentation........................................................................................................................................................57
6 Appendix................................................................................................................................................................................58
6.1 Abbreviations and Acronyms........................................................................................................................................... 58
6.2 Notational Conventions.................................................................................................................................................... 58
7 Revision History................................................................................................................................................................... 60
List of Figures
Figure 2-1. D4100 Platform Diagram...........................................................................................................................................6
Figure 2-2. DLPLCRC410EVM connected to DLPLCR95EVM................................................................................................... 8
Figure 2-3. DLPLCRC410EVM Controller Board Key Components............................................................................................ 9
Figure 3-1. DLPLCRC410EVM Controller Connectors (Top View)............................................................................................12
Figure 3-2. DLPLCRC410EVM Controller Connectors (Bottom View)...................................................................................... 13
Figure 3-3. DLPLCRC410EVM Controller Configuration Jumpers............................................................................................ 26
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Figure 3-4. DLPLCRC410EVM On-Board Switches..................................................................................................................27
Figure 3-5. DLPLCRC410EVM Controller Board Indicators...................................................................................................... 29
Figure 3-6. DLPLCRC410EVM Test Point Locations.................................................................................................................30
Figure 4-1. Discovery 4100 Explorer GUI..................................................................................................................................31
Figure 4-2. Updating Driver Software........................................................................................................................................ 33
Figure 4-3. Browse for Driver Software..................................................................................................................................... 34
Figure 4-4. Pick from a list of Device Drivers.............................................................................................................................34
Figure 4-5. Select Universal Serial Bus devices........................................................................................................................35
Figure 4-6. Have Disk................................................................................................................................................................ 35
Figure 4-7. Browse for .inf file....................................................................................................................................................36
Figure 4-8. Select TI D4100 Explorer........................................................................................................................................ 36
Figure 4-9. Driver Installation Window.......................................................................................................................................37
Figure 4-10. Verify Device......................................................................................................................................................... 37
Figure 4-11. Discovery 4100 Explorer USB and DMD - Connection Status.............................................................................. 38
Figure 4-12. Graphical User Interface Layout............................................................................................................................39
Figure 4-13. Menu Bar...............................................................................................................................................................39
Figure 4-14. File Menu...............................................................................................................................................................40
Figure 4-15. View Menu.............................................................................................................................................................40
Figure 4-16. DMD Menu............................................................................................................................................................ 40
Figure 4-17. Execution Menu.....................................................................................................................................................41
Figure 4-18. Test Patterns Menu............................................................................................................................................... 42
Figure 4-19. Help Menu............................................................................................................................................................. 42
Figure 4-20. Toolbar...................................................................................................................................................................43
Figure 4-21. Script Commands Window.................................................................................................................................... 44
Figure 4-22. Load Tab................................................................................................................................................................45
Figure 4-23. Reset Tab.............................................................................................................................................................. 46
Figure 4-24. Clear Tab............................................................................................................................................................... 47
Figure 4-25. Float Tab................................................................................................................................................................48
Figure 4-26. Control Tab............................................................................................................................................................ 49
Figure 4-27. Status Window...................................................................................................................................................... 50
Figure 4-28. Script Window....................................................................................................................................................... 50
Figure 4-29. DLPC410 Control Window.................................................................................................................................... 53
Figure 4-30. Test Patterns Window............................................................................................................................................54
Figure 4-31. About Box..............................................................................................................................................................56
List of Tables
Table 2-1. D4100 Platform EVMs and DMD Types......................................................................................................................5
Table 3-1. J12 Input Power Pinout.............................................................................................................................................13
Table 3-2. J18 Input Power Pinout.............................................................................................................................................13
Table 3-3. J1 USB Pinout...........................................................................................................................................................14
Table 3-4. J3 USB GPIO............................................................................................................................................................14
Table 3-5. J6 GPIO_A Connector.............................................................................................................................................. 14
Table 3-6. J8 DLPC410 Mictor Connector................................................................................................................................. 15
Table 3-7. J9 USB/APPSFPGA Mictor Connector..................................................................................................................... 16
Table 3-8. J13 DMD Flex Connector 1.......................................................................................................................................17
Table 3-9. J14 DMD Flex Connector 2.......................................................................................................................................19
Table 3-10. J15 DDR2 SODIMM Connector.............................................................................................................................. 21
Table 3-11. J16 EXP-1 Connector..............................................................................................................................................22
Table 3-12. J16 EXP-1 Power and Ground Connections...........................................................................................................23
Table 3-13. J17 EXP-2 Connector............................................................................................................................................. 24
Table 3-14. J17 EXP-2 Power and Ground Connections...........................................................................................................25
Table 3-15. H1 Xilinx APPSFPGA JTAG Header.......................................................................................................................25
Table 3-16. EXP Voltage Select.................................................................................................................................................26
Table 3-17. APPSFPGA Revision Select...................................................................................................................................26
Table 3-18. Shared USB Signal Enable/Disable........................................................................................................................27
Table 3-19. DLPA200 B Output Enable......................................................................................................................................27
Table 3-20. SW1 Dip Switch Assignments.................................................................................................................................28
Table 3-21. DLPLCRC410EVM Test Point Net Names..............................................................................................................30
Table 4-1. DMD Characteristics................................................................................................................................................. 32
Table 4-2. SW1 Dip Switch Assignments...................................................................................................................................55
Trademarks
ActiveX™ is a trademark of ACTIVE NETWORK, LLC.
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All trademarks are the property of their respective owners.
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1 Introduction
This guide explains the hardware and software features of the DLP Discovery 4100 Development Platform
evaluation modules (EVMs). The EVM architectures and connectors are described along with a quick start guide
on how to operate the D4100 Platform using a PC based Graphical User Interface (GUI). Specific DLP chip
details and operation can be found in related component documentation.
1.1 Welcome
The DLP Discovery 4100 Development Platform is a great way to evaluate the fastest binary pattern and data
rates the DLP chip portfolio offers. Designers get pixel accurate control of all DMD micromirrors with Global,
Quad, Dual and Single Block Modes available for tailoring DMD micromirror pattern timing for continuous (lamp)
or solid state (switched) illuminated applications. The D4100 is also a path for customers to design with the high
performance UV and NIR DLP chips for systems such as:
• Lithography
• 3D printing and additive manufacturing
• Dynamic grayscale marking and coding
• Industrial printing
• Structured light such as:
– Factory automation and 3D machine vision
– 3D In-line automated optical inspection (AOI)
– Robotic vision
– Offline 3D metrology
– 3D scanners
– 3D identification and biometrics
• Medical and life sciences
• High speed imaging and display
WARNING
Hot Surfaces on the D4100 Controller Board near U11 and U5.
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2 Overview
DLP Discovery 4100 is a group of six evaluation modules which, when paired together, create a highly
flexible platform to learn, experiment and develop with DLP technology. At the heart of the platform is the
DLPLCRC410EVM controller board. The DLPLCRC410EVM board includes the DLPC410, DLPR410, DLPA200,
digital receiver, flash, power management circuits, and supporting digital logic. To give designers scalability
to port their DLP design work across multiple DMD devices, the DLPLCRC410EVM operates with any of the
following five DMD EVMs:
• DLPLCR65NEVM: includes DLP650LNIR DMD board, DLP650LNIR DMD, and one flex cable
• DLPLCR70EVM: includes the DLP7000 DMD board, DLP7000 DMD, and one flex cable
• DLPLCR70UVEVM: includes the DLP7000UV DMD board, DLP7000UV DMD, and one flex cable
• DLPLCR95EVM: includes the DLP9500 DMD board, DLP9500 DMD, and two flex cables
• DLPLCR95UVEVM: includes the DLP9500UV DMD board, DLP9500UV DMD, and two flex cables
When the DLPLCRC410EVM is connected to any of the DMD EVMs, the DLPC410, Applications FPGA, and
Software GUI recognizes and provides the proper signals and timing to the attached DMD. Out of the box, the
DLPLCRC410EVM delivers a small set of scrolling test patterns which allow customers to evaluate their optical
designs for related optical performance. When desired, these scrolling test patterns can be stopped keeping a
selected pattern constant. If these patterns are not sufficient, the PC-based software GUI can be used. The GUI
program allows binary pattern data to be downloaded via USB to the on-board Applications FPGA (APPSFPGA).
The Applications FPGA sends the data to the DLPC410 which then displays the image or pattern on the DMD.
The Xilinx Virtex 5 (LX50) APPSFPGA provides a user programmable platform for developing custom
applications. The APPSFPGA is connected to EXP Expansion Connectors for custom interfaces. An onboard
USB interface provides a convenient interface for development. Connections for DDR2 SODIMM memory and
SPI Flash Memory to the Application FPGA are also included. A Cypress CY7C68013A USB controller is
included for customer USB control applications. The source code for the APPSFPGA is provided on TI.COM to
provide VHDL savvy customers a reference to leverage for their own development.
Users of the D4100 have the ability to work with visible, UV and NIR light with pixel-level precision and fast
pattern rates. The D4100 offers developers a flexible platform to design products to fit many applications using
the proven reliability of DLP technology. As previously mentioned, the five DMD-based EVMs enable five distinct
DMD options: two in the visible spectrum, two in the UV spectrum, and one in the NIR spectrum. The EVMs,
DMDs, and select performance data are shown in Table 2-1:
Table 2-1. D4100 Platform EVMs and DMD Types
EVM DMD PRODUCT FOLDER DMD
COLUMNS
DMD
ROWS
RESET MAX BINARY PATTERN
RATE (Hz) DATA BUS
WIDTH
GLOBAL
RESET
PHASED
RESET
DLPLCR95EVM DLP9500 0.95 1080p 1920 1080 17,636 23,148 64
DLPLCR95UVEVM DLP9500UV 0.95 UV 1080p
DLPLCR70EVM DLP7000 0.7 XGA 1024 768 22,614 32,552 32
DLPLCR70UVEVM DLP7000UV 0.7 UV XGA
DLPLCR65NEVM DLP650LNIR .65 NIR WXGA 1280 800 10,800 12,500 16
The D4100 Platform combines the high performance D4100 chip set with a user programmable Application
FPGA (APPSFPGA).
The Xilinx Virtex 5 (LX50) APPSFPGA provides a user programmable platform for developing custom
applications. The APPSFPGA is connected to EXP Expansion Connectors for custom interfaces. An onboard
USB interface provides a convenient interface for rapid prototyping. Connections for DDR2 SO-DIMM memory
and SPI Flash Memory to the Application FPGA are included for customer use. A Cypress CY7C68013A USB
controller is included for customer USB control applications.
This document helps facilitate use of the D4100 Platform and provides a hardware reference design details for
DLPLCRC410EVM.
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2.1 The DLP Discovery 4100 Development Platform
The DLP Discovery 4100 Development Platform (D4100 Platform) typically refers to the combination of one
DLPLCRC410EVM plus one DMD EVM. Together these include:
• 1 ea. DLPLCRC410EVM Controller Board
• 1 ea. DMD board with DMD and DMD mounting mechanics (Type-A DMDs only)
• 1 ea. or 2 ea. flexible PCB cables
Not included in the kit but needed for operation are:
• 1 ea. Power supply: VOUT = 5 V, IOUT = 6 A (required)
Not included, optional and only needed if developing and downloading new APPSFPGA firmware:
• 1 ea. Xilinx DLC9G programming cable.
Figure 2-1 is a simplified block diagram of the D4100 Platform.
DLPLCR65NEVM
DLPLCR70EVM
DLPLCR70UVEVM
DLPLCR95EVM
DLPLCR95UVEVM
Cypress
USB
Cypress
PROM
I/O
Connectors:
MICTOR
EXP
JTAG
GPIO
Power
Connectors
Applications FPGA
(APPSFPGA)
64 Bit SODIMM
Connector
DLPC410
DLPA200
(B)
DLPA200
(A)
APPS FPGA
PROM DLPR410
PROM
FLEX 2 *
FLEX 1
* DLPLCR95(UV)EVMs only
DLPLCRC410EVM Controller Board
DMD EVMs
Figure 2-1. D4100 Platform Diagram
The DLP Discovery 4100 EVM Controller Board of the DLPLCRC410EVM contains:
• DLPC410 DLP Digital Controller
– Provides input high speed 16/32/64 bit 2xLVDS data and control user interface.
– Provides output data and control interface to the DMD and DLPA200s.
• DLPR410 Configuration PROM
– Stores and provides configuration data for the DLPC410 controller.
• DLPA200 DMD Micromirror Driver
– Generates Mirror Clocking Pulses (Resets) for up to 16 DMD Reset Blocks.
– Supports high reset frequencies.
– One required for DLP650LNIR, DLP7000, or DLP7000UV DMDs, and two for DLP9500, DLP9500UV
DMDs.
• 16/32/64-bit 400 MHz 2xLVDS DLPC410 to DMD Data Interface
– 16 bits used for the DLP650LNIR DMD.
– 32 bits used for the DLP7000 and DLP7000UV DMDs.
– 64 bits used for the DLP9500 and DLP9500UV DMDs.
• 5 Volt input power connector
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– On-board regulation of other power supplies included.
• Applications FPGA (APPSFPGA)
– Xilinx Virtex 5 (XC5VLX50) FPGA for user application pattern generation and development opportunities.
• APPSFPGA Configuration PROM (XCF16P)
– Stores and provides configuration data for the APPSFPGA. User programmable for future development.
• A 64-bit DDR2 SODIMM connector
– For end user development of image storage.
• A Cypress CY7C68013A USB controller
– Provides USB data and control interface (USB speeds can limit pattern rates).
– Enabled end user development of USB interface.
• EXP Expansion Connectors
– Connect to external EXP interface compatible customer boards.
– Includes additional 2xLVDS pairs to support 64 bit 2xLVDS connection through EXP connectors.
• Flash Memory (connected to APPSFPGA)
– Non-volatile storage for end user development.
• Various I/O connectors
– Mictor test connectors for logic analyzer connection.
– JTAG headers for device programming.
– GPIO connectors for general purpose digital I/O.
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2.2 DLP Discovery 4100 Development Platform Photo
When the DLPLCRC410EVM and the DLPLCR95EVM are assembled together, the combined D4100 Platform
is as shown in Figure 2-2. Other DMD EVMs connect to the DLPLCRC410EVM in a similar fashion and look
very similar, except the DLPLCRC410EVM only uses a single flex cable (Flex 1) for connection between the
Controller Board and the DMD Board.
Figure 2-2. DLPLCRC410EVM connected to DLPLCR95EVM
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2.3 Key Components
Figure 2-3 shows the D4100 Controller Board key components covered in this section.
GPIO
USB
Controller
50 MHz
Oscillator
Voltage
Regulators:
64 Bit DDR2
SO-DIMM
APPS
FPGA
PROM
Applications FPGA
EXP Connectors Mictor
DLPC410
DMD Connector 2
Mictor
DMD Connector 1
DLPA200
(B)
DLPA200
(A)
DLPR410
Battery
3.3 V
1.8 V
0.9 V
MBRST
MBRST
12 V
2.5 V
1.0 V
Figure 2-3. DLPLCRC410EVM Controller Board Key Components
2.3.1 Xilinx Virtex 5 APPSFPGA
The APPSFPGA (Xilinx Virtex 5 LX50) is used for development of interface and control solutions for the DMD.
The APPSFPGA is connected to a number of I/O connectors, interface controllers, and memory for use in
prototyping a custom control solution prior to developing a custom board solution.
2.3.2 DLPC410 - Digital Controller for DLP Discovery 4100 Chipset
The D4100 chipset includes the DLPC410 controller (configured Xilinx Virtex 5 LX30) which exposes a high-
speed 2xLVDS data and control interface for DMD control. This interface is connected to the APPSFPGA to
support control from the APPSFPGA. The DLPC410 generates DMD and DLPA200 initialization and control
signals in response to the inputs on the control interface.
For more information, refer to the DLPC410 data sheet - DLPS024.
2.3.3 DLPA200 - DMD Micromirror Driver
Two DLPA200 reset drivers provide the high voltage power and reset driver functions for the DMD. One
DLPA200 is required for the DLP650LNIR, DLP7000, or DLP7000UV DMDs, and two for the DLP9500 or
DLP9500UV DMDs. J11 is used to enable/disable the second DLPA200.
For more information on the DLPA200, refer to the DLPA200 data sheet - DLPS015.
2.3.4 DLPR410 - Configuration PROM for DLPC410 Controller
The D4100 chipset includes the DLPR410 controller which configures the DLPC410 (Xilinx Virtex 5 LX30). The
contents of this PROM must not be altered and must not be programmed!
For more information, refer to the DLPR410 data sheet - DLPS027.
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2.3.5 APPSFPGA Flash Configuration PROM
The PROM is used to store and configure the APPSFPGA. The PROM is a Xilinx XCF16P Flash PROM
pre-loaded with a test pattern generation capability. The APPSFPGA PROM programming can be changed by
customers as needed via a JTAG interface and a Xilinx programming tool. TI recommends downloading and
saving a copy of the pre-loaded test pattern generation program before reprogramming this PROM.
2.3.6 DMD Connectors
Two DMD Land Grid Array type connectors provide connections for two DMD flex cable. Connect a flex cable at
both J13 and J14 locations for connection to a DLPLCR95EVM or DLPLCR95UVEVM. Otherwise, connect only
one flex cable to J13 for connections to the DLPLCR70EVM, DLPLCR70UVEMV, and DLPLCR65NEVM.
2.3.7 USB Controller
A Cypress CY7C68013A USB controller is included for development of USB interface functions.
2.3.8 50-MHz Oscillator
The controller has a fixed 50-MHz, 2.5 Volt oscillator connected to the APPSFPGA for clock generation.
2.3.9 DDR2 SODIMM Connector
A 64-bit DDR2 SODIMM connector provides a high speed memory connection to the APPSFPGA. Memory
controller design for the APPSFPGA is not included. For a memory controller reference design, visit
www.xilinx.com.
2.3.10 Connectors
2.3.10.1 JTAG Header H1
The H1 JTAG header port provides a programming interface to the APPSFPGA and flash configuration PROM.
2.3.10.2 Mictor Connectors
The Mictor connectors support connection of a logic analyzer to the APPSFPGA and the Cypress CY7C68013A
signals for development support.
2.3.10.3 GPIO Connectors
General purpose digital I/O connectors.
2.3.11 Battery
A battery provides power for encryption security in the Virtex 5 FPGA. See Xilinx Virtex 5 data sheet for more
detail.
2.3.12 Power Supplies
Onboard voltage regulation is provided for all required power supplies. This section lists controller voltage
regulators and their purposes.
2.3.12.1 J14 Power Connector
The J14 power connector is the input power supply connector for the DLPLCRC410EVM controller board. For
proper operation, this power connector must be connected to a 5 VDC power supply capable of providing 30 W
of input power. This connector must not be used when connecting power through input power connector J14.
2.3.12.2 J14 Power Connector
The J14 power connector is the input power supply connector for the DLPLCRC410EVM controller board. For
proper operation, this power connector must be connected to a 5 VDC power supply capable of providing 30 W
of input power. This connector must not be used when connecting power through input power connector J14.
2.3.12.3 REG. 0.9 V
This delivers 1 A at 0.9 V as a DDR2 reference voltage supply.
2.3.12.4 REG. 1.0 V
This delivers 3 A at 1.0 V as the Virtex 5 core supply.
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2.3.12.5 REG. 1.8 V
This delivers 3 A at 1.8 V for the DDR2 supply and FPGA I/O.
2.3.12.6 REG. 2.5 V
This delivers 6 A at 2.5 V to supply the XCF16P FPGA I/O.
2.3.12.7 REG. 3.3 V
This delivers 3 A at 3.3 V to supply the DMD and USB controller.
2.3.12.8 REG. 12 V
This delivers the 0.5 A at 12 V to supply the DLPA200.
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3 Hardware Overview and Setup
3.1 Getting Started
The following steps must be followed in starting board operation using the default APPSFPGA code installed at
the factory:
1. Connect the desired DMD EVM to the DLPLCRC410EVM using the provided flex cables. A single flex cable
connects J13 to either the DLPLCR70EVM, DLPLCR70UVEVM, or the DLPLCR65NEVM. Two flex cables
attached to J13 and J14 are used for the DLPLCR95EVM and DLPLCR95UVEVM.
2. Confirm all SW1 switches are in the OFF position. Confirm all five J2 jumpers are in place. If using a
DLPLCR95EVM and DLPLCR95UVEVM confirm J10 is installed.
3. Connect a 5 Volt, 6 Amp power supply to either power input connector J12 or J18 (not both) with the power
supply OFF.
4. Turn the power supply ON and then slide SW4 to ON. D2 and D3 briefly illuminates to indicate the
APPSFPGA and DLPC410 Controller are being configured. Once configuration is complete, D2 and D3
turns off and D16 and D17 illuminates green. D9 flashes green at 1 Hz. D10 displays green. From this point,
the DMD repeatedly cycles through several test patterns.
To stop operation:
1. TI highly recommends to float the DMD mirrors to set the mirrors to a flat state before powering off. Press
SW3 to float the DMD.
2. Turn power OFF.
3.2 User Connectors and I/O
This section describes the use of each DLPLCRC410EVM Controller Board external connector and provides pin
out information. Figure 3-1 and Figure 3-2 show connector locations on the D4100 controller board.
J3, J6
GPIO
Connectors
J8
DLPC410 Mictor
Connector
J13, J14
DMD Flex
Connectors
J9
APPSFPGA Mictor
Connector
J1 USB
Connector
J12, J18
Input Power
Connectors
H1 JTAG
Figure 3-1. DLPLCRC410EVM Controller Connectors (Top View)
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J15 DDR2
SODIMM
J17 EXP2J16 EXP1
Figure 3-2. DLPLCRC410EVM Controller Connectors (Bottom View)
3.2.1 J12 Input Power Connector
Connector J12 accepts +5 VDC input power for the D4100 Platform. Do not use connectors J12 and J18
concurrently.
J12 is a DC Power Jack connector manufactured by CUI Inc., part number PJ-047BH, or equivalent.
Table 3-1. J12 Input Power Pinout
Pin Number Pin Name Description
1 +5V_IN +5 VDC input, 30W maximum. Pin 1 is center and is 2.5 mm ID and
5.5 mm OD.
2 GND Pins 2 and 3 are tied together to Ground
3 GND Pins 2 and 3 are tied together to Ground
3.2.2 J18 Input Power Connector
Connector J18 accepts +5 VDC input power for the D4100 Platform. Do not use connectors J18 and J12
concurrently.
J18 is a Molex connector, part number 043045-0412 or equivalent.
Table 3-2. J18 Input Power Pinout
Pin Number Pin Name Description
1 GND Ground
2 GND Ground
3 +5V_IN +5 VDC input, 30W maximum.
4 +5V_IN +5 VDC input, 30W maximum.
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3.2.3 J1 USB Connector Pinout
Connector J1 provides USB input to the controller board.
Table 3-3. J1 USB Pinout
Pin Number Pin Name Pin Number Pin Name
1 USB_5V 2 D–
3 D+ 4 NC
5 GND
3.2.4 J3 USB GPIO
Connector J3 provides eight general purpose USB I/O pin connections to the Cypress USB Controller. For more
information, see the Cypress CY7C68013A data sheet at www.cypress.com.
Table 3-4. J3 USB GPIO
Pin Number Pin Name Pin Number Pin Name
1 3.3 V 6 USB_GPIO B3
2 USB_GPIO B7 7 USB_GPIO B2
3 USB_GPIO B6 8 USB_GPIO B1
4 USB_GPIO B5 9 USB_GPIO B0
5 USB_GPIO B4 10 GND
3.2.5 J6 GPIO_A Connector
Connector J6 provides eight general purpose I/O pins to the APPSFPGA.
Table 3-5. J6 GPIO_A Connector
Pin Number Pin Name APPSFPGA Pin
Number
Pin Number Pin Name APPSFPGA Pin
Number
1 2.5 V NC 6 GPIO_A3 AG16
2 GPIO_A7 AF20 7 GPIO_A2 AG17
3 GPIO_A6 AF19 8 GPIO_A1 AH19
4 GPIO_A5 AG12 9 GPIO_A0 AG20
5 GPIO_A4 AH12 10 GND NC
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3.2.6 J8 DLPC410 Mictor Connector
J8 provides connection to the DLPC410 for a logic analyzer. This connector must not be used for normal
development or operation.
Table 3-6. J8 DLPC410 Mictor Connector
J8 Pin Number Pin Name DLPC410 Pin
Number
J8 Pin Number Pin Name DLPC410 Pin
Number
1 NC NC 2 ECP2_M_TP0 AD9
3 GND NC 4 ECP2_M_TP1 AA11
5 DDCSPARE0 L7 6 ECP2_M_TP2 W11
7 DDCSPARE1 AC13 8 ECP2_M_TP3 AB26
9 NC NC 10 ECP2_M_TP4 AB9
11 NC NC 12 ECP2_M_TP5 AB11
13 ECP2_M_TP31 AA13 14 ECP2_M_TP6 AA10
15 ECP2_M_TP3O AB13 16 ECP2_M_TP7 AA12
17 ECP2_M_TP29 AD14 18 ECP2_M_TP8 Y11
19 ECP2_M_TP28 L5 20 ECP2_M_TP9 AB17
21 ECP2_M_TP27 AC14 22 ECP2_M_TP10 AA17
23 ECP2_M_TP26 AB15 24 ECP2_M_TP11 AA15
25 ECP2_M_TP25 H19 26 ECP2_M_TP12 AF12
27 ECP2_M_TP24 J18 28 ECP2_M_TP13 AE11
29 ECP2_M_TP23 H18 30 ECP2_M_TP14 AC9
31 ECP2_M_TP22 G15 32 ECP2_M_TP15 AF11
33 ECP2_M_TP21 G14 34 ECP2_M_TP16 AB12
35 ECP2_M_TP20 H17 36 ECP2_M_TP17 AA16
37 ECP2_M_TP19 G20 38 ECP2_M_TP18 AD13
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3.2.7 J9 USB/APPSFPGA Mictor Connector
J9 is the Mictor connector for the USB controller and APPSFPGA. Signals from the USB or APPSFPGA are
routed to the connector as selected by jumper J6. Refer to the D4100 controller board schematic (DLPC410
Board Design Files) for more information. Signals can be routed to the connector by HDL code and monitored
with a logic analyzer to support development.
Table 3-7. J9 USB/APPSFPGA Mictor Connector
J9 Pin Number Pin Name APPSFPGA Pin
Number
J9 Pin Number Pin Name APPSFPGA Pin
Number
1 NC NC 2 NC NC
3 GND NC 4 D4100_I2C_CLK P29
5 USB_IF_CLK/
TEST_CLK_0
N29 6 D4100_I2C_DATA U28
7 USB_FDO/
TST_HDR_BY0_0
H29 8 GPIFADR0/
TST_HDR_BY2_0
K31
9 USB_FD1/
TST_HDR_BY0_1
H30 10 GPIFADR1/
TST_HDR_BY2_1
L31
11 USB_FD2/
TST_HDR_BY0_2
J31 12 GPIFADR2/
TST_HDR_BY2_2
P31
13 USB_FD3/
TST_HDR_BY0_3
G30 14 GPIFADR3/
TST_HDR_BY2_3
P30
15 USB_FD4/
TST_HDR_BY0_4
J30 16 GPIFADR4/
TST_HDR_BY2_4
N30
17 USB_FD5/
TST_HDR_BY0_5
G31 18 GPIFADR5/
TST_HDR_BY2_5
M31
19 USB_FD6/
TST_HDR_BY0_6
J29 20 GPIFADR6/
TST_HDR_BY2_6
R28
21 USB_FD7/
TST_HDR_BY0_7
F29 22 GPIFADR7/
TST_HDR_BY2_7
R29
23 USB_FD8/
TST_HDR_BY1_0
K29 24 GPIFADR8/
TST_HDR_BY3_0
T31
25 USB_FD9/
TST_HDR_BY1_1
F30 26 USB_CTRL0/
TST_HDR_BY3_1
R31
27 USB_FD1O/
TST_HDR_BY1_2
L30 28 USB_CTRL1/
TST_HDR_BY3_2
U30
29 USB_FD11/
TST_HDR_BY1_3
F31 30 USB_CTRL2/
TST_HDR_BY3_3
T30
31 USB_FD12/
TST_HDR_BY1_4
L29 32 USB_CTRL3/
TST_HDR_BY3_4
T28
33 USB_FD13/
TST_HDR_BY1_5
E29 34 USB_FPGA_RESET/
TST_HDR_BY3_5
T29
35 USB_FD14/
TST_HDR_BY1_6
E31 36 USB_INT5/
TST_HDR_BY3_6
U27
37 USB_FD15/
TST_HDR_BY1_7
M30 38 NC NC
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3.2.8 J13 DMD Flex 1 Connector
Connector J13 provides control and data signals to the DMD Flex 1 connector. This connector is used for
connection to all DMD types.
Table 3-8. J13 DMD Flex Connector 1
Pin Number Pin Name Pin Number Pin Name Pin Number Pin Name
1A GND 1B 3.3 V 1C 3.3 V
2C GND 2A DDC_DOUT_A13_DPP 2B DDC_DOUT_A13_DPN
3A GND 3B DDC_DOUT_A11_DPP 3C DDC_DOUT_A11_DPN
4C GND 4A DDC_DOUT_A9_DPP 4B DDC_DOUT_A9_DPN
5A GND 5B DDC_DCLKOUT_A_DPP 5C DDC_DCLKOUT_A_DPN
6C GND 6A DDC_DOUT_A7_DPP 6B DDC_DOUT_A7_DPP
7A GND 7B DDC_DOUT_A5_DPP 7C DDC_DOUT_A5_DPN
8C GND 8A DDC_DOUT_A3_DPP 8B DDC_DOUT_A3_DPN
9A GND 9B DDC_DOUT_A1_DPP 9C DDC_DOUT_A1_DPN
10C GND 10A DAD_A_SCPDO 10B DAD_A_SCPCLK
11A GND 11B DMDSPARE1 11C DMD_A_SCPEN
12C GND 12A MBRST1_15 12B MBRST1_14
13A GND 13B DMD_VCC2 13C DMD_VCC2
14C GND 14A MBRST1_10 14B MBRST1_6
15A GND 15B MBRST1_9 15C MBRST1_7
16C GND 16A MBRST1_13 16B MBRST1_12
17A GND 17B DDC_DOUT_B1_DPP 17C DDC_DOUT_B1_DPN
18C GND 18A DDC_DOUT_B3_DPP 18B DDC_DOUT_B3_DPN
19A GND 19B DDC_DOUT_B5_DPP 19C DDC_DOUT_B5_DPN
20C GND 20A DDC_DOUT_B7_DPP 20B DDC_DOUT_B7_DPN
21A GND 21B DDC_DCLKOUT_B_DPP 21C DDC_DCLKOUT_B_DPN
22C GND 22A DDC_DOUT_B9_DPP 22B DDC_DOUT_B9_DPN
23A GND 23B DDC_DOUT_B11_DPP 23C DDC_DOUT_B11_DPN
24C GND 24A DDC_DOUT_B13_DPP 24B DDC_DOUT_B13_DPN
25A GND 25B DDC_DOUT_B15_DPP 25C DDC_DOUT_B15_DPN
1D GND 1E DDC_DOUT_A15_DPP 1F DDC_DOUT_A15_DPN
2F GND 2D DDC_DOUT_A14_DPP 2E DDC_DOUT_A14_DPN
3D GND 3E DDC_DOUT_A12_DPP 3F DDC_DOUT_A12_DPN
4F GND 4D DDC_DOUT_A10_DPP 4E DDC_DOUT_A10_DPN
5D GND 5E DDC_DOUT_A8_DPP 5F DDC_DOUT_A8_DPN
6F GND 6D DDC_SCTRL_A_DPP 6E DDC_SCTRL_A_DPN
7D GND 7E DDC_DOUT_A6_DPP 7F DDC_DOUT_A6_DPN
8F GND 8D DDC_DOUT_A4_DPP 8E DDC_DOUT_A4_DPN
9D GND 9E DDC_DOUT_A2_DPP 9F DDC_DOUT_A2_DPN
10F GND 10D DDC_DOUT_A0_DPP 10E DDC_DOUT_A0_DPN
11D GND 11E SCPDI 11F DMD_A_RESET
12F GND 12D DMDSPARE0 12E MBRST1_11
13D GND 13E MBRST1_5 13F MBRST1_4
14F GND 14D MBRST1_0 14E MBRST1_3
15D GND 15E MBRST1_2 15F MBRST1_8
16F GND 16D DDC_DOUT_B0_DPP 16E DDC_DOUT_B0_DPN
17D GND 17E DDC_DOUT_B2_DPP 17F DDC_DOUT_B2_DPN
18F GND 18D DDC_DOUT_B4_DPP 18E DDC_DOUT_B4_DPN
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Table 3-8. J13 DMD Flex Connector 1 (continued)
Pin Number Pin Name Pin Number Pin Name Pin Number Pin Name
19D GND 19E DDC_DOUT_B6_DPP 19F DDC_DOUT_B6_DPN
20F GND 20D DDC_SCTRL_B_DPP 20E DDC_SCTRL_B_DPP
21D GND 21E DDC_DOUT_B8_DPP 21F DDC_DOUT_B8_DPN
22F GND 22D DDC_DOUT_B10_DPP 22E DDC_DOUT_B10_DPN
23D GND 23E DDC_DOUT_B12_DPP 23F DDC_DOUT_B12_DPN
24F GND 24D DDC_DOUT_B14_DPP 24E DDC_DOUT_B14_DPN
25D GND 25E 3.3 V 25F 3.3 V
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3.2.9 J14 DMD Flex 2 Connector
Connector J14 provides control and data signals to the DMD Flex 2 connector. This connector is only used for
connection to DLP9500 and DLP9500UV DMDs.
Table 3-9. J14 DMD Flex Connector 2
Pin Number Pin Name Pin Number Pin Name Pin Number Pin Name
1A GND 1B 3.3 V 1C 3.3 V
2C GND 2A DDC_DOUT_C13_DPP 2B DDC_DOUT_C13_DPN
3A GND 3B DDC_DOUT_C11_DPP 3C DDC_DOUT_C11_DPN
4C GND 4A DDC_DOUT_C9_DPP 4B DDC_DOUT_C9_DPN
5A GND 5B DDC_DCLKOUT_C_DPP 5C DDC_DCLKOUT_C_DPN
6C GND 6A DDC_DOUT_C7_DPP 6B DDC_DOUT_C7_DPP
7A GND 7B DDC_DOUT_C5_DPP 7C DDC_DOUT_C5_DPN
8C GND 8A DDC_DOUT_C3_DPP 8B DDC_DOUT_C3_DPN
9A GND 9B DDC_DOUT_C1_DPP 9C DDC_DOUT_C1_DPN
10C GND 10A DAD_B_SCPDO 10B DAD_B_SCPCLK
11A GND 11B DMDSPARE2 11C DMD_B_SCPEN
12C GND 12A MBRST2_15 12B MBRST2_14
13A GND 13B DMD_VCC2 13C DMD_VCC2
14C GND 14A MBRST2_10 14B MBRST2_6
15A GND 15B MBRST2_9 15C MBRST2_7
16C GND 16A MBRST2_13 16B MBRST2_12
17A GND 17B DDC_DOUT_D1_DPP 17C DDC_DOUT_D1_DPN
18C GND 18A DDC_DOUT_D3_DPP 18B DDC_DOUT_D3_DPN
19A GND 19B DDC_DOUT_D5_DPP 19C DDC_DOUT_D5_DPN
20C GND 20A DDC_DOUT_D7_DPP 20B DDC_DOUT_D7_DPN
21A GND 21B DDC_DCLKOUT_D_DPP 21C DDC_DCLKOUT_D_DPN
22C GND 22A DDC_DOUT_D9_DPP 22B DDC_DOUT_D9_DPN
23A GND 23B DDC_DOUT_D11_DPP 23C DDC_DOUT_D11_DPN
24C GND 24A DDC_DOUT_D13_DPP 24B DDC_DOUT_D13_DPN
25A GND 25B DDC_DOUT_D15_DPP 25C DDC_DOUT_D15_DPN
1D GND 1E DDC_DOUT_C15_DPP 1F DDC_DOUT_C15_DPN
2F GND 2D DDC_DOUT_C14_DPP 2E DDC_DOUT_C14_DPN
3D GND 3E DDC_DOUT_C12_DPP 3F DDC_DOUT_C12_DPN
4F GND 4D DDC_DOUT_C10_DPP 4E DDC_DOUT_C10_DPN
5D GND 5E DDC_DOUT_C8_DPP 5F DDC_DOUT_C8_DPN
6F GND 6D DDC_SCTRL_C_DPP 6E DDC_SCTRL_C_DPN
7D GND 7E DDC_DOUT_C6_DPP 7F DDC_DOUT_C6_DPN
8F GND 8D DDC_DOUT_C4_DPP 8E DDC_DOUT_C4_DPN
9D GND 9E DDC_DOUT_C2_DPP 9F DDC_DOUT_C2_DPN
10F GND 10D DDC_DOUT_C0_DPP 10E DDC_DOUT_C0_DPN
11D GND 11E SCPDI 11F DMD_B_RESET
12F GND 12D DMDSPARE0 12E MBRST2_11
13D GND 13E MBRST2_5 13F MBRST2_4
14F GND 14D MBRST2_0 14E MBRST2_3
15D GND 15E MBRST2_2 15F MBRST2_8
16F GND 16D DDC_DOUT_D0_DPP 16E DDC_DOUT_D0_DPN
17D GND 17E DDC_DOUT_D2_DPP 17F DDC_DOUT_D2_DPN
18F GND 18D DDC_DOUT_D4_DPP 18E DDC_DOUT_D4_DPN
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Table 3-9. J14 DMD Flex Connector 2 (continued)
Pin Number Pin Name Pin Number Pin Name Pin Number Pin Name
19D GND 19E DDC_DOUT_D6_DPP 19F DDC_DOUT_D6_DPN
20F GND 20D DDC_SCTRL_D_DPP 20E DDC_SCTRL_D_DPP
21D GND 21E DDC_DOUT_D8_DPP 21F DDC_DOUT_D8_DPN
22F GND 22D DDC_DOUT_D10_DPP 22E DDC_DOUT_D10_DPN
23D GND 23E DDC_DOUT_D12_DPP 23F DDC_DOUT_D12_DPN
24F GND 24D DDC_DOUT_D14_DPP 24E DDC_DOUT_D14_DPN
25D GND 25E 3.3 V 25F 3.3 V
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