Ublox SARA-R5 Series Quick setup guide

UBX-19041356 - R04
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SARA-R5 series
LTE-M / NB-IoT modules with secure cloud
System integration manual
Abstract
This document describes the features and the integration of the size-optimized SARA-R5 series
cellular modules, based on the u-blox UBX-R5 cellular chipset. The modules are specifically designed
for IoT, integrating an in-house developed cellular modem, end-to-end trusted domain security and
u-blox’s leading GNSS technology. The modules deliver high performance satellite positioning
alongside data connectivity in the very small and compact SARA form factor.

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Document information
Title
SARA-R5 series
Subtitle
LTE-M / NB-IoT modules with secure cloud
Document type
System integration manual
Document number
UBX-19041356
Revision and date
R04
12-Oct-2020
Disclosure restriction
C1-Public
Product status
Corresponding content status
Functional sample
Draft
For functional testing. Revised and supplementary data will be published later.
In development /
Prototype
Objective specification
Target values. Revised and supplementary data will be published later.
Engineering sample
Advance information
Data based on early testing. Revised and supplementary data will be published later.
Initial production
Early production information
Data from product verification. Revised and supplementary data may be published later.
Mass production /
End of life
Production information
Document contains the final product specification.
This document applies to the following products:
Product name
Type number
Modem version
Application version
PCN reference
Product status
SARA-R500S
SARA-R500S-00B-00
02.05
A00.01
UBX-20037360
Initial production
SARA-R510S
SARA-R510S-00B-00
02.05
A00.01
UBX-20037360
Initial production
SARA-R510M8S
SARA-R510M8S-00B-00
02.05
A00.01
UBX-20037360
Initial production
u-blox or third parties may hold intellectual property rights in the products, names, logos and designs included in this
document. Copying, reproduction, modification or disclosure to third parties of this document or any part thereof is only
permitted with the express written permission of u-blox.
The information contained herein is provided “as is” and u-blox assumes no liability for its use. No warranty, either express or
implied, is given, including but not limited to, with respect to the accuracy, correctness, reliability and fitness for a particular
purpose of the information. This document may be revised by u-blox at any time without notice. For the most recent
documents, visit www.u-blox.com.
Copyright © u-blox AG.

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Contents
Document information................................................................................................................................ 2
Contents ..........................................................................................................................................................3
1System description...............................................................................................................................6
1.1 Overview........................................................................................................................................................ 6
1.2 Architecture .................................................................................................................................................8
1.3 Pin-out .......................................................................................................................................................... 11
1.4 Operating modes....................................................................................................................................... 15
1.5 Supply interfaces ...................................................................................................................................... 16
1.5.1 Module supply input (VCC) ............................................................................................................. 16
1.5.2 Generic digital interfaces supply output (V_INT)....................................................................... 19
1.6 System function interfaces ....................................................................................................................20
1.6.1 Module power-on ..............................................................................................................................20
1.6.2 Module power-off..............................................................................................................................23
1.6.3 Module reset ......................................................................................................................................25
1.7 Antenna interfaces...................................................................................................................................26
1.7.1 Cellular antenna RF interface (ANT).............................................................................................26
1.7.2 GNSS antenna RF interface (ANT_GNSS)...................................................................................27
1.7.3 Cellular antenna detection interface (ANT_DET) ......................................................................28
1.8 SIM interface..............................................................................................................................................28
1.8.1 SIM card interface ............................................................................................................................28
1.8.2 SIM card detection interface (GPIO5)...........................................................................................28
1.9 Data communication interfaces ............................................................................................................29
1.9.1 UART interfaces................................................................................................................................29
1.9.2 USB interface.....................................................................................................................................37
1.9.3 SPI interfaces ....................................................................................................................................37
1.9.4 SDIO interface ...................................................................................................................................38
1.9.5 DDC (I2C) interface...........................................................................................................................38
1.10 Audio............................................................................................................................................................38
1.11 General purpose input / output (GPIO) .................................................................................................39
1.12 Reserved pin (RSVD) ................................................................................................................................39
2Design-in................................................................................................................................................ 40
2.1 Overview......................................................................................................................................................40
2.2 Supply interfaces ...................................................................................................................................... 41
2.2.1 Module supply (VCC)........................................................................................................................ 41
2.2.2 Generic digital interfaces supply output (V_INT).......................................................................52
2.3 System functions interfaces ..................................................................................................................53
2.3.1 Module power-on (PWR_ON) ..........................................................................................................53
2.3.2 Module reset (RESET_N).................................................................................................................54
2.4 Antenna interfaces...................................................................................................................................55
2.4.1 General guidelines for antenna interfaces ..................................................................................55

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2.4.2 Cellular antenna RF interface (ANT).............................................................................................59
2.4.3 GNSS antenna RF interface (ANT_GNSS)...................................................................................65
2.4.4 Cellular and GNSS RF coexistence................................................................................................69
2.4.5 Cellular antenna detection interface (ANT_DET) ...................................................................... 72
2.4.6 Cellular antenna dynamic tuning control interface ...................................................................74
2.5 SIM interface..............................................................................................................................................76
2.5.1 Guidelines for SIM circuit design ...................................................................................................76
2.5.2 Guidelines for SIM layout design .................................................................................................. 80
2.6 Data communication interfaces ............................................................................................................ 81
2.6.1 UART interfaces................................................................................................................................ 81
2.6.2 USB interface.....................................................................................................................................88
2.6.3 SPI interfaces ....................................................................................................................................88
2.6.4 SDIO interface ...................................................................................................................................89
2.6.5 DDC (I2C) interface...........................................................................................................................89
2.7 Audio............................................................................................................................................................ 91
2.8 General purpose input / output (GPIO) .................................................................................................92
2.8.1 Guidelines for GPIO circuit design .................................................................................................92
2.8.2 Guidelines for general purpose input/output layout design ....................................................93
2.9 Reserved pin (RSVD) ................................................................................................................................93
2.10 Module placement ....................................................................................................................................93
2.11 Module footprint and paste mask .........................................................................................................94
2.12 Schematic for SARA-R5 series module integration ..........................................................................95
2.13 Design-in checklist....................................................................................................................................96
2.13.1 Schematic checklist.........................................................................................................................96
2.13.2 Layout checklist................................................................................................................................97
2.13.3 Antennas checklist...........................................................................................................................97
3Handling and soldering ..................................................................................................................... 98
3.1 Packaging, shipping, storage and moisture preconditioning ..........................................................98
3.2 Handling ......................................................................................................................................................98
3.3 Soldering .....................................................................................................................................................99
3.3.1 Soldering paste .................................................................................................................................99
3.3.2 Reflow soldering................................................................................................................................99
3.3.3 Optical inspection...........................................................................................................................100
3.3.4 Cleaning ............................................................................................................................................100
3.3.5 Repeated reflow soldering .............................................................................................................101
3.3.6 Wave soldering.................................................................................................................................101
3.3.7 Hand soldering .................................................................................................................................101
3.3.8 Rework ...............................................................................................................................................101
3.3.9 Conformal coating ...........................................................................................................................101
3.3.10 Casting...............................................................................................................................................101
3.3.11 Grounding metal covers ................................................................................................................ 102
3.3.12 Use of ultrasonic processes ......................................................................................................... 102

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4Approvals..............................................................................................................................................103
4.1 Product certification approval overview.............................................................................................103
4.2 US Federal Communications Commission notice............................................................................ 104
4.2.1 Safety warnings review the structure ........................................................................................104
4.2.2 Declaration of Conformity.............................................................................................................105
4.2.3 Modifications...................................................................................................................................105
4.3 Innovation, Science, Economic Development Canada notice ........................................................106
4.3.1 Declaration of Conformity.............................................................................................................106
4.3.2 Modifications................................................................................................................................... 107
4.4 European Conformance.........................................................................................................................108
4.5 GITEKI Japan ........................................................................................................................................... 109
5Product testing .................................................................................................................................. 110
5.1 u-blox in-series production test ............................................................................................................110
5.2 Test parameters for OEM manufacturers..........................................................................................110
5.2.1 “Go / No go” tests for integrated devices.....................................................................................111
5.2.2 Cellular RF functional tests ............................................................................................................111
5.2.3 GNSS RF functional tests ..............................................................................................................112
Appendix ...................................................................................................................................................... 113
AMigration between SARA modules.............................................................................................. 113
BGlossary ................................................................................................................................................ 113
Related documents .................................................................................................................................. 116
Revision history..........................................................................................................................................117
Contact......................................................................................................................................................... 118

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1System description
1.1 Overview
The SARA-R5 series LTE Cat M1 / NB2 modules are ideal solutions for IoT, in the miniature SARA LGA
form factor (26.0 x 16.0 mm, 96-pin). They allow an easy integration into compact designs and a
seamless drop-in migration from other u-blox cellular module families.
SARA-R5 series modules are form-factor compatible with u-blox LISA, LARA and TOBY cellular
module families and are pin-to-pin compatible with u-blox SARA-R4, SARA-N, SARA-G and SARA-U
cellular module families. This facilitates migration from u-blox cellular modules supporting various
radio access technologies, maximizes customer investments, simplifies logistics, and enables very
short time-to-market. See Table 1 for a summary of the main features and interfaces.
Model
Region
RAT
Positioning
Interfaces
Features
Grade
3GPP Release Baseline
3GPP LTE category
LTE FDD bands
Integrated GNSS receiver
External GNSS control via modem
AssistNow software
CellLocate®
UART
USB (for diagnostics)
SPI
SDIO
DDC (I2C)
GPIOs
Digital audio (I2S)
Secure Cloud services Ver 1.1
Embedded Secure Element EAL5+ High certified
Antenna dynamic tuning
CellTime®
Ultra-low power consumption in PSM
Embedded TCP/UDP stack
Embedded HTTP, FTP
Embedded TLS, DTLS
FW update via serial (FOAT)
u-blox Firmware update Over the Air (uFOTA)
LwM2M with dynamically loaded objects
Embedded MQTT, MQTT-SN
Embedded CoAP
Last gasp
Jamming detection
Antenna and SIM detection
Standard
Professional
Automotive
SARA-R500S
Multi
Region
14
M1
NB2
*
●
●
●
●
●
○
○
●
●
○
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
SARA-R510S
Multi
Region
14
M1
NB2
*
●
●
●
●
●
○
○
●
●
○
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
SARA-R510M8S
Multi
Region
14
M1
NB2
*
●
●
●
●
●
○
○
●
●
○
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
* = LTE Bands 1, 2, 3, 4, 5, 8, 12, 13, 18, 19, 20, 26, 28 in M1 and NB2, LTE band 25 in M1-only, and LTE bands 66, 71, 85 in NB2-only
●= supported by all FW versions ○= supported by future FW versions
Table 1: SARA-R5 series main features summary
☞The “00” products version of the SARA-R5 series modules do not support LTE category NB2.
With a discrete, hardware-based secure element and a lightweight pre-shared key management
system, u-blox offers state-of-the-art security that is ideal for IoT applications and includes local data
protection, zero touch provisioning, anti-cloning, and local secure chip-to-chip communication.
SARA-R5 series modules are the optimal choice for LPWA applications with low to medium data
throughput rates, as well as devices that require long battery lifetimes, such as used in smart
metering, smart cities, telematics, and connected health.
The modules support handover capability and delivers the technology necessary for use in
applications such as vehicle, asset and people tracking where mobility is a pre-requisite. Other
applications where the modules are well-suited include and are not limited to: smart home, security
systems, industrial monitoring and control.

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The modules support multi-band data communication over an extended operating temperature range
of –40 to +85 °C, with extremely low power consumption, and with coverage enhancement for deeper
range into buildings and basements (and underground with NB2).
SARA-R5 series modules include the following variants / product versions:
•SARA-R500S LTE Cat M1 / NB2 module for multi-region use, cost effective solution for devices
that do not need to reach ultra-low power consumption in deep-sleep power saving mode (PSM)
•SARA-R510S LTE Cat M1 / NB2 module for multi-region use, designed to achieve extremely low
current consumption in deep-sleep power saving mode (PSM)
•SARA-R510M8S LTE Cat M1 / NB2 module for multi-region use, integrating the u-blox M8 GNSS
receiver for global position acquisition
Table 2 summarizes cellular and GNSS characteristics of the modules.
Item
SARA-R500S
SARA-R510S
SARA-R510M8S
Cellular protocol stack
3GPP release 14
3GPP release 14
3GPP release 14
Cellular RAT
LTE Cat M1 Half-Duplex
LTE Cat NB2 Half-Duplex
LTE Cat M1 Half-Duplex
LTE Cat NB2 Half-Duplex
LTE Cat M1 Half-Duplex
LTE Cat NB2 Half-Duplex
Cellular LTE FDD bands
Band 1 (2100 MHz)
Band 2 (1900 MHz)
Band 3 (1800 MHz)
Band 4 (1700 MHz)
Band 5 (850 MHz)
Band 8 (900 MHz)
Band 12 (700 MHz)
Band 13 (750 MHz)
Band 18 (850 MHz)
Band 19 (850 MHz)
Band 20 (800 MHz)
Band 25 (1900 MHz) 1
Band 26 (850 MHz)
Band 28 (700 MHz)
Band 66 (1700 MHz) 2
Band 71 (600 MHz) 2
Band 85 (700 MHz) 2
Band 1 (2100 MHz)
Band 2 (1900 MHz)
Band 3 (1800 MHz)
Band 4 (1700 MHz)
Band 5 (850 MHz)
Band 8 (900 MHz)
Band 12 (700 MHz)
Band 13 (750 MHz)
Band 18 (850 MHz)
Band 19 (850 MHz)
Band 20 (800 MHz)
Band 25 (1900 MHz) 1
Band 26 (850 MHz)
Band 28 (700 MHz)
Band 66 (1700 MHz) 2
Band 71 (600 MHz) 2
Band 85 (700 MHz) 2
Band 1 (2100 MHz)
Band 2 (1900 MHz)
Band 3 (1800 MHz)
Band 4 (1700 MHz)
Band 5 (850 MHz)
Band 8 (900 MHz)
Band 12 (700 MHz)
Band 13 (750 MHz)
Band 18 (850 MHz)
Band 19 (850 MHz)
Band 20 (800 MHz)
Band 25 (1900 MHz) 1
Band 26 (850 MHz)
Band 28 (700 MHz)
Band 66 (1700 MHz) 2
Band 71 (600 MHz) 2
Band 85 (700 MHz) 2
Cellular power class
LTE power class 3 (23 dBm)
LTE power class 3 (23 dBm)
LTE power class 3 (23 dBm)
Cellular data rate
LTE category M1:
up to 1200 kbit/s UL
up to 375 kbit/s DL
LTE category NB2:
up to 140 kbit/s UL
up to 125 kbit/s DL
LTE category M1:
up to 1200 kbit/s UL
up to 375 kbit/s DL
LTE category NB2:
up to 140 kbit/s UL
up to 125 kbit/s DL
LTE category M1:
up to 1200 kbit/s UL
up to 375 kbit/s DL
LTE category NB2:
up to 140 kbit/s UL
up to 125 kbit/s DL
GNSS receiver
-
-
72-channel u-blox M8 engine
GPS L1C/A, SBAS L1C/A,
QZSS L1C/A, QZSS L1-SAIF,
GLONASS L10F, BeiDou B1I,
Galileo E1B/C
Table 2: SARA-R5 series modules cellular and GNSS characteristics summary
☞The “00” products version of the SARA-R5 series modules do not support LTE category NB2.
☞See Table 46 for the detailed list of RATs and bands included in each certification approval of the
SARA-R5 series modules product versions.
1
Not supported in LTE category NB2
2
Not supported in LTE category M1

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1.2 Architecture
Figure 1, Figure 2 and Figure 3 summarize the internal architecture of the SARA-R500S modules,
SARA-R510S modules, and SARA-R510M8S modules, respectively.
V_INT (I/O)
VCC (supply)
ANT_DET
ANT
Flash memory
SIM
I2S
GPIOs
Reset
Power-on
UART
USB
DDC (I2C)
PA
UBX-R5
Cellular chipset
Base Band
processor
Power
Management
Unit
RF transceiver
Filter
Filter
Switch
SPI
SDIO
Secure element
(eSIM)
32 kHz
26 MHz
TCXO
Figure 1: SARA-R500S block diagram
V_INT (I/O)
VCC (supply)
ANT_DET
ANT
Flash memory
SIM
I2S
GPIOs
Reset
Power-on
UART
USB
DDC (I2C)
PA
UBX-R5
Cellular chipset
Base Band
processor
Power
Management
Unit
RF transceiver
Filter
Filter
Switch
SPI
SDIO
Secure element
(eSIM)
RTC
32 kHz
26 MHz
TCXO
Figure 2: SARA-R510S block diagram

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ANT_GNSS
V_INT (I/O)
VCC (supply)
ANT_DET
ANT
Flash memory
SIM
I2S
GPIOs
Reset
Power-on
UART
USB
DDC (I2C)
PA
UBX-R5
Cellular chipset
Base Band
processor
Power
Management
Unit
RF transceiver
Filter
Filter
Switch
SAW LNA UBX-M8
GNSS chipset
SPI
SDIO
Secure element
(eSIM)
32 kHz
26 MHz
TCXO
Figure 3: SARA-R510M8S block diagram
☞The “00” product version of the SARA-R5 series modules do not support the following interfaces,
which should be left unconnected and should not be driven by external devices:
oSPI interface
oSDIO interface
oDigital audio (I2S) interface
SARA-R5 series modules internally consist of the following sections described herein with more
details than the simplified block diagrams of Figure 1, Figure 2 and Figure 3.
RF section
The RF section is composed of the following main elements:
•RF switch connecting the antenna port (ANT) to the suitable RF Tx / Rx paths for LTE Cat M1 / NB2
Half-Duplex operations
•Power Amplifiers (PA) amplifying the Tx signal modulated and pre-amplified by the RF transceiver
•RF filters along the Tx and Rx signal paths providing RF filtering
•RF transceiver integrated in the u-blox UBX-R5 cellular chipset, performing modulation,
up-conversion and pre-amplification of the baseband signals for LTE transmission, and
performing down-conversion and demodulation of the RF signal for LTE reception
•26 MHz Temperature-Controlled Crystal Oscillator (TCXO) generating the reference clock signal
for the cellular RF transceiver, the Base-Band system and the GNSS system, when the related
system is in active mode or connected mode.

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Base-Band and Power Management section
The Base-Band and Power Management section, based on the u-blox UBX-R5 cellular chipset, is
composed of the following main elements:
•On-chip modem processor, vector signal processor, with dedicated hardware assistance for signal
processing and system timing
•On-chip modem processor, with interfaces control functions
•On-chip voltage regulators to derive all the internal or external (V_SIM, V_INT) supply voltages
from the module supply input VCC
•On-chip cryptographic hardware acceleration with Root of Trust
•On-chip memory system, including pSRAM and secure boot ROM
•Dedicated flash memory IC
•Dedicated secure element
•32.768 kHz crystal oscillator to provide the clock reference in the low power idle mode, which can
be enabled using the +UPSV AT command, and in the PSM deep-sleep mode, which can be enabled
using the +CPSMS in addition to the +UPSV AT command
GNSS section
The GNSS section, based on the u-blox UBX-M8 GNSS chipset, is composed of the following main
elements illustrated in Figure 4:
•u-blox UBX-M8030 concurrent GNSS chipset with SPG 3.01 firmware version
•Dedicated SAW filter
•Additional Low Noise Amplifier (LNA)
•26 MHz Temperature-Controlled Crystal Oscillator (TCXO) generating the reference clock signal
for the cellular RF transceiver, the Base-Band system and the GNSS system
ANT_GNSS
UBX-R5
Cellular chipset
Base Band
processor
Power
Management
RF
transceiver
SAW LNA UBX-M8030
GNSS chipset
26 MHz
TCXO
LNA_EN (PIO16)
RF_IN Tx-Ready(PIO14)
I2C (PIO8/PIO9)
Ext-Int (PIO13)
Time-Pulse (PIO11)
V_BCKPVCC 26 MHz
RTC
32 kHz
SQI
Flash
memory
SARA-R510M8S
I2C
Main UART
Auxiliary UART
VCC
Time pulse (GPIO6)
Ext-Int (EXT_INT)
Figure 4: SARA-R510M8S modules GNSS section block diagram

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1.3 Pin-out
Table 3 lists the pin-out of the SARA-R5 series modules, with pins grouped by function.
Function
Pin name
Pin no.
I/O
Description
Remarks
Power
VCC
51, 52, 53
I
Module supply input
VCC supply circuit affects the RF performance and compliance
of the device integrating the module with applicable required
certification schemes.
See section 1.5.1 for functional description / requirements.
See section 2.2.1 for external circuit design-in.
GND
1, 3, 5, 14,
20-22, 30,
32, 43,
50, 54,
55, 57-61,
63-96
N/A
Ground
GND pins are internally connected to each other.
External ground connection affects the RF and thermal
performance of the device.
See section 1.5.1for functional description.
See section 2.2.1 for external circuit design-in.
V_INT
4
O
Generic digital
interfaces supply
output
V_INT = 1.8 V (typical) generated by internal regulator when the
module is switched on, outside the low power PSM deep-sleep
mode.
See section 1.5.2 for functional description.
See section 2.2.2 for external circuit design-in.
Provide test point for diagnostic purposes.
System
PWR_ON
15
I
Power-on input
Internal active pull-up.
See sections 1.6.1, 1.6.2 for functional description.
See section 2.3.1 for external circuit design-in.
Provide test point for diagnostic purposes.
RESET_N
18
I
External reset input
Internal active pull-up.
See section 1.6.3 for functional description.
See section 2.3.2 for external circuit design-in.
Provide test point for diagnostic purposes.
Antenna
ANT
56
I/O
Cellular antenna
50 nominal characteristic impedance.
Antenna circuit affects the RF performance and application
device compliance with required certification schemes.
See section 1.7.1 for functional description / requirements.
See section 2.4.2 for external circuit design-in.
ANT_GNSS
31
I
GNSS antenna 3
50 nominal characteristic impedance.
See section 1.7.2 for functional description / requirements.
See section 2.4.3 for external circuit design-in.
ANT_DET
62
I
Antenna detection
ADC for antenna presence detection function.
See section 1.7.3 for functional description.
See section 2.4.5 for external circuit design-in.
SIM
VSIM
41
O
SIM supply output
VSIM = 1.8 V / 3 V output as per the connected SIM type.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_IO
39
I/O
SIM data
Data input/output for 1.8 V / 3 V SIM.
Internal pull-up to VSIM.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_CLK
38
O
SIM clock
Clock output for 1.8 V / 3 V SIM.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_RST
40
O
SIM reset
Reset output for 1.8 V / 3 V SIM.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
3
Not supported by SARA-R500S and SARA-R510S modules

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Function
Pin name
Pin no.
I/O
Description
Remarks
UART
RXD
13
O
UART data output
USIO variants 0 / 1 / 2 / 3 / 4:
Primary UART circuit 104 (RxD) in ITU-T V.24, for AT, data,
Mux, FOAT, FW update via u-blox EasyFlash tool.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
Provide test point for FW update purposes.
TXD
12
I
UART data input
USIO variants 0 / 1 / 2 / 3 / 4:
Primary UART circuit 103 (TxD) in ITU-T V.24, for AT, data,
Mux, FOAT, FW update via u-blox EasyFlash tool.
Internal active pull-up enabled.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
Provide test point for FW update purposes.
CTS
11
O
UART clear to send
output
USIO variants 0 / 1 / 2 / 3 / 4:
Primary UART circuit 106 (CTS) in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
RTS
10
I
UART request to
send input
USIO variants 0 / 1 / 2 / 3 / 4:
Primary UART circuit 105 (RTS) in ITU-T V.24.
Internal active pull-up enabled.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
DSR
6
O/I
UART data set
ready output /
AUX UART request
to send input
USIO variant 0:
Pin disabled
USIO variant 1:
Primary UART circuit 107 (DSR) in ITU-T V.24.
USIO variants 2 / 3 / 4:
Auxiliary UART circuit 105 (RTS) in ITU-T V.24.
Internal active pull-up enabled.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
RI
7
O
UART ring indicator
output /
AUX UART clear to
send output
USIO variants 0 / 1:
Primary UART circuit 125 (RI) in ITU-T V.24.
USIO variants 2 / 3 / 4:
Auxiliary UART circuit 106 (CTS) in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
DTR
9
I
UART data terminal
ready input /
AUX UART data
input
USIO variants 0 / 1:
Primary UART circuit 108/2 (DTR) in ITU-T V.24.
Internal active pull-up enabled.
USIO variants 2 / 3 / 4:
Auxiliary UART circuit 103 (TxD) in ITU-T V.24, for AT, data,
GNSS tunneling, FOAT, diagnostics.
Internal active pull-up enabled.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
Provide test point for diagnostic purposes.
DCD
8
O
UART data carrier
detect output /
AUX UART data
output
USIO variant 0:
Pin disabled.
USIO variant 1:
Primary UART circuit 109 (DCD) in ITU-T V.24.
USIO variants 2 / 3 / 4:
Auxiliary UART circuit 104 (RxD) in ITU-T V.24, for AT, data,
GNSS tunneling, FOAT, diagnostics.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
Provide test point for diagnostic purposes.

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Function
Pin name
Pin no.
I/O
Description
Remarks
USB
VUSB_DET
17
I
USB detect input
VBUS USB supply generated by the host must be connected to
this input pin to enable the USB interface.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
Provide test point for diagnostic purposes.
USB_D-
28
I/O
USB Data Line D-
USB interface for diagnostics.
90 nominal differential impedance.
Pull-up, pull-down and series resistors, as required by the USB
2.0 specification [4], are part of the USB pin driver and shall not
be provided externally.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
Provide test point for diagnostic purposes.
USB_D+
29
I/O
USB Data Line D+
USB interface for diagnostics.
90 nominal differential impedance.
Pull-up, pull-down and series resistors, as required by the USB
2.0 specification [4], are part of the USB pin driver and shall not
be provided externally.
See section 1.9.2 for functional description.
See section 2.6.2 for external circuit design-in.
Provide test point for diagnostic purposes.
SPI
SDIO_D0
47
I/O
SPI MOSI
SPI Master Output Slave Input, alternatively settable as SDIO.
SPI supported by “00”product version for diagnostics only.
SDIO_D1
49
I/O
SPI MISO
SPI Master Input Slave Output, alternatively settable as SDIO.
SPI supported by “00” product version for diagnostics only.
SDIO_D2
44
I/O
SPI clock
SPI clock, alternatively configurable as SDIO.
SPI supported by “00” product version for diagnostics only.
SDIO_D3
48
I/O
SPI Chip Select
SPI Chip Select, alternatively configurable as SDIO.
SPI supported by “00” product version for diagnostics only.
SDIO
SDIO_D0
47
I/O
SDIO serial data [0]
SDIO serial data [0], alternatively configurable as SPI MOSI.
SDIO not supported by “00”product version.
SDIO_D1
49
I/O
SDIO serial data [1]
SDIO serial data [1], alternatively configurable as SPI MISO.
SDIO not supported by “00”product version.
SDIO_D2
44
I/O
SDIO serial data [2]
SDIO serial data [2], alternatively configurable as SPI clock.
SDIO not supported by “00”product version.
SDIO_D3
48
I/O
SDIO serial data [3]
SDIO serial data [3], alternatively settable as SPI Chip Select.
SDIO not supported by “00”product version.
SDIO_CLK
45
O
SDIO serial clock
SDIO serial clock.
SDIO not supported by “00”product version.
SDIO_CMD
46
I/O
SDIO command
SDIO command, alternatively configurable by AT+UGPIOC.
SDIO not supported by “00”product version.
DDC
SCL
27
O
I2C bus clock line
Fixed open drain, for communication with I2C-slave devices.
Internal active pull-up: external pull-up is not required.
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.
SDA
26
I/O
I2C bus data line
Fixed open drain, for communication with I2C-slave devices.
Internal active pull-up: external pull-up is not required.
See section 1.9.5 for functional description.
See section 2.6.5 for external circuit design-in.

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Function
Pin name
Pin no.
I/O
Description
Remarks
Audio
I2S_TXD
35
O
I2S transmit data
I2S transmit data.
Alternatively configurable by +UTEST AT command.
I2S not supported by “00” product version.
I2S_RXD
37
I
I2S receive data
I2S receive data.
I2S not supported by “00”product version.
I2S_CLK
36
I/O
I2S clock
I2S clock.
I2S not supported by “00”product version.
I2S_WA
34
I/O
I2S word alignment
I2S word alignment.
Alternatively configurable by +UTEST AT command.
I2S not supported by “00” product version.
GPIO
GPIO1
16
I/O
GPIO
Pin with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
GPIO2
23
I/O
GPIO
Pin with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
GPIO3
24
I/O
GPIO
Pin with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
GPIO4
25
I/O
GPIO
Pin with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
GPIO5
42
I/O
GPIO
Pin with alternatively configurable functions.
See sections 1.8.2 and 1.11 for functional description.
See sections 2.5 and 2.8 for external circuit design-in.
GPIO6
19
I/O
GPIO
Pin with alternatively configurable functions.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
I2S_TXD
35
O
Pin for antenna
dynamic tuning
Configurable as output for antenna dynamic tuning.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
I2S_WA
34
O
Pin for antenna
dynamic tuning
Configurable as output for antenna dynamic tuning.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
EXT_INT
33
I
External interrupt
Configurable as interrupt input triggering the generation of an
URC time stamp.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
SDIO_CMD
46
I
External GNSS time
pulse input
Configurable as input for external GNSS time pulse.
Not supported by SARA-R510M8S modules.
See section 1.11 for functional description.
See section 2.8 for external circuit design-in.
Reserved
RSVD
2
N/A
Reserved pin
Leave unconnected.
See sections 1.12 and 2.9.
Table 3: SARA-R5 series modules pin definition, grouped by function

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1.4 Operating modes
SARA-R5 series modules have several operating modes as defined in Table 4.
General Status
Operating Mode
Definition
Power-down
Not-powered mode
VCC supply not present or below operating range: module is switched off.
Power-off mode
VCC supply within operating range and module is switched off.
Normal operation
Deep-sleep mode
RTC runs with 32 kHz reference internally generated.
Idle mode
Module processor runs with 32 kHz reference internally generated.
Active mode
Module processor runs with 26 MHz reference internally generated.
Connected mode
RF Tx/Rx data connection enabled and processor core runs with 26 MHz reference.
Table 4: SARA-R5 series modules operating modes definition
Figure 5 describes the transition between the different operating modes.
If low power mode and PSM are enabled,
if AT inactivity timer & active timer are expired,
if no other concurrent activity is executed
•Upon expiration of the Periodic Update Timer
•Using PWR_ON pin
Incoming/outgoing data or
other dedicated network communication
No RF Tx/Rx in progress,
communication dropped
Remove VCC
Switch on:
•PWR_ON
•RTC alarm
Not powered
Power off
ActiveConnected Deep sleep
Switch off:
•AT+CPWROFF
Apply VCC
(SARA-R510S)
If low power mode is enabled,
if AT inactivity timer is expired,
if no other concurrent activity is executed
Idle
•Network paging
•Data received over UART
•RTC alarm
Apply VCC
(SARA-R500S and
SARA-R510M8S)
Figure 5: SARA-R5 series modules operating modes transitions
The initial operating mode of SARA-R5 series modules is the one with VCC supply not present or below
the operating range: the modules are switched off in not-powered mode.
Once a valid VCC supply is applied to the SARA-R500S and the SARA-R510M8S modules, this event
triggers the switch-on routine of the modules that subsequently enter the active mode.
Instead, once a valid VCC supply is applied to the SARA-R510S modules, they remain switched off in
power-off mode. Then the proper toggling of the PWR_ON input line is necessary to trigger the
switch-on routine of the modules that subsequently enter the active mode.
SARA-R5 series modules are fully ready to operate when in active mode: the available communication
interfaces are completely functional and the module can accept and respond to any AT command,
entering connected mode upon LTE signal reception / transmission.

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The internal GNSS functionality can be concurrently enabled on the SARA-R510M8S modules by the
dedicated +UGPS AT command, as well as the possible external GNSS functionality can be
concurrently enabled using SARA-R500S or SARA-R510S modules by the dedicated +UGPS AT
command.
Then, the SARA-R5 series modules switch from active mode to the low power idle mode whenever
possible, if the low power configuration is enabled by the dedicated +UPSV AT command. The low
power idle mode can last for different time periods according to the specific +UPSV AT command
setting, according to the specific +CEDRXS / +CEDRXRDP AT commands setting, and according to
the concurrent activities executed by the module, as for example according to the concurrent GNSS
activities.
Then, after having enabled the low power configuration by the dedicated +UPSV AT command,
according to the +CPSMS / +UCPSMS AT commands setting, and according to the concurrent
activities executed by the module (for example according to the concurrent GNSS activities),
whenever possible the SARA-R500S and SARA-R510M8S modules can enter the PSM deep-sleep
mode and the SARA-R510S modules can enter the ultra-low power PSM deep-sleep mode.
Once the modules enter the PSM deep-sleep mode (SARA-R500S and SARA-R510M8S modules) or
the ultra-low power PSM deep-sleep mode (SARA-R510S modules), the available communication
interfaces are not functional: a wake up event, consisting in proper toggling of the PWR_ON input line
or the expiration of the “Periodic Update Timer” set by the LTE network, is necessary to trigger the
wake up routine of the modules that subsequently enter back into the active mode.
SARA-R5 series modules can be gracefully switched off by the dedicated +CPWROFF AT command.
☞See the SARA-R5 series AT commands manual [2], +UPSV, +CEDRXS, +CEDRXRDP, +CPSMS,
+UCPSMS, +UGPS, +CALA, +CPWROFF AT commands, for the possible configurations and
settings of different operating modes.
1.5 Supply interfaces
1.5.1 Module supply input (VCC)
The modules must be supplied via the three VCC pins that represent the module power supply input.
Voltage must be stable, because during operation, the current drawn by the SARA-R5 series modules
through the VCC pins may vary significantly, depending on the operating mode and state (as
described in sections 1.5.1.2, 1.5.1.3, 1.5.1.4 and 1.5.1.5).
It is important that the supply source is able to withstand the average current consumption occurring
during Tx / Rx call at maximum RF power level (see the SARA-R5 series data sheet [1]).
The 3 VCC pins of SARA-R5 series modules are internally connected each other to both the internal
Power Amplifier and the internal baseband Power Management Unit.
Figure 6 provides a simplified block diagram of SARA-R5 series modules’ internal VCC supply routing.
53
VCC
52
VCC
51
VCC
SARA-R5 series
Power
Management
Unit
Memory
Baseband
Processor
Transceiver
Power
Amplifier
Figure 6: Block diagram of SARA-R5 series modules’ internal VCC supply routing

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1.5.1.1 VCC supply requirements
Table 5 summarizes the requirements for the VCC modules supply. See section 2.2.1 for suggestions
to correctly design a VCC supply circuit compliant with the requirements listed in Table 5.
⚠The supply circuit affects the RF compliance of the device integrating SARA-R5 series modules
with applicable required certification schemes as well as antenna circuit design. Compliance is
guaranteed if the requirements summarized in the Table 5 are fulfilled.
Item
Requirement
Remark
VCC nominal voltage
Within VCC normal operating range:
3.3 V / 4.4 V
RF performance is guaranteed when VCC voltage is inside
the normal operating range limits.
RF performance may be affected when VCC voltage is
outside the normal operating range limits, though the
module is still fully functional until the VCC voltage is
inside the extended operating range limits.
VCC voltage during
normal operation
Within VCC extended operating range:
3.0 V / 4.5 V
VCC voltage must be above the extended operating range
minimum limit to switch-on the module.
The module may switch-off when the VCC voltage drops
below the extended operating range minimum limit.
Operation above VCC extended operating range is not
recommended and may affect device reliability.
VCC current
Support with adequate margin the
highest averaged VCC current
consumption value during Tx
conditions specified in the SARA-R5
series data sheet [1]
The maximum average current consumption can be
greater than the specified value according to the actual
antenna mismatching, temperature and supply voltage.
Section 1.5.1.2 describes current consumption profiles in
connected mode.
VCC voltage ripple
Noise in the supply pins must be
minimized
High supply voltage ripple values during RF transmissions
in connected mode directly affect the RF compliance with
the applicable certification schemes.
Table 5: Summary of VCC modules supply requirements
1.5.1.2 VCC current consumption in LTE connected mode
During an LTE connection, the SARA-R5 series modules transmit and receive in half duplex mode. The
current consumption depends on output RF power, which is always regulated by the network (the
current base station) sending power control commands to the module. These power control
commands are logically divided into a slot of 0.5 ms (time length of one Resource Block), thus the rate
of power change can reach a maximum rate of 2 kHz.
Figure 7 shows an example of SARA-R5 series modules’ current consumption profile versus time in
connected mode: transmission is enabled for one sub-frame (1 ms) according to LTE Category M1
half-duplex connected mode. For detailed consumption values, see the SARA-R5 series data sheet [1].
Current [mA]
Time
[ms]
0
300
200
1 00
400
Current consumptionvalue
depends on TX power and
actual antenna load
1 Slot
1 Resource Block
(0.5 ms) 1 LTE Radio Frame
(1 0 ms)
1 Slot
1 Resource Block
(0.5 ms) 1 LTE Radio Frame
(1 0 ms)
Figure 7: VCC current consumption profile versus time during LTE Cat M1 half-duplex connection

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1.5.1.3 VCC consumption in deep-sleep mode (low power mode and PSM enabled)
The low power mode and the PSM configurations are by default disabled, but they can be enabled
using the +UPSV and +CPSMS AT commands (see the SARA-R5 series AT commands manual [2]).
When low power mode and PSM are enabled, whenever possible the modules automatically enter the
PSM deep-sleep mode (SARA-R500S and SARA-R510M8S modules) or the ultra-low power PSM
deep-sleep mode (SARA-R510S), reducing current consumption down to the lowest steady value: only
the RTC runs with internal 32 kHz reference clock frequency. Detailed current consumption values
can be found in the SARA-R5 series data sheet [1].
1.5.1.4 VCC consumption in low power idle mode (low power mode enabled)
The low power mode configuration is by default disabled, but it can be enabled using the +UPSV AT
command (see the SARA-R5 series AT commands manual [2]).
When low power mode is enabled, the module automatically enters the low power idle mode whenever
possible, but it must periodically monitor the paging channel of the current base station (paging block
reception), in accordance to the LTE system requirements, even if connected mode is not enabled by
the application. When the module monitors the paging channel, it wakes up to the active mode to
enable the reception of the paging block. In between, the module switches to low power mode. This is
known as discontinuous reception (DRX) or extended discontinuous reception (eDRX).
Figure 8 illustrates an example of the module current consumption profile when low power mode
configuration is enabled: the module is registered with the network, automatically enters the low
power idle mode, and periodically wakes up to active mode to monitor the paging channel for the
paging block reception in discontinuous reception (DRX) mode.
Detailed current consumption values can be found in the SARA-R5 series data sheet [1].
IDLE MODE ACTIVE MODE IDLE MODE
Active Mode
Enabled
Idle Mode
Enabled
Time [s]
Current [mA]
Time [ms]
Current [mA]
RX
Enabled
0
1 00
0
1 00
Paging period
Figure 8: VCC current consumption profile with low power mode enabled and module registered with the network: themodule
is in low-power idle mode and periodically wakes up to active mode to monitor the paging channel for paging block reception

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1.5.1.5 VCC consumption in active mode (low power mode and PSM disabled)
The active mode is the state where the module is switched on and ready to communicate with an
external device by means of the application interfaces (as the UART serial interface). The module
processor core is active and the 26 MHz reference clock frequency is used.
If low power mode configuration is disabled, as it is by default (see the SARA-R5 series AT commands
manual [2], +UPSV AT commands for details), the module remains in active mode. Otherwise, if low
power mode configuration is enabled, the module enters low power idle mode (and deep-sleep mode
power saving mode, if enabled) whenever possible.
Figure 9 shows a typical example of the module current consumption profile when the module is in
active mode. Here, the module is registered with the network and, while active mode is maintained,
the receiver is periodically activated to monitor the paging channel for paging block reception.
Detailed current consumption values can be found in the SARA-R5 series data sheet [1].
ACTIVE MODE
Paging period
Time [s]
Current [mA]
Time [ms]
Current [mA]
RX
enabled
0
1 00
0
1 00
Figure 9: VCC current consumption profile with low power mode disabled and module registered with the network: active
mode is always held and the receiver is periodically activated to monitor the paging channel for paging block reception
1.5.2 Generic digital interfaces supply output (V_INT)
The same voltage domain internally used as supply for the generic digital interfaces of SARA-R5
series modules is also available on the V_INT output pin, as illustrated in Figure 10.
The internal regulator that generates the V_INT supply output is a switching (DC-DC) converter, which
is directly supplied from the VCC main supply input of the module.
The V_INT voltage regulator output of SARA-R5 series modules is disabled (i.e. 0 V) when the module
is switched off, and it can be used to monitor the operating mode of the module as follows:
•When the module is off, or in deep-sleep mode, the voltage level is low (i.e. 0 V)
•When the module is on, outside deep-sleep mode, the voltage level is high (i.e. 1.8 V)
The current capability is specified in the SARA-R5 series data sheet [1]. The V_INT voltage domain can
be used in place of an external discrete regulator as a reference voltage rail for external components.

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Baseband
processor
51
VCC
52
VCC
53
VCC
4
V_INT
DCDC Digital I/O
interfaces
Power
management
SARA-R5 series
Figure 10: SARA-R5 series interfaces supply output (V_INT) simplified block diagram
1.6 System function interfaces
1.6.1 Module power-on
1.6.1.1 Switch-on events
When the SARA-R500S and SARA-R510M8S modules are in the not-powered mode (i.e. switched off,
with the VCC module supply not applied), the switch-on routine can be triggered by:
•Applying a voltage at the VCC module supply input within the operating range (see SARA-R5 series
data sheet [1]).
When the SARA-R510S modules are in the not-powered mode (i.e. switched off, with the VCC module
supply not applied), the switch-on routine can be triggered by:
•Applying a voltage at the VCC module supply input within the operating range, and then forcing a
low level at the PWR_ON input pin (normally high due to internal pull-up) for a valid time period (see
SARA-R5 series data sheet [1]).
When the SARA-R5 series modules are in the power-off mode (i.e. switched off, but with a valid voltage
present at the VCC module supply input) or in deep-sleep mode, they can be switched on or they can
be woken up as following:
•Forcing a low level at the PWR_ON input pin (normally high due to internal pull-up) for a valid time
period (see SARA-R5 series data sheet [1]).
As illustrated in Figure 11, the PWR_ON input pin is equipped with an internal pull-up resistor. Detailed
electrical characteristics with voltages and timings are described in the SARA-R5 series data
sheet [1].
Baseband processor
15
PWR_ON
SARA-R5 series
Power-on
Power management
Power-on
Figure 11: SARA-R5 series PWR_ON input equivalent circuit description