Ublox NORA-W10 Series User manual

UBX-22002764 - R02
C1-Public www.u-blox.com
EVK-NORA-W10
Evaluation kit for NORA-W10 series modules
User guide
Abstract
The document describes how to set up and use the EVK-NORA-W101 and EVK-NORA-W106
evaluation kits for prototyping NORA-W10 open CPU, multiradio modules. To obtain the different
options for debugging and the development capabilities included in the evaluation board see NORA-
W10 system integration manual [2].

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Document information
Title
EVK-NORA-W1
Subtitle
Evaluation kit for NORA-W10 series modules
Document type
User guide
Document number
UBX-22002764
Revision and date
R02
22-Jul-2022
Disclosure restriction
C1-Public
Product status
Corresponding content status
In development /
Prototype
Objective specification
Target values. Revised and supplementary data will be published later.
Engineering sample
Advance information
Data based on early testing. Revised and supplementary data will be published later.
Initial production
Early production information
Data from product verification. Revised and supplementary data may be published later.
Mass production/
End of life
Production information
Document contains the final product specification.
This document applies to the following products:
Product name
Document status
EVK-NORA-W101
Objective specification
EVK-NORA-W106
Objective specification
☞For information about the hardware, software, and status of the available product types, see the
NORA-W10 data sheet [1].
u-blox or third parties may hold intellectual property rights in the products, names, logos and designs included in this
document. Copying, reproduction, modification or disclosure to third parties of this document or any part thereof is only
permitted with the express written permission of u-blox.
The information contained herein is provided “as is” and u-blox assumes no liability for its use. No warranty, either express or
implied, is given, including but not limited to, with respect to the accuracy, correctness, reliability and fitness for a particular
purpose of the information. This document may be revised by u-blox at any time without notice. For the most recent
documents, visit www.u-blox.com.
Copyright © u-blox AG.

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Contents
Document information................................................................................................................................2
Contents ..........................................................................................................................................................3
1Product description ..............................................................................................................................4
1.1 Key features .................................................................................................................................................4
1.2 Kit includes ................................................................................................................................................... 5
1.2.1 EVK-NORA-W101...............................................................................................................................5
1.2.2 EVK-NORA-W106...............................................................................................................................5
2Setting up the evaluation board.......................................................................................................6
3Hardware description...........................................................................................................................7
3.1 Overview........................................................................................................................................................7
3.2 Power .............................................................................................................................................................7
3.2.1 Powering the board ............................................................................................................................8
3.3 Reset..............................................................................................................................................................9
3.4 Buttons........................................................................................................................................................10
3.5 LEDs.............................................................................................................................................................11
3.6 Serial communication ..............................................................................................................................12
3.7 32.768 kHz low frequency clock.............................................................................................................13
3.8 Current sensing headers .........................................................................................................................14
3.9 External JTAG debug interface..............................................................................................................15
3.10 QSPI memory .............................................................................................................................................16
3.11 Jumpers......................................................................................................................................................17
3.12 Header pin-out ...........................................................................................................................................18
Appendix ....................................................................................................................................................... 21
AGlossary ................................................................................................................................................. 21
Related documentation ........................................................................................................................... 22
Revision history.......................................................................................................................................... 22
Contact.......................................................................................................................................................... 22

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1Product description
The EVK-NORA-W10 evaluation kit provides stand-alone use of the NORA-W10 series module.
All pins and interfaces supported on NORA-W10 series modules are conveniently accessed from the
evaluation board. A simple USB connection provides the physical interface for the power,
programming, and COM ports. A USB peripheral connector, reset button, and four other user buttons
are available.
GPIO signals are available on headers that are compatible with the Arduino® form factor. This allows
easy use of existing Arduino shields. Current sense resistors allow for measuring current into the
module and into the shield.
This guide provides setup instructions for starting development and describes the hardware
functionality of the EVK-NORA-W10 board.
1.1 Key features
EVK-NORA-W2 provides developers with access several practical features for testing and evaluating
the connectivity options supported in NORA-W2 series modules, including:
•Used for evaluation of NORA-W101 or NORA-W106 modules
•COM ports and debug ports over USB
•Full GPIO of the NORA-W1 series
•Buttons and status LEDs for user interaction
•32.768 kHz crystal
•USB peripheral connector
•Power input through USB-C or pin sockets
•Current measurement access points from pin headers and jumpers
Figure 1: EVK-NORA-W10 evaluation board (top view)

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1.2 Kit includes
1.2.1 EVK-NORA-W101
•EVK-NORA-W10 evaluation board with NORA-W101 module
•USB-C to USB-A adapter cable
•2.4 GHz U.FL antenna
1.2.2 EVK-NORA-W106
•EVK-NORA-W10 evaluation board with NORA-W106 module –equipped with 2.4 GHz integrated
antenna (external antenna not supplied)
•USB-C to USB-A adapter cable

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2Setting up the evaluation board
The EVK-NORA-W10 is delivered without any software (open CPU) and the software must be
developed by the user.
The following devices are applicable:
•EVK-NORA-W101
•EVK-NORA-W106
Connect the external power supply to the EVK as described in Powering the board. The green status
LED (D10) is lit when the internal EVK 3.3 V supply is active.
⚠Before powering up the EVK-NORA-W106, be sure to connect the 2.4 GHz antenna to the U.FL
antenna connector (J12). Failing to do can cause module malfunction.
⚠Observe that the inrush current when powering-up the EVK. The current level can be significantly
higher than it is during normal operation.
The operating system installs the correct COM port drivers automatically. The drivers need to be
installed only when you connect the unit to a new computer for the first time. For more information
about the COM ports and their configuration, see the FTDI FT231XQ-R Datasheet [3].
Windows OS automatically assigns one COM port to the unit.
To view the assigned COM ports on Windows 10:
1. Open the Control Panel and click Hardware and Sound.
2. Click Device Manager in Devices and Printers. This opens the Device Manager window where you
can view the assigned COM ports.
NORA-W10 open CPU module variants are used for developing custom software based on the
Espressif IoT Development Framework (ESP-IDF) that provides a self-sufficient SDK and API for
application development. Before compiling custom software, the ESP-IDF must be configured for use
with the NORA-W10 open CPU variant. For information about setting up the ESP-IDF work
environment, see the NORA-W10 system integration manual [2].

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3Hardware description
☞Design files for the EVK-NORA-W10 PCB are available from your local u-blox support team.
3.1 Overview
Figure 2 shows the physical location of the power switch, supported IO signals, LEDs, buttons, and
connectors on the EVK-NORA-W10 board.
Figure 2: EVK-NORA-W10 PCB overview
3.2 Power
The EVK-NORA-W1 has three possible power sources:
•USB supply from the debug interface
•USB peripheral supply from the NORA-W1module
•+5 V [ 3.6–5.5 V supply from the 2.54 mm pitch pin header (J1 pin-8)
Each of the three power sources are separated using a Schottky diode (D1 –D3, MBR120VLSFT3G).
The diode prevents reverse voltage to any of the other supplies, which means that the power sources
can be connected simultaneously. See Figure 3 and Figure 4.
GPIO8
GPIO9
NC.
IOREF
RESET
+3V3
VBUS
GND
GND
+Vin
GPIO11
GPIO12
GPIO13
GPIO5
GPIO15
GPIO16
GPIO0
GPIO21
NC.
GND
GPIO36
GPIO37
GPIO35
GPIO34
GPIO38
GPIO33
GPIO10
GPIO14
GPIO2
GPIO3
GPIO4
GPIO46
TxD
RxD
GPIO45
GPIO6
GPIO1
GPIO7
GPI047
GPIO48
GPIO18
GPIO17
LED4:TxD
LED6:RTS
LED5:RxD
LED7:CTS
LED8:DTR
LED9:DSR
BTN1:GPIO46
BTN2:GPIO0
BTN3:GPIO47
BTN4:GPIO48
RGB LED
RF-port
POWER LED D10
POWER SW6
RESET BTN
J1
J2
J3
J4
J7
J5
Buttons and switches
Not connected
IO-signals
Color code
LEDs
Supply voltage
Ground connection
Pin-1 indicator
GPIO42
GPIO41
GPIO40
GPIO39
Header
J8
J20
J79

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⚠Only if the power protection circuits are left intact can the USB be safely connected at the same
time as external power. This makes programming of the module easier.
⚠The EVK USB type C connectors are only capable of handling 5 V input, 12 V is not allowed.
3.2.1 Powering the board
Set the power switch (SW6) “ON” to extend the VBUS supply to the 3.3 V LDO regulator and power up
the board. The LDO regulator powers the +3V3, VDD and VDD-IO power rails. The green LED (D1) is
lit when power is applied. See also LEDs.
Figure 3: EVK schematic - power supply
Figure 4: EVK schematic - IOREF separation
+3V3 (J1 pin 4) can supply external parts with up to 50 mA (max).
IOREF (J1 pin 2) is the external supply input to the IO voltage level shifters (optional). A protection
diode (Maxim MAX40203AUK) with a voltage drop of 28 mV at 100 mA separates IOREF from +3V3.

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3.3 Reset
EVK-NORA-W10 provides a hardware reset to the NORA-W10 module. The Reset button (SW5) is
connected to the module RESETn signal.
To enter bootloader mode, hold down the Boot button (SW2) during the USB power on. To enter the
programming mode, assert a reset in bootloader mode. See also Figure 5.
Figure 5: EVK schematic - reset and boot buttons
UART-DTR and UART-RTS can be used to initiate BOOT and nRESET as an alternative to using the
buttons SW2 and SW5. Figure 6 shows the location and schematic for these circuits.
Figure 6: Alternative BOOTn and RESET using UART-DTR and RTS
Signal name
Description
GPIO0/BOOTn
GPIO0 input to module interface during normal operation.
Drive low during power-up to enter bootloader mode on NORA-W1 module.
RESETn
NORA-W1 reset signal.
Table 1: EVK reset signals

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3.4 Buttons
In addition to the RESET button, the evaluation board also supports four user buttons that are active-
low and connect to ground when pressed. The functionality of these buttons is controlled by the
system software through the GPIO interface. The buttons and the associated GPIO signals are shown
in Figure 7.
☞The BOOTn button is multifunctional. Press the button when powering on the board to enter the
boot mode. When the power cycle is complete, the button can then be used for other user
functions in the software.
Figure 7: EVK schematic - user buttons

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Table 2 describes the various user buttons and their relationship with the corresponding GPIO signals
and protection diodes shown in Figure 7. For proper operation, the internal pull-up resistor of each
NORA-W10 GPIO pin must be enabled.
Button
Switch
GPIO
Protection diode
Function
1
SW1
GPIO46
D21
No predefined function (software controlled)
2
SW2
GPIO0
D22
BOOTn
3
SW3
GPIO47
D23
No predefined function (software controlled)
4
SW4
GPIO48
D24
No predefined function (software controlled)
5
SW5
-
-
RESETn
Table 2: User button components
3.5 LEDs
EVK-NORA-W1 supports eight LEDs:
•Power status (D10): Indicates power on the board when lit (green)
•UART0 status (D4–D9): Indicates UART0 signal status under GPIO control, as shown in Figure 9.
•System status (RGB1): Powered by +3V3 and turned on by pulling the associated GPIO low.
Disconnect each LED from the GPIO by removing resistors R78–R79, as shown in Table 3.
Table 3 describes the association between each RGB LED and respective GPIO. Having disconnected
an RGB LED (R78-R79), the related signal can be optionally used for analog-to-digital conversion.
RGB LED
Associated GPIO
Comments
Red (pin1)
GPIO5/ADC1-CH4
Remove R77 to disconnect R-LED
Green (pin2)
GPIO2/ADC1-CH1
Remove R78 to disconnect G-LED
Blue (pin3)
GPIO8/ADC1-CH7
Remove R79 to disconnect B-LED
Table 3: RGB LED associated signals
Figure 8 shows the schematic for the System status (RGB1) LED. Figure 9 shows the schematic for
the six UART0 status LEDs.
Figure 8: Schematic –RGB and power LED
Figure 9: Schematic –UART0 status LEDs

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Table 4 describes each of the UART0 LEDs and their relationship with corresponding pin sockets,
GPIO, and serial UART0 signals.
LED
Color
GPIO
Pin socket
Comments
D4
Green
GPIO43/UART0-TxD
J3-7
D5
Orange
GPIO44/UART0-RxD
J3-8
D6
Green
GPIO45/UART0-RTS
J5-1
D7
Orange
GPIO6/UART0-CTS
J5-2
D8
Green
GPIO1/UART0-DTR
J5-3
D9
Orange
GPIO7/UART0-DSR
J5-4
D10
Green
-
Power ON LED
Table 4: UART0 LEDs and associated signals
3.6 Serial communication
The evaluation board allows for easy serial communication with the NORA-W10 module and a
connected computer through a single FTDI, USB-to-UART IC that provides one COM port.
The COM port is connected to module UART0 through 1 kΩ resistors, which means that multiple
UART0 signals can be connected to pin sockets J3 and J5 at the same time.
Table 5 shows the function and COM port connections for each module pin.
NORA-W1 pin name
NORA-W1 function
Resistor/Jumper enable
Interface IC function
G9
GPIO44/UART0-RxD
R20
FTDI-TxD
G8
GPIO43/UART0-TxD
R22
FTDI-RxD
F9
GPIO6/UART0-CTS
R23
FTDI-RTS
F8
GPIO45/UART0-RTS
R29
FTDI-CTS
E9
GPIO7/UART0-DSR
R30
FTDI-DTR
E8
GPIO1/UART0-DTR
R32
FTDI-DSR
Table 5: COM port connections

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Figure 10: UART0 level shifters and pin socket
Figure 11: FTDI drawing, 1 port default
3.7 32.768 kHz low frequency clock
The evaluation board has a 32.768 kHz crystal connected to the NORA-W10 module to allow use of
the external crystal oscillator option to source the RTC clock. The other options to source the RTC
clock are from the internal slow RC oscillator and the internal fast RC oscillator divided clock.

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If the signals GPIO15/ADC2-CH4 and GPIO16/ADC2-CH5 are used, the crystal can be removed from
the circuit by opening jumpers J19 and J21 and soldering across the normally open positions, as
shown in Figure 12. This connects XT-32k-p and XT-32k-n to the EVK pin socket J2, pin 5 and pin 6.
See also GPIO jumpers.
Figure 12: Schematic –32 kHz crystal
3.8 Current sensing headers
The evaluation board provides two current sensing headers:
•J7 for power consumption measurement of the module VDD supply.
•J8 for power consumption measurement of the module VDD-IO supply.
Each of the 2.54 mm pitch 3-pin headers has two pins connected across a 1 Ωcurrent-sense resistors
RMOD and RIO respectively, with the third connected to GND. The module VDD and VDD-IO supplies
are sourced through these resistors. To measure current consumption, use a multimeter or other
precise voltage measurement device to measure the voltage drop across pins 2 and 3. Current can
also be measured directly by opening JRMOD or JRIO to remove the current-sense resistor from the
circuit. Use an ammeter in-series with the two voltage pins.
⚠Pin 1 of J7 and J8 is connected to GND.
To bypass the current sense resistors, RMOD and RIO, solder the respective jumpers JMOD and JRIO.
The default hardware configuration does not require any modification of the current sense headers
for the EVK-NORA-W10 to perform properly.
Figure 13: Current sensing header circuits

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3.9 External JTAG debug interface
External target hardware can be attached to the J20 header connector for firmware programming
and debug. J20 is implemented with a 2x5 header with 1.27 mm pitch. Figure 13 shows the physical
layout of connector.
Figure 14: J20 physical layout
Figure 15 shows a schematic diagram of the JTAG debug interface.
Figure 15: External JTAG debug interface

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3.10 QSPI memory
A Quad SPI PSRAM can be optionally mounted on EVK board at U2. The present configuration of
NORA-W1 already includes an internal flash memory, so U1 should be left unmounted.
PSRAM can be powered from +3V3 or internal VDD-SPI supplies in the module internal. Include either
resistor R70 or R71 to select the preferred choice of power supply to the SPI flash memory chip.
Figure 16: Quad PSRAM EVK - schematic and EVK board view
Table 6 shows the respective SPI functions for corresponding ESP32-S3 GPIOs and NORA-W10 pins.
Interface function
ESP32-S3 GPIO
NORA-W10 pin
Interface IC function
QSPI-CS1
32
E1
PSRAM chip select
QSPI-CLK
33
F1
SPI0 clock
QSPI-IO3 HD
30
F2
SPI0 Hold
QSPI-IO2 WP
31
D1
SPI0 Write Protect
QSPI-IO1 Q
34
E2
SPI0 Controller Input
Peripheral
QSPI-IO0 D
35
D2
SPI0 Controller Output
Table 6: Quad SPI interface signal overview

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3.11 Jumpers
The EVK-NORA-W10 printed circuit board (PCB) supports several solder-bridge jumpers for
configuring GPIO functions. Most jumpers disconnect on-board components from the GPIO nets and
subsequently eliminate interference generated by any external circuits attached to the I/O sockets
(female). The physical location of the jumpers is shown in Figure 17.
Figure 17: PCB jumper positions
The physical location of some GPIO jumpers, test points, and other components are shown on the
bottom side of the PCB, as shown in Figure 18.
Figure 18: Legend for GPIO jumpers and test points (bottom view)
Pin-1 indicator

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Table 6 shows the default configuration of “solder-bridge" jumpers. Choose alternative configurations
by cutting the bridge and soldering the jumpers in the default positions.
Jumper
Jumper type
Default function
Alternate function
J15
Solder-bridge
Connected to J20 debug connector, JTAG-TMS
Cut and close to Test Point GPIO42
J16
Solder-bridge
Connected to J20 debug connector, JTAG-TCK
Cut and close to Test Point GPIO39
J17
Solder-bridge
Connected to J20 debug connector, JTAG-TDO
Cut and close to Test Point GPIO40
J18
Solder-bridge
Connected to J20 debug connector, JTAG-TDI
Cut and close to Test Point GPIO41
J19
Solder-bridge
Connected to 32KHz clock, XT-32k-p
Cut and close to J2 connector GPIO15
J21
Solder-bridge
Connected to 32KHz clock, XT-32k-n
Cut and close to J2 connector GPIO16
Table 7: Solder-bridge jumpers overview
3.12 Header pin-out
Figure 14 shows the 2.54 mm pitch sockets exposing the IO signals on the NORA-W10 module.
Figure 19: EVK-NORA-W10 headers
⚠To enable the EVK-NORA-W10 I/O pins to handle 5 V signals the level shifters (U102 –U104, TI
TXS0108EPWR) must be populated and IOREF must be supplied with +5 V. When using 3.3 V on
the EVK-NORA-W1 I/O pins, the Arduino Uno® style shields must be configured to use the +3.3 V
I/O voltage reference.
GPIO8
GPIO9
NC.
IOREF
RESET
+3V3
VBUS
GND
GND
+Vin
GPIO11
GPIO12
GPIO13
GPIO5
GPIO15
GPIO16
GPIO21
NC
GND
GPIO36
GPIO37
GPIO35
GPIO34
GPIO38
GPIO33
GPIO10
GPIO14
GPIO2
GPIO3
GPIO4
GPIO46
TxD
RxD
GPIO45
GPIO6
GPIO1
GPIO7
GPI047
GPIO48
GPIO18
GPIO17
J1
J3
J4
J5
Headers
IO-signals
Color code
Supply voltage
Ground connection
GPIO42
GPIO41
GPIO40
GPIO39
J20
Pin-1 indicator
J2
J7
J8
GPIO0

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Table 8 - Table 13 show the pin assignments of each header.
Pin
Pin name
NORA-W1 pin
Function
1
NC.
-
No connection
2
IOREF
-
Level shifter supply voltage
3
RESETn
J3
ESP-GPIO/AIN6
4
+3V3
–
Supply
5
VBUS
Supply
6
GND
Ground
7
GND
Ground
8
+Vin
Supply
Table 8: Header J1, power
Pin
Pin name
NORA-W1 pin PT1/PT2
Function
1
GPIO11
G3
GPIO ADC2-CH0
2
GPIO12
G2
GPIO ADC2-CH1
3
GPIO13
A6
GPIO ADC2-CH2
4
GPIO5
J8
GPIO ADC1-CH4
5
GPIO15
C6
GPIO ADC2-CH4, XTAL-32K-P
6
GPIO16
B6
GPIO ADC2-CH5, XTAL-32K-N
Table 9: Header J2, analog IO
Pin
Pin name
NORA-W1 pin
Function
1
GPIO10
H3
FSPI-IO4
2
GPIO14
A5
FSPI-DQS
3
GPIO2
H8
ADC1-CH1
4
GPIO3
J9
ADC-CH2
5
GPIO4
D8
ADC1-CH3
6
GPIO46
H7
GPIO46
7
TxD
G8
GPIO43
8
RxD
G9
GPIO44
Table 10: Header J3, digital IO
Pin
Pin name
NORA-W1 pin
Function
1
GPIO0
F7
BOOTn
2
GPIO21
C8
GPIO21
3
NC.
–
4
GND
–
5
GPIO36
B1
FSPI-CLK
6
GPIO37
C1
FSPI-Q
7
GPIO35
C2
FSPI-D
8
GPIO34
B3
FSPI-CS0
9
GPIO38
A2
FSPI-WP
10
GPIO33
D3
FSPIHD
Table 11: Header J4, digital IO

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Pin
Pin name
NORA-W1 pin
Function
1
GPIO45
F8
RTS
2
GPIO6
F9
CTS
3
GPIO1
E8
DTR
4
GPIO7
E9
DSR
5
GPIO47
F3
SPICLK_P
6
GPIO48
E3
SPICLK_N
7
GPIO18
B4
SDA
8
GPIO17
A3
SCL
Table 12: Header J5, digital IO
Pin
Pin name
NORA-W1 pin
Function
1
+3V3
-
Supply
2
JTAG-TMS
H2
GPIO42 if J15 is changed
3
GND
-
Ground
4
JTAG-TCK
J2
GPIO-39 if J16 is changed
5
GND
-
Ground
6
JTAG-TDO
G1
GPIO40 if J17 is changed
7
NC.
-
No connection
8
JTAG-TDI
H1
GPIO41 if J18 is changed
9
GND
-
Ground
10
RESET
J3
Module reset
Table 13: Header J20, External JTAG debug port