Wolfson WM8940 User manual

w WM8940
Mono CODEC with Speaker Driver
WOLFSON MICROELECTRONICS plc
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Production Data, Rev 4.2, April 2008
Copyright ©2008 Wolfson Microelectronics plc
DESCRIPTION
The WM8940 is a low power, high quality mono CODEC
designed for portable applications such as digital still cameras
or camcorders.
The device integrates support for a differential or single ended
mic, and includes drivers for speakers or headphone, and
mono line output. External component requirements are
reduced as no separate microphone or headphone amplifiers
are required.
Advanced Sigma Delta Converters are used along with digital
decimation and interpolation filters to give high quality audio at
sample rates from 8 to 48ks/s. A selectable high pass filter
and four fully-programmable notch filters are available in the
ADC path. An advanced mixed signal ALC function with noise
gate is provided, while readback of PGA gain during ALC
operation is supported. The digital audio interface supports A-
law and µ-law companding.
An on-chip PLL is provided to generate the required Master
Clock from an external reference clock. The PLL clock can
also be output if required elsewhere in the system.
The WM8940 operates at supply voltages from 2.5 to 3.6V,
although the digital supplies can operate at voltages down to
1.71V to save power. Different sections of the chip can also be
powered down under software control using the selectable two
or three wire control interface.
WM8940 is supplied in a very small 4x4mm QFN package,
offering high levels of functionality in minimum board area,
with high thermal performance.
FEATURES
•Mono CODEC:
•Audio sample rates:8, 11.025, 16, 22.05, 24, 32, 44.1, 48kHz
•DAC SNR 98dB, THD -84dB (‘A’-weighted @ 8 – 48ks/s)
•ADC SNR 94dB, THD -80dB (‘A’-weighted @ 8 – 48ks/s)
•On-chip Headphone/Speaker Driver
- 40mW output power into 16Ω
- BTL speaker drive 0.4W into 8Ω
•Additional MONO Line output
•Multiple analog or ‘Aux’ inputs, plus analog bypass path
•Mic Preamps:
•Differential or single end Microphone Interface
- Programmable preamp gain
- Pseudo differential inputs with common mode rejection
- Programmable ALC / Noise Gate in ADC path
•Low-noise bias supplied for electret microphones
OTHER FEATURES
•Digital Playback Limiter
•Programmable high pass filter (wind noise reduction)
•4 notch filters (narrowband noise suppression)
•On-chip PLL
•Low power, low voltage
- 2.5V to 3.6V (digital: 1.71V to 3.6V)
•4x4x0.9mm 24 lead QFN package
APPLICATIONS
•Digital still cameras and camcorders
•General purpose mono audio CODEC

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BLOCK DIAGRAM

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TABLE OF CONTENTS
DESCRIPTION .......................................................................................................1
FEATURES.............................................................................................................1
APPLICATIONS .....................................................................................................1
BLOCK DIAGRAM.................................................................................................2
TABLE OF CONTENTS .........................................................................................3
PIN CONFIGURATION...........................................................................................5
ORDERING INFORMATION ..................................................................................5
PIN DESCRIPTION ................................................................................................6
ABSOLUTE MAXIMUM RATINGS.........................................................................7
RECOMMENDED OPERATING CONDITIONS .....................................................7
ELECTRICAL CHARACTERISTICS ......................................................................8
TERMINOLOGY .......................................................................................................... 10
AUDIO PATHS OVERVIEW.................................................................................11
SIGNAL TIMING REQUIREMENTS.....................................................................13
SYSTEM CLOCK TIMING ........................................................................................... 13
AUDIO INTERFACE TIMING – MASTER MODE ........................................................ 13
AUDIO INTERFACE TIMING – SLAVE MODE............................................................ 14
CONTROL INTERFACE TIMING – 3-WIRE MODE .................................................... 15
CONTROL INTERFACE TIMING – 2-WIRE MODE .................................................... 16
DEVICE DESCRIPTION.......................................................................................17
INTRODUCTION......................................................................................................... 17
INPUT SIGNAL PATH ................................................................................................. 18
ANALOGUE TO DIGITAL CONVERTER (ADC).......................................................... 23
INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) .......................................... 28
OUTPUT SIGNAL PATH ............................................................................................. 41
ANALOGUE OUTPUTS............................................................................................... 45
OUTPUT SWITCH ...................................................................................................... 48
DIGITAL AUDIO INTERFACES................................................................................... 51
AUDIO SAMPLE RATES............................................................................................. 55
MASTER CLOCK AND PHASE LOCKED LOOP (PLL)............................................... 55
COMPANDING............................................................................................................ 58
GENERAL PURPOSE INPUT/OUTPUT...................................................................... 60
CONTROL INTERFACE.............................................................................................. 61
3-WIRE SERIAL CONTROL MODE ............................................................................ 62
READBACK IN 3-WIRE MODE ................................................................................... 62
2-WIRE SERIAL CONTROL MODE ............................................................................ 63
RESETTING THE CHIP .............................................................................................. 64
POWER SUPPLIES .................................................................................................... 64
POWER MANAGEMENT ............................................................................................ 66
POP MINIMISATION ................................................................................................... 67
REGISTER MAP...................................................................................................68
REGISTER BITS BY ADDRESS ................................................................................. 69
DIGITAL FILTER CHARACTERISTICS...............................................................80
TERMINOLOGY .......................................................................................................... 80
DAC FILTER RESPONSES......................................................................................... 81
ADC FILTER RESPONSES......................................................................................... 81
HIGHPASS FILTER..................................................................................................... 82
NOTCH FILTERS AND LOW PASS FILTER............................................................... 83

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NOTCH FILTER WORKED EXAMPLE........................................................................ 84
APPLICATIONS INFORMATION.........................................................................85
RECOMMENDED EXTERNAL COMPONENTS.......................................................... 85
PACKAGE DIAGRAM ..........................................................................................86
IMPORTANT NOTICE..........................................................................................87
ADDRESS ................................................................................................................... 87

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PIN CONFIGURATION
TOP VIEW
ORDERING INFORMATION
ORDER CODE TEMPERATURE
RANGE PACKAGE MOISTURE SENSITIVITY LEVEL PACKAGE BODY TEMPERATURE
WM8940GEFL/V -25°C to +85°C 24-lead QFN (4x4x0.9mm)
(Pb-free)
MSL3 260oC
WM8940GEFL/RV -25°C to +85°C 24-lead QFN (4x4x0.9mm)
(Pb-free, tape and reel)
MSL3 260oC
Note:
Reel Quantity = 3,500

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PIN DESCRIPTION
PIN NAME TYPE DESCRIPTION
1 MICBIAS Analogue Output Microphone bias
2 AVDD Supply Analogue supply
3 AGND Supply Analogue ground
4 DCVDD Supply Digital Supply (Core)
5 DBVDD Supply Digital supply (Input/Output)
6 DGND Supply Digital ground
7 ADCDAT Digital Output ADC digital audio data output
8 DACDAT Digital Input DAC digital audio data input
9 FRAME Digital Input / Output DAC and ADC sample rate clock or frame synch
10 BCLK Digital Input / Output Digital audio port clock
11 MCLK Digital Input Master clock input
12 CSB/GPIO Digital Input / Output 3-Wire control interface chip select or GPIO pin.
13 SCLK Digital Input 3-Wire control interface clock Input / 2-Wire control interface clock
input
14 SDIN Digital Input / Output 3-Wire control interface data Input / 2-Wire control interface data input
15 MODE / GPIO Digital Input Control interface mode selection pin or GPIO pin.
16 MONOOUT Analogue Output Mono output
17 SPKOUTP Analogue Output Speaker output positive
18 SPKGND Supply Speaker ground
19 SPKOUTN Analogue Output Speaker output negative
20 SPKVDD Supply Speaker supply
21 AUX Analogue Input Auxiliary analogue input
22 VMID Reference Decoupling for midrail reference voltage
23 MICN Analogue Input Microphone negative input (common mode)
24 MICP Analogue Input Microphone positive input
Note:
1. It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB.
2. Refer to the application note WAN_0118 on “Guidelines on How to Use QFN Packages and Create Associated PCB
Footprints”

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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given
under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to
damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this
device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION MIN MAX
DBVDD, DCVDD, AVDD, SPKVDD supply voltages -0.3V +4.2
Voltage range digital inputs DGND -0.3V DVDD +0.3V
Voltage range analogue inputs AGND -0.3V AVDD +0.3V
Operating temperature range, TA-25°C +85°C
Storage temperature prior to soldering 30°C max / 85% RH max
Storage temperature after soldering -65°C +150°C
Notes
1. Analogue and digital grounds must always be within 0.3V of each other.
2. All digital and analogue supplies are completely independent from each other.
RECOMMENDED OPERATING CONDITIONS
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Digital supply range (Core) DCVDD 1.71 3.6 V
Digital supply range (Buffer) DBVDD 1.71 3.6 V
Analogue supplies range AVDD, SPKVDD12.5 3.6 V
Ground DGND,AGND, SPKGND 0 V
Notes
1. Analogue supply voltages must be ≥the digital supply voltages
2. DBVDD must be ≥DCVDD

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ELECTRICAL CHARACTERISTICS
Test Conditions
DCVDD = 1.8V, AVDD = DBVDD = 3.3V, SPKVDD =3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise
stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Microphone Input PGA Inputs (MICN, MICP)
INPPGAVOL and PGABOOST = 0dB
Full-scale Input Signal Level – Single-
ended input via LIN/RIN 1
AVDD/3.3 Vrms
Full-scale Input Signal Level –
Pseudo-differential input 1,2
AVDD*0.7/
3.3
V
rms
Input PGA equivalent input noise INPPGAVOL = +35.25dB
No input signal
0 to 20kHz
76.5 dB
MICN input resistance INPPGAVOL = +35.25dB 2 kΩ
MICN input resistance INPPGAVOL = 0dB 58.5 kΩ
MICN input resistance INPPGAVOL = -12dB 97.5 kΩ
MICP input resistance All gain settings 124.5 kΩ
Input Capacitance All analogue input pins 10 pF
Maximum Input PGA Programmable
Gain
Gain adjusted by
INPPGAVOL
+33.25 +35.25 +37.25 dB
Minimum Input PGA Programmable
Gain
Gain adjusted by
INPPGAVOL
-14 -12 -10 dB
Programmable Gain Step Size Guaranteed monotonic 0.75 dB
Input PGA Mute Attenuation INPPGAMUTE 92 dB
Input Gain Boost PGABOOST= 0 0 dB
Input Gain Boost PGABOOST = 1 +20 dB
Auxiliary Analogue Inputs (AUX)
Full-scale Input Signal Level 2AVDD/3.3 Vrms
Input Resistance Input boost and mixer
enabled, at 0dB gain
20 kΩ
Input Capacitance All analogue Inputs 10 pF
Maximum Gain from AUX input PGA
mixers
Gain adjusted by
AUX2BOOSTVOL
+4.0 +6 +7.5 dB
Minimum Gain from AUX input PGA
mixers
Gain adjusted by
AUX2BOOSTVOL
-14 -12 -9 dB
AUX2BOOSTVOL step size Guaranteed monotonic 3 dB
Analogue to Digital Converter (ADC) - Input from MICN and MICP in differential configuration to input PGA
INPPGAVO, PGABOOST and ADCVOL = 0dB
Signal to Noise Ratio 3SNR
A-weighted
AVDD=3.3V
88 91 dB
Total Harmonic Distortion 4 THD
-1dBV Input
AVDD=3.3V
-80 -75 dB
Total Harmonic Distortion + Noise 5 THD+N -1dBV Input
AVDD=3.3V
-75 -68 dB
Channel Separation 6
1kHz full scale input signal 100 dBFS

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Test Conditions
DCVDD = 1.8V, AVDD = DBVDD = 3.3V, SPKVDD =3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise
stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Digital to Analogue Converter (DAC) to MONO Output with 10kΩ/ 50pF load and DACVOL 0dB
Full-scale output 1DACVOL = 0dB AVDD/3.3 Vrms
Signal to Noise Ratio 3 SNR A-weighted
AVDD=SPKVDD=3.3V
93 98 dB
Total Harmonic Distortion 4
THD 0dBFS input
AVDD=SPKVDD=3.3V
-80 -75 dBFS
Total Harmonic Distortion + Noise 5
THD+N 0dBFS input
AVDD=SPKVDD=3.3V
-78 -74 dBFS
Channel Separation 6
1kHz signal 100 dB
MICP and MICN input PGA to input boost stage into 10kΩ/ 50pF load on SPKOUTP and SPKOUTP
INPPGAVOL, PGABOOST = 0dB
Full-scale output voltage, 0dB gain SPKVDD/3.3 Vrms
Signal to Noise Ratio 3 SNR A-weighted
AVDD=SPKVDD=3.3V
94 99 dB
Total Harmonic Distortion 4
THD full-scale signal
AVDD=SPKVDD=3.3V
-90 -85 dBFS
Total Harmonic Distortion + Noise 5
THD+N full-scale signal
AVDD=SPKVDD=3.3V
-87 -82 dBFS
Channel Separation 6100 dB
DAC to Speaker Output (SPKOUTP, SPKOUTN with 8Ωbridge tied load) Bypass mode
Output Power Po Output power is closely correlated with THD see below
Total Harmonic Distortion 4THD Po=350mW, RL = 8Ω
SPKVDD=3.3V
0.03
-70
-60
%
dB
Signal to Noise Ratio 3SNR A-weighted
SPKVDD=3.3V
93.5 98 dB
Power Supply Rejection Ratio
(50Hz-22kHz)
PSRR RL = 8ΩBTL 50 dB
AUX In to Headphone Output (SPKOUTP, SPKOUTN with 16R resistive load to GND) Bypass mode
Signal to Noise Ratio 3SNR A-weighted
SPKVDD=3.3V
95 99 dB
Total Harmonic Distortion 4
THD Po=20mW, RL = 16Ω
SPKVDD=3.3V
0.02
-74
-67 %
dB
Microphone Bias
MBVSEL=0 0.9*AVDD V
Bias Voltage
MBVSEL=1 0.65*AVDD V
Bias Current Source for VMICBIAS within +/-3% 3 mA
Output Noise Voltage 1kHz to 20kHz 15 nV/√Hz
Digital Input / Output
Input HIGH Level VIH 0.7×
DBVDD
V
Input LOW Level VIL 0.3×DBVDD V
Output HIGH Level VOH I
OL=1mA 0.9×
DBVDD
V
Output LOW Level VOL I
OH-1 m A 0.1xDBVDD V
Input Capacitance All digital pins 10 pF

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TERMINOLOGY
1. Full-scale input and output levels scale in relation to AVDD or SPKVDD depending upon the input or output used. For
example, when AVDD = 3.3V, 0dBFS = 1Vrms (0dBV). When AVDD < 3.3V the absolute level of 0dBFS will decrease
with a linear relationship to AVDD.
2. Input level to RIP and LIP in differential configurations is limited to a maximum of -3dB or performance will be
reduced.
3. Signal-to-noise ratio (dB) – SNR is the difference in level between a reference full scale output signal and the device
output with no signal applied. This ratio is also called idle channel noise. (No Auto-zero or Automute function is
employed in achieving these results).
4. Total Harmonic Distortion (dB) – THD is the difference in level between a reference output signal and the first seven
harmonics of that signal. The reference output signal need not be at full scale amplitude; THD is typically measured
using an output power of 20mW into a 16ohm load, corresponding to a reference signal level of -5dB. However the
stated test conditions include input signal level, signal gain settings, output load characteristics and power supply
voltages To calculate the ratio, the fundamental frequency of the output signal is notched out and an RMS value of
the next seven harmonics is calculated.
5. Total Harmonic Distortion plus Noise (dB) – THD+N is the difference in level between a reference output signal and
the sum of the harmonics, wide-band noise and interference on the output signal. To calculate the ratio, the
fundamental frequency of the output signal is notched out and an RMS value of the total harmonics, wide-band noise
and interference is calculated.
6. Channel Separation (dB) – Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down