Wolfson WM8580 User manual

w WM8580
Multichannel CODEC with S/PDIF Transceiver
WOLFSON MICROELECTRONICS plc
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Product Preview, March 2006, Rev 1.0
Copyright 2006 Wolfson Microelectronics plc
DESCRIPTION
The WM8580 is a multi-channel audio CODEC with S/PDIF
transceiver. The WM8580 is ideal for DVD and surround
sound processing applications for home hi-fi, automotive
and other audiovisual equipment.
Integrated into the device is a stereo 24-bit multi-bit sigma
delta ADC with support for digital audio output word lengths
from 16-bit to 32-bit, and sampling rates from 8kHz to
192kHz.
Also included are three stereo 24-bit multi-bit sigma delta
DACs, each with a dedicated oversampling digital
interpolation filter. Digital audio input word lengths from 16-
bits to 32-bits and sampling rates from 8kHz to 192kHz are
supported. Each DAC channel has independent digital
volume and mute control.
Two independent audio data interfaces support I2S, Left
Justified, Right Justified and DSP digital audio formats.
Each audio interface can operate in either Master Mode or
Slave Mode.
The S/PDIF transceiver is IEC-60958-3 compatible and
supports frame rates from 32k/s to 192k/s. It has four
multiplexed inputs and one output. Status and error
monitoring is built-in and results can reported over the serial
interface or via GPO pins. S/PDIF Channel Block
configuration is also supported.
The device has two PLLs that can be configured
independently to generate two system clocks for internal or
external use.
Device control and setup is via a 2-wire or 3-wire (SPI
compatible) serial interface. The serial interface provides
access to all features including channel selection, volume
controls, mutes, de-emphasis, S/PDIF control/status, and
power management facilities. Alternatively, the device has a
Hardware Control Mode where device features can be
enabled/disabled using selected pins.
The device is available in a 48-lead TQFP package.
FEATURES
•Mutli-channel CODEC with 3 Stereo DACs and 1 Stereo
ADC
•Integrated S/PDIF / IEC-60958-3 transceiver
•Audio Performance
−103dB SNR (‘A’ weighted @ 48kHz) DAC
−-90dB THD (48kHz) DAC
−100dB SNR (‘A’ weighted @ 48kHz) ADC
−-90dB THD (48kHz) ADC
•DAC Sampling Frequency: 8kHz – 192kHz
•ADC Sampling Frequency: 8kHz – 192kHz
•Independent ADC and DAC Sample Rates
•2 and 3-Wire Serial Control Interface with readback, or
Hardware Control Interface
•GPO pins allow visibility of user selected status flags
•Programmable Audio Data Interface Modes
−I
2S, Left, Right Justified or DSP
−16/20/24/32 bit Word Lengths
•Three Independent Stereo DAC Outputs with Digital
Volume Controls
•Two Independent Master or Slave Audio Data Interfaces
•Flexible Digital Interface Routing with Clock Selection
Control
•2.7V to 5.5V Analogue, 2.7V to 3.6V Digital Supply
Operation
•48-lead TQFP Package
APPLICATIONS
•Digital TV
•DVD Players and Receivers
•Surround Sound AV Processors and Hi-Fi systems
•Automotive Audio

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BLOCK DIAGRAM

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TABLE OF CONTENTS
DESCRIPTION .....................................................................................................................................................................1
FEATURES ..........................................................................................................................................................................1
APPLICATIONS ...................................................................................................................................................................1
BLOCK DIAGRAM ...............................................................................................................................................................2
TABLE OF CONTENTS........................................................................................................................................................ 3
PIN CONFIGURATION.........................................................................................................................................................4
ORDERING INFORMATION................................................................................................................................................. 4
PIN DESCRIPTION ..............................................................................................................................................................5
MULTI-FUNCTION PINS.................................................................................................................................................. 6
ABSOLUTE MAXIMUM RATINGS ....................................................................................................................................... 7
RECOMMENDED OPERATING CONDITIONS....................................................................................................................8
ELECTRICAL CHARACTERISTICS.....................................................................................................................................8
TERMINOLOGY.............................................................................................................................................................10
MASTER CLOCK TIMING.............................................................................................................................................. 11
DIGITAL AUDIO INTERFACE – MASTER MODE.......................................................................................................... 12
DIGITAL AUDIO INTERFACE – SLAVE MODE ............................................................................................................. 13
CONTROL INTERFACE TIMING – 3-WIRE MODE ....................................................................................................... 14
CONTROL INTERFACE TIMING – 2-WIRE MODE ....................................................................................................... 15
DEVICE DESCRIPTION ..................................................................................................................................................... 16
INTRODUCTION............................................................................................................................................................16
CONTROL INTERFACE OPERATION...........................................................................................................................17
DIGITAL AUDIO INTERFACES......................................................................................................................................21
AUDIO DATA FORMATS ............................................................................................................................................... 23
AUDIO INTERFACE CONTROL.....................................................................................................................................27
DAC FEATURES............................................................................................................................................................29
ADC FEATURES............................................................................................................................................................35
DIGITAL ROUTING OPTIONS .......................................................................................................................................36
CLOCK SELECTION...................................................................................................................................................... 38
PHASE-LOCKED LOOPS AND S/PDIF CLOCKING (SOFTWARE MODE)................................................................... 44
PHASE-LOCKED LOOPS AND S/PDIF CLOCKING (HARDWARE MODE) .................................................................. 52
S/PDIF TRANSCEIVER ................................................................................................................................................. 53
POWERDOWN MODES ................................................................................................................................................ 65
INTERNAL POWER ON RESET CIRCUIT.....................................................................................................................67
HARDWARE CONTROL MODE .................................................................................................................................... 69
REGISTER MAP ............................................................................................................................................................72
DIGITAL FILTER CHARACTERISTICS.............................................................................................................................. 86
DAC FILTER RESPONSES ........................................................................................................................................... 86
DIGITAL DE-EMPHASIS CHARACTERISTICS .............................................................................................................87
ADC FILTER RESPONSES ........................................................................................................................................... 88
ADC HIGH PASS FILTER ..............................................................................................................................................88
RECOMMENDED EXTERNAL COMPONENTS.................................................................................................................89
PACKAGE DIMENSIONS................................................................................................................................................... 91
IMPORTANT NOTICE ........................................................................................................................................................92
ADDRESS:..................................................................................................................................................................... 92

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PIN CONFIGURATION
ORDERING INFORMATION
DEVICE TEMPERATURE
RANGE PACKAGE MOISTURE SENSITIVITY LEVEL
PEAK
SOLDERING
TEMPERATURE
WM8580GEFT/V -25 to +85oC 48-lead TQFP
(Pb-free) MSL1 260°C
WM8580GEFT/RV -25 to +85oC 48-lead TQFP
(Pb-free, tape and reel) MSL1 260°C
Note:
Reel quantity = 2,200

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PIN DESCRIPTION
PIN NAME TYPE DESCRIPTION
1 PGND Supply PLL ground
2 PVDD Supply PLL positive supply
3 XTI Digital Input Crystal or CMOS clock input
4 XTO Digital Output Crystal output
5 MFP10 Digital Output Multi-Function Pin (MFP) 10. See Table 1 for details of all MFP pins.
6 MFP9 Digital Output Multi-Function Pin (MFP) 9. See Table 1 for details of all MFP pins.
7 MFP8 Digital Input/Output Multi-Function Pin (MFP) 8. See Table 1 for details of all MFP pins.
8 MFP7 Digital Input/Output Multi-Function Pin (MFP) 7. See Table 1 for details of all MFP pins.
9 MFP6 Digital Input/Output Multi-Function Pin (MFP) 6. See Table 1 for details of all MFP pins.
10 SPDIFOP Digital Output S/PDIF transmitter output.
11 MFP5 Digital Input/Output Multi-Function Pin (MFP) 5. See Table 1 for details of all MFP pins.
12 MFP4 Digital Input/Output Multi-Function Pin (MFP) 4. See Table 1 for details of all MFP pins.
13 MFP3 Digital Input/Output Multi-Function Pin (MFP) 3. See Table 1 for details of all MFP pins.
14 SPDIFIN1 Digital Input S/PDIF receiver input 1
15 CLKOUT Digital Output PLL or crystal oscillator clock output
16 DVDD Supply Digital positive supply
17 DGND Supply Digital ground
18 MUTE Digital Input/Output DAC mute-all Input / All-DAC Infinite Zero Detect (IZD) flag output
19 DIN1 Digital Input Primary Audio Interface (PAIF) receiver data input 1
20 DIN2 Digital Input Primary Audio Interface (PAIF) receiver data input 2
21 DIN3 Digital Input Primary Audio Interface (PAIF) receiver data input 3
22 PAIFRX_LRCLK Digital Input/Output Primary Audio Interface (PAIF) receiver left/right word clock
23 PAIFRX_BCLK Digital Input/Output Primary Audio Interface (PAIF) receiver bit clock
24 MCLK Digital Input/Output System Master clock; 256, 384, 512, 768, 1024 or 1152 fs
25 DOUT Digital Output Primary Audio Interface (PAIF) transmitter data output
26 PAIFTX_LRCLK Digital Input/Output Primary audio interface transmitter left/right word clock
27 MFP1 Digital Input/Output Multi-Function Pin (MFP) 1. See Table 1 for details of all MFP pins.
28 MFP2 Digital Input/Output Multi-Function Pin (MFP) 2. See Table 1 for details of all MFP pins.
29 HWMODE Digital Input Configures control to be either Software Mode or Hardware Mode
30 SWMODE Digital Input/Output Configures software interface to be either 2-wire or 3-wire. See note 2.
31 SDO Digital Output 3-wire control interface data output. See note 3.
32 SDIN Digital Input/Output Control interface data input (and output under 2-wire control)
33 SCLK Digital Input Control interface clock
34 CSB Digital Input 3-wire control interface latch signal / device address selection
35 AINR Analogue Input ADC Right Channel Input
36 AINL Analogue Input ADC Left Channel Input
37 ADCREFP Analogue Output ADC reference buffer decoupling pin; 10uF external decoupling
38 VMID Analogue Output Midrail divider decoupling pin; 10uF external decoupling
39 AGND Supply Analogue ground
40 AVDD Supply Analogue positive supply
41 VOUT1L Analogue Output DAC channel 1 left output
42 VOUT1R Analogue Output DAC channel 1 right output
43 VOUT2L Analogue Output DAC channel 2 left output
44 VOUT2R Analogue Output DAC channel 2 right output
45 VREFP Analogue Input DAC and ADC positive reference
46 VREFN Analogue Input DAC and ADC ground reference

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PIN NAME TYPE DESCRIPTION
47 VOUT3L Analogue Output DAC channel 3 left output
48 VOUT3R Analogue Output DAC channel 3 right output
Notes :
1. Digital input pins have Schmitt trigger input buffers. Pins 32, 33, 34 are 5V tolerant.
2. In hardware control mode, pin 30 is used for UNLOCK flag output.
3. In hardware control mode, pin 31 is used for NON_AUDIO flag output.
MULTI-FUNCTION PINS
The WM8580 has 8 Multi-Function Input/Output pins (MFP1 etc.). The function and direction (input/output) of these pins
are configured using the HWMODE input pin and software register control as shown below. If HWMODE is set, the MFPs
have the function shown in column 1 of Table 1. If HWMODE is not set, and the register SAIF_EN is set, the MFPs have
the function shown in column 2. Otherwise, the GPOnOP registers determine the MFP function as shown in columns 3 and
4.
PIN NAME HARDWARE
CONTROL MODE
FUNCTION
1
SECONDARY AUDIO
INTERFACE FUNCTION
2
S/PDIF INPUT &
INDEPENDENT
CLOCKING
3
GENERAL PURPOSE
OUTPUT FUNCTION
4
MFP1 PAIFTX_BCLK n/a1PAIFTX_BCLK2GPO1
MFP2 ADCMCLK n/a1ADCMCLK3GPO2
MFP3 DR1 n/a1SPDIFIN2 GPO3
MFP4 DR2 n/a1SPDIFIN3 GPO4
MFP5 DR3 n/a1SPDIFIN4 GPO5
MFP6 DR4 SAIF_BCLK GPO6 GPO6
MFP7 ALLPD SAIF_LRCLK GPO7 GPO7
MFP8 C SAIF_DIN GPO8 GPO8
MFP9 SFRM_CLK SAIF_DOUT GPO9 GPO9
MFP10 192BCLK n/a1GPO10 GPO10
Table 1 Multi-Function Pin Configuration
Notes:
1. These pins are not used as part of the Secondary Audio Interface, so their function is that of either Column 3 or
Column 4.
2. MFP1 can by GPO1 only if ADC_CLKSEL and PAIFTXMST_CLKSEL (if in master mode) source MCLK.
3. MFP2 can be GPO2 if neither ADC_CLKSEL, TX_CLKSEL or SAIFMST_CLKSEL (if in master mode) source
ADCMCLK.
HWMODE = 1
GPIOnOP
SAIF_EN = 1
Y
Y
N
N

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PIN FUNCTION TYPE DESCRIPTION
PAIFTX_BCLK Digital Input/Output Primary Audio Interface Transmitter (PAIFTX) Bit Clock
ADCMCLK Digital Input Master ADC clock; 256fs, 384fs, 512fs ,786fs, 1024fs or 1152fs
SAIF_DIN Digital Input Secondary Audio Interface (SAIF) Receiver data input
SAIF_DOUT Digital Output Secondary Audio Interface (SAIF) Transmitter data output
SAIF_BCLK Digital Input/Output Secondary Audio Interface (SAIF) Bit Clock
SAIF_LRCLK Digital Input/Output Secondary Audio Interface (SAIF) Left/Right Word Clock
SPDIFIN2/3/4 Digital Input S/PDIF Receiver Input
GPO1 – GPO10 Digital Output General Purpose Output
DR1/2/3/4 Digital Input Internal Digital Routing Configuration in Hardware Mode
ALLPD Digital Input Chip Powerdown in Hardware Mode
C Digital Output Recovered channel-bit for current S/PDIF sub-frame
SFRM_CLK Digital Output Indicates current S/PDIF sub-frame:
1 = Sub-frame A
0 = Sub-frame B
192BCLK Digital Output Indicates start of S/PDIF 192-frame block. High for duration of frame 0.
Table 2 Multi-Function Pin Description
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
The WM8580 has been classified as MSL1, which has an unlimited floor life at <30oC / 85% Relative Humidity and therefore will
not be supplied in moisture barrier bags.
CONDITION MIN MAX
Digital supply voltage -0.3V +3.63V
Analogue supply voltage -0.3V +7V
PLL supply voltage -0.3V +5V
Voltage range digital inputs (SCLK, CSB & SDIN only) DGND -0.3V +7V
Voltage range digital inputs DGND -0.3V DVDD + 0.3V
Voltage range analogue inputs 1AGND -0.3V
PGND -0.3V
AVDD +0.3V
PVDD +0.3V
Master Clock Frequency 37MHz
Operating temperature range, TA-25°C +85°C
Storage temperature prior to soldering 30°C max / 85% RH max
Storage temperature after soldering -65°C +150°C
Pb Free Package body temperature (soldering 10 seconds) +260°C
Package body temperature (soldering 2 minutes) +183°C
Notes: 1. Analogue and digital grounds must always be within 0.3V of each other.

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RECOMMENDED OPERATING CONDITIONS
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Digital supply range DVDD 2.7 3.6 V
Analogue supply range AVDD, PVDD 2.7 5.5 V
Ground AGND, VREFN, DGND.
PGND
0 V
Difference DGND to
AGND/PGND
-0.3 0 +0.3 V
Note: Digital supply DVDD must never be more than 0.3V greater than AVDD.
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, PGND, DGND = 0V, TA = +25oC, 1kHz Signal, fs = 48kHz,
24-Bit Data, Slave Mode, MCLK, ADCMCLK = 256fs, 1Vrms Input Signal Level unless otherwise stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
DAC Performance (Load = 10kΩ, 50pF)
0dBFs Full scale output voltage 1.0 x
VREFP/5
V
rms
A-weighted,
@ fs = 48kHz
103 dB
Unweighted,
@ fs = 48kHz
100 dB
A-weighted,
@ fs = 48kHz, AVDD =
3.3V
99 dB
A-weighted,
@ fs = 96kHz
101 dB
Unweighted,
@ fs = 96kHz
98 dB
A-weighted,
@ fs = 96kHz, AVDD =
3.3V
99 dB
A-weighted,
@ fs = 192kHz
101 dB
Unweighted,
@ fs = 192kHz
98 dB
Signal to Noise Ratio (Note
1,2,4)
SNR
A-weighted,
@ fs = 192kHz, AVDD
= 3.3V
99 dB
Dynamic Range (Note 2,4) DNR A-weighted, -60dB full
scale input
103 dB
1
kHz, 0dB Full Scale @
fs = 48kHz
-90 dB
1
kHz, 0dB Full Scale @
fs = 96kHz
-87 dB
Total Harmonic Distortion THD
1
kHz, 0dB Full Scale @
fs = 192kHz
-84 dB
DAC Channel separation 100 dB
Mute Attenuation 1kHz Input, 0dB gain 100 dB
Output Offset Error 2 mV

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Test Conditions
AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, PGND, DGND = 0V, TA = +25oC, 1kHz Signal, fs = 48kHz,
24-Bit Data, Slave Mode, MCLK, ADCMCLK = 256fs, 1Vrms Input Signal Level unless otherwise stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
1kHz 100mVp-p 50 dB
Power Supply Rejection Ratio PSRR
20Hz to 20kHz
100mVp-p
45 dB
ADC Performance
Full Scale Input Signal Level (for
ADC 0dB Input)
1.0 x
VREFP/5
V
rms
Input resistance 20 kΩ
Input capacitance 10 pF
A-weighted,
@ fs = 48kHz
100 dB
Unweighted,
@ fs = 48kHz
97 dB
A-weighted,
@ fs = 48kHz, AVDD =
3.3V
97 dB
A-weighted,
@ fs = 96kHz
97 dB
Unweighted,
@ fs = 96kHz
94 dB
A-weighted,
@ fs = 96kHz, AVDD =
3.3V
94 dB
A-weighted,
@ fs = 192kHz
97 dB
Unweighted,
@ fs = 192kHz
94 dB
Signal to Noise Ratio (Note
1,2,4)
SNR
A-weighted,
@ fs = 192kHz, AVDD
= 3.3V
94 dB
1kHz, -1dB Full Scale
@ fs = 48kHz
-90 dB
1kHz, -1dB Full Scale
@ fs = 96kHz
-88 dB
Total Harmonic Distortion THD
1kHz, -1dB Full Scale
@ fs = 192kHz
-85 dB
Dynamic Range DNR -60dB FS 100
ADC Channel Separation 1kHz Input 100 dB
Channel Level Matching (Note
4)
1KHz Signal 0.1 dB
Channel Phase Deviation 1kHz Signal 0.0001 Degree
Offset Error HPF On
HPF Off
0
100
LSB
LSB
1kHz 100mVpp 50 dB
Power Supply Rejection Ratio PSRR
20Hz to 20kHz
100mVpp
45 dB
Digital Logic Levels (CMOS Levels)
Input LOW level VIL 0.3 x DVDD V
Input HIGH level VIH 0.7 x DVDD V
Input leakage current -1 ±0.2 +1 µA
Input capacitance 5 pF
Output LOW VOL IOL=1mA 0.1 x DVDD V
Output HIGH VOH IOH=-1mA 0.9 x DVDD V

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Test Conditions
AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, PGND, DGND = 0V, TA = +25oC, 1kHz Signal, fs = 48kHz,
24-Bit Data, Slave Mode, MCLK, ADCMCLK = 256fs, 1Vrms Input Signal Level unless otherwise stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Analogue Reference Levels
Reference voltage VVMID VREFP/2 –
50mV
VREFP/2 VREFP/2 +
50mV
V
Potential divider resistance RVMID VREFP to VMID and
VMID to VREFN
20 kΩ
S/PDIF Transceiver Performance
Jitter on recovered clock 50 ps
S/PDIF Input Levels CMOS MODE
Input LOW level VIL 0.3 X DVDD V
Input HIGH level VIH 0.7 X DVDD V
Input capacitance 1.25 pF
Input Frequency 36 MHz
S/PDIF Input Levels Comparator MODE
Input capacitance 1.31 pF
Input resistance 18 Ω
Input frequency 25 MHz
Input Amplitude 200 0.5 X DVDD mV
PLL
Period Jitter 80 ps(rms)
XTAL
Input XTI LOW level VXIL 0 557 mV
Input XTI HIGH level VXIH 853 mV
Input XTI capacitance CXJ 3.32 4.491 pF
Input XTI leakage IXleak 28.92 38.96 mA
Output XTO LOW VXOL 15pF load capacitors 86 278 mV
Output XTO HIGH VXOH 15pF load capacitors 1.458 1.942 V
Supply Current
Analogue supply current AVDD, VREFP = 5V 45 mA
Analogue supply current AVDD, VREFP = 3.3V 30 mA
Digital supply current DVDD = 3.3V 16 mA
Power Down 10 uA
Notes:
1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’
weighted.
2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use
such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical
Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic
specification values.
3. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).
TERMINOLOGY
1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output
with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).
2. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal.
Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB
to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB).
3. THD (dB) - THD is a ratio, of the rms values, of Distortion/Signal.
4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).
5. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down one channel and measuring the other.
6. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.