Advantech EVA-X4300 User manual

User Manual
EVA-X4300
System Design Guide

EVA-X4300 System Design Guide ii
Copyright
Advantech reserves the right to make changes without further notice to any products
or data herein to improve reliability, function, or design. Information furnished by
Advantech is believed to be accurate and reliable. However, Advantech does not
assure any liability arising out of the application or use of this information, nor the
application or use of any product or circuit described herein, neither does it convey
any license under its patent rights nor the rights of others.
Copyright © 2008 Advantech Co., Ltd. All rights reserved.
Part No. 2006X43020 Edition 1
Printed in Taiwan August 2008

iii EVA-X4300 System Design Guide
Contents
Chapter 1 Overview...............................................1
1.1 Overview ................................................................................................... 2
Chapter 2 Layout Guide........................................3
2.1 BGA Layout Guideline............................................................................... 4
2.2 Package Outline........................................................................................ 6
2.3 Signal Arrangement .................................................................................. 8
2.4 EVA-X4300 Power Requirement............................................................. 11
2.5 General Layout Rule ............................................................................... 11
2.6 Crystal / External Oscillator..................................................................... 15
2.7 DDR2 Interface ....................................................................................... 16
2.8 Switching Power...................................................................................... 19
2.9 PCI Interface ........................................................................................... 20
2.10 USB 2.0................................................................................................... 21
2.11 IDE .......................................................................................................... 23
2.12 LPC Interface .......................................................................................... 24
2.13 10/100 LAN ............................................................................................. 25
Appendix A References .........................................29
A.1 References.............................................................................................. 30

EVA-X4300 System Design Guide iv

Chapter 1
1Overview

EVA-X4300 System Design Guide 2
1.1 Overview
The EVA-X4300 is a fully static 32-bit x86-based processor that is compatible with a
wide-range of PC peripherals, applications and operating systems, such as DOS,
WinCE, Linux, and most popular 32-bit RTOSs (Real Time OS). It enables maximum
software re-use based on its feature of legacy compatibility. The EVA-X4300 inte-
grates 32 KB write-through direct map L1 cache, a PCI bus interface at 33 MHz, an 8/
16-bit ISA bus interface, SDR SDRAM, DDR2 SDRAM, a ROM controller, IPC (Inter-
nal Peripheral Controller) with DMA and interrupt timer/counter included, FIFO UART,
SPI (Serial Peripheral Interface), LPC (low pin count), a USB 1.1/2.0 host controller,
LoC (LAN on Chip), an IDE controller, and 256 KB flash within a single 581-pin BGA
package to form a an SoC (System-on-Chip) processor. The EVA-X4300 integrates
comprehensive features and rich I/O flexibility within a single System-on-Chip, to
reduce board design complexity and shorten product development schedules. Taking
advantage of ultra low power consumption, the EVA-X4300 is able to operate in a
wide range of temperatures without additional thermal design. With the commitment
of long term supply guaranteed for the EVA-X4300, customers can extend product
life cycle and receive a maximum return on investment.
The EVA-X4300 provides an ideal solution for embedded systems and communica-
tion products (such as the thin client, NAT router, home gateway, access point and
tablet PC) producing optimal performance.
This system design guide provides detailed usage information of the highly inte-
grated EVA-X4300 SoC processor.

Chapter 2
2Layout Guide

EVA-X4300 System Design Guide 4
2.1 BGA Layout Guideline
The package of EVA-X4300 is 581-ball PBGA. The ball diameter is 0.6 mm (24 mil);
ball pitch is 1 mm (40 mil). There are 6 rows of balls arranged along the edge of the
package.
For 6-layer:
!Ball pad diameter: 24 mil
!Traces width/ spacing for Signals: 5.5/ 5 mil
!Trace width for Power and Ground: 20 mils
!Vias PAD/ Drill diameter for all Signals: 14/ 8 mil
!Via-to-via spacing (center to center): 40 mil
!Via-to-pad spacing (center to center): 30 mil

5 EVA-X4300 System Design Guide
Chapter 2 Layout Guide
For 4-layer:
!Ball pad diameter: 14 mil
!Traces width/ spacing for Signals: 5/ 5 mil
!Trace width for Power and Ground: 20 mils
!Vias PAD/ Drill diameter for all Signals: 22/ 12 mil
!Via-to-via spacing (center to center): 40 mil
!Via-to-pad spacing (center to center): 30 mil
Note! All the Vias must be covered by solder mask. To minimize inductance,
power vias should be as large as possible and take good care of the
inadvertently cut of the ground and power planes.

EVA-X4300 System Design Guide 6
2.2 Package Outline

7 EVA-X4300 System Design Guide
Chapter 2 Layout Guide

EVA-X4300 System Design Guide 8
2.3 Signal Arrangement
Top Vi ew
26 ○○○○○○○○○○○○○○○○○○○○○○○○○○
25 ○○○○○○○○○○○○○○○○○○○○○○○○○○
24 ○○○○○○○○○○○○○○○○○○○○○○○○○○
23 ○○○○○○○○○○○○○○○○○○○○○○○○○○
22 ○○○○○○○○○○○○○○○○○○○○○○○○○○
22 ○○○○○○○○○○○○○○○○○○○○○○○○○○
20 ○○○○○○ ○○○○○○
19 ○○○○○○ ○○○○○○
18 ○○○○○○ ○○○○○○○○○○ ○○○○○○
17 ○○○○○○ ○○○○○○○○○○ ○○○○○○
16 ○○○○○○ ○○○○○○○○○○ ○○○○○○
15 ○○○○○○ ○○○○○○○○○○ ○○○○○○
14 ○○○○○○ ○○○○○○○○○○ ○○○○○○
13 ○○○○○○ ○○○○○○○○○○ ○○○○○○
12 ○○○○○○ ○○○○○○○○○○ ○○○○○○
11 ○○○○○○ ○○○○○○○○○○ ○○○○○○
10 ○○○○○○ ○○○○○○○○○○ ○○○○○○
9○○○○○○ ○○○○○○○○○○ ○○○○○○
8○○○○○○ ○○○○○○
7○○○○○○○ ○○○○○○
6○○○○○○○○○○○○○○○○○○○○○○○○○○
5○○○○○○○○○○○○○○○○○○○○○○○○○○
4○○○○○○○○○○○○○○○○○○○○○○○○○○
3○○○○○○○○○○○○○○○○○○○○○○○○○○
2○○○○○○○○○○○○○○○○○○○○○○○○○○
1○○○○○○○○○○○○○○○○○○○○○○○○○○
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
Pin #1 Corner

9 EVA-X4300 System Design Guide
Chapter 2 Layout Guide
ABCDEFGHJKLMN
26 NC AD24 TRDY_ PCIRST_ AD13 AD10 AD5 AD3 AD1 TXP RXP DP1 DP0
25 AD25 CBE_3 IRDY_ STOP_ AD14 AD9 AD7 AD4 AD2 TXN RXN DM1 DM0
24 AD26 CBE_2 FRAME_ DEVSEL_ AD15 CBE_0 PAR AD0 ISET VCCA0 VCCA1 VSSA1 AVSS0
23 AD27 AD16 AD17 TEST0 TEST4 VCC_SPI AD11 INTA_ VCCAPLL VSSAPLL VSSA0 VCCABG AVDDPLL
0
22 AD28 AD18 AD19 TEST2 TEST1 ATSTP CBE_1 AD12 AD6 Duplex Link/Active VSSABG AVDD0
21 AD29 AD20 AD21 GND_SPI TEST3 ATSTN ROM_CS_ AD8 TXC0 TXEN0 RXDV0 RXC0 RTC_AS_
GPIO_37
20 PCICLK_2 AD30 AD31 AD23 AD22 INTC_
19 PCICLK_0 PREQ2 PGNT0 PGNT2 INTD_ INTB_
18 PCICLK_1 PREQ1 PREQ0 PGNT1 VCC3V VCC3V TXD0_3 TXD0_0 RXD0_0 RXD0_3 Vdd_io
17 MD4 MD0 MD14 DQM1 GNDK GND_R3 TXD0_2 TXD0_1 RXD0_1 RXD0_2 Vdd_io
16 MD3 MD1 MD9 MD15 MD15 GND_R3 MDC MDIO COL0 VCC3V GND_R3
15 MD2 MD7 MD11 MD12 MD8 GND_R3 VCC3V VCC3V VCC3V VCC3V GND_R3
14 MD5 DQM0 MD13 DQS0 MD10 VCCK VCCK VCCK VCCK VCCK GND_R3
13 MD6 CS_1 WE_ RAS_ CS_0 VCCK GND_R3 GND_R3 GND_R3 GND_R3 GND_R3
12 MA10 MA6 BA2 BA0 CAS_ BA1 GNDK GNDK GNDK GND_R3 GND_R3
11 MA1 MA5 MA7 MA9 MA11 MA13 GNDK GNDK GNDK GNDK GND_R3
10 MA0 MA3 MA4 VDLL0 GNDDLL0 MA12 GNDK GNDK GNDK GNDK GND_R3
9SDRAM-
CLKN
SDRAM-
CLKP MA2 VDLL1 GNDDLL1 MA8 TMS GNDK GNDK GNDK VCCK
8NC NC NC VCCO GNDK VCCK
7NC NC VCCO VCCO GNDK GNDO TCK
6NC NC VCCO GNDO GNDO GNDO TDO TDI SOUT9 SIN9 PE/SDD9 SOUT4 SIN4
5NC NC VCCO GNDO GNDO GNDO GNDO GNDPLL0 GNDPLL1 PD6/SDD6 PD5/SDD5 BUSY/
SDD10
SLCT/
SDD8
4NC NC VCCO VCCO VCCO GNDO VCCK VPLL0 VPLL1 PD7/SDD7 ACK_/
SDD11 PD4/SDD4 ERR_/ SDD14
3NC NC NC NC TEST5 TEST6 SIN3 RTS3_/
SRST_ TESTCLK PD3/SDD3 AFD_/ SDD15
SLIN_/
SDD12 PDD9
2NC NC NC NC TEST7 TEST8 SOUT3 CTS3_/
SIOR_
DCD3_/
SDRQ PD0/SDD0 PD1/SDD1 PD2/SDD2 PINT
1NC NC NC NC NC DTR3_/
SDACK_
RI3/
SIORDY
DSR3_/
SCBLID_
INIT_/
SDD13 PA2 STB_/ SCS0_ PRST_ PDD3
ABCDEFGHJKLMN

EVA-X4300 System Design Guide 10
PRTUVWYAAABACADAEAF
AVDD33_0 DP3 DP2 AVDD33_1 RTC_Xin AVDD3 XOUT_14.
318
POWER_
GOOD
CLK25MO
UT
DCD2_/
PWM0CLK
CTS2_/
PWM1GAT
E
DSR2_/
PWM0GAT
E
NC 26
AVSSPLL0 DM3 DM2 AVSSPLL1 RTC_Xout AVSS3 XIN_14.31
8MTBF CLK24MO ut
DTR2_/
PWM2OU
T
RTS2_/
PWM1OU
T
TXD_EN2/
PWM2GAT
E
SIN2/
PWM2CLK 25
REXT0 AVDD1 AVSS2 REXT1 AVDDPLL
1
SERIRQ Vss_pll_1 Vdd_pll_1 Vdd_pll_0 Vss_pll_0 RI2_/
PWM1CLK
SOUT2/
PWM0OU
T
DCD1_/
GPIO_40 24
AVSS1 AVDD2 LAD0 LAD1 LAD2 LAD3 SPEAKER Vdd_core Vss_io Vdd_io DTR1_/
GPIO_45
CTS1_/
GPIO_47
DSR1_/
GPIO_46 23
RTC_RD_
GPIO_36
RTC_IRQ8
_/GPIO_34 RTC_PS SYSFAILO ut_
Ext_Switch
_fail_
E_SPI_CL
K/
GPIOP_31
E_SPI_DI/
GPIOP_33 Vdd_core Vss_io Vdd_io RI1_/ GPIO_43
SOUT1/
GPIO_41
RTS1_/
GPIO_42 22
VBat VBatGnd RTC_WR_
GPIO_35
ExtSysFailI
n_
EXT_GPC
S_
E_SPI_CS
/
GPIOP_30
E_SPI_DO
/
GPIOP_32
Vdd_core Vss_io Vdd_io TXD_EN1 SIN1/
GPIO_44
GPIO_P2_
1/SA25 21
GPIO_P2_
7/SA31
GPIO_P2_
6/SA30 Vss_io GPIO_P2_ 5/SA29
GPIO_P2_
4/SA28
GPIO_P2_
2/SA26 20
GPIO_P1_
7
GPIO_P2_
0/SA24
GPIO_P1_
6
GPIO_P1_
5
GPIO_P1_
4
GPIO_P1_
019
Vss_io Vss_io Vss_core LFRAME_ LDRQ_ GPIO_P0_
7
GPIO_P1_
3
GPIO_P1_
2
GPIO_P2_
3/SA27
GPIO_P0_
5
GPIO_P0_
318
Vss_io Vss_io Vss_core Vss_io Vss_io GPIO_P0_
6
GPIO_P1_
1
GPIO_P0_
1
GPIO_P0_
0
GPIO_P0_
4
GPIO_P0_
217
Vdd_io Vss_io Vss_core Vss_core KBDATA /
A20GATE_ SD3 IOR_ GPCS0_ GPCS1_ SD15 SD14 16
Vdd_io Vss_io Vss_io Vss_core MSDATA LA20 LA18 LA23 LA19 DRQ7 SD12 15
VCC3V Vdd_io Vss_io Vss_core MSCLK SD4IRQ9SD2 SD6LA21SD11
14
VCC3V Vdd_io Vss_io Vss_core KBCLK_K
BRST_ IOCHCK_ SA2 SBHE_ LA22 SA5 DACK_2 13
VCC3V Vss_io Vdd_core Vss_core Vss_core SA3 DRQ0 Vss_core SD8 MEMW_ SA1 12
VCC3V Vss_io Vdd_core Vss_core Vss_core DRQ5 SA4 Vss_core DACK_6 SD10 DRQ6 11
VCC3V Vdd_io Vss_io Vdd_core Vdd_core SMEMR_ DACK_5 Vss_core SD13 SD9 SYSCLK 10
VCCK Vdd_io Vss_io Vss_io Vss_io SA19 SA17 DRQ2 DACK_0 LA17 MEMR_ 9
SMEMW_ AEN IRQ12 0WS_ IOCHRDY
_OSC14M 8
SD0 SA10 SA8 IRQ5 IRQ7 DACK_7 7
CTS4_/
SIOW_
DCD4_/
SA2
DSR4_/
SCS1_
RTS4_/
SINT
DTR4_/
SA0 Vss_io SD7 Vdd_io Vss_core Vdd_core SA7 IRQ10 REFRESH _6
PDD12 PDD2 PDD1 PDD11 RI4/SA1 Vss_io DRQ3 Vdd_io Vss_core Vdd_core SA18 SA9 TC 5
PDD10 PDD5 PDD6 PDD7 Vss_core Vdd_io SD5 Vdd_io Vss_core Vdd_core DRQ1 BALE IRQ15 4
PIORDY PIOW_ PDD0 PDD8 Vdd_io Vdd_io DACK_3 SA16 DACK_1 SA0 SA11 IOCS16_ IRQ11 3
PA1 PA0 PCS0_ PDD4 PDD15 PDD14 IOW_ SA12 SA14 SA6 SA13 IRQ3 IRQ14 2
PDD13 PDRQ PDACK_ PCBLID_ PIOR_ PCS1_ SD1 SA15 RSET_DR
VIRQ6 IRQ4 MEMCS16 _NC 1
PRTUVWYAAABACADAEAF

11 EVA-X4300 System Design Guide
Chapter 2 Layout Guide
2.4 EVA-X4300 Power Requirement
2.5 General Layout Rule
1. Keep all traces as SHORT as possible.
2. Decoupling is to remove the RF energy injected into the power distribution net-
work from high-speed switching devices.
3. Bypassing is to divert unwanted common-mode RF noise from components or
cables coupling from one area to another.
4. Place 0.01 µF~0.1 µF decoupling capacitors across each pair of VCC and GND
pins. Use the shortest and thickest trace between decoupling capacitor and the
VCC/GND pins.
5. Bulk capacitors ensure that a sufficient amount of DC voltage and current is
available for digital components. At least one bulk capacitor should be located:
! Every VLSI device
! Power connector(s)
! Daughter card slots
! Furthest location from the power connector
! Clock generation circuitry
6. The voltage rating of the bulk capacitors should be 50% higher than the actual
voltage level to prevent self-destruction and/ or voltage surge.
7. For decoupling of DDR2 interface, please check the DDR2 section for more
details.
8. In digital circuits, conductors may be treated as transmission lines if the propa-
gation time (Tdelay) is equal to or greater than the pulse transition time (Trise or
Tfall).
9. The propagation speed on typical PCB is about 170 pS/inch (50 ΩStripline),
150pS/inch (50 ΩMicrostrip).
10. There are 4 properties affect the performance of the transmission line:
! Impedance: reflection/ distortion
! Time delay
! High-Frequency Loss: limit signal bandwidth and transmission distance
! Crosstalk: coupling
DC Volt Tolerance Ripple & Noise Max. Current
3.3V for VCCP ± 0.30 V < 100 mV 185 mA
3.3V for VCCO
1.8V for VCCO
± 0.15 V
± 0.09 V < 50 mA < 245 mA
DC Volt Min. Volt Max. Volt Ripple & Noise Max. Current
1.3V for VCCK 1.30 V 1.40 V < 50 mA 240 mA
Note! CPU clock 300 MHz, DDR2 clock 133 MHz and PCI clock 33 MHz

EVA-X4300 System Design Guide 12
11. It is recommended to add serial damping resistors to all high-speed signals,
especially the clock signals, to reduce high frequency energy and EMI. These
resistors should be placed as close to the driving source as possible.
12. The clock signals should be the first routed trace in any PCB design. Adjacently
routed (guard) ground traces provide shielding and signal return path. These
ground shielding traces should be connect to the ground plane by vias at both
ends. It is best to run all clock signals on the signal plane above a solid ground
plane (on a multi-layer board).
13. If clock/ high-speed signals must make a layer jump, route ground trace adja-
cent to the signals and connect both ends of the ground trace to the GND plane,
to form a RF return path of the signals.
14. The split power planes may cause serious EMI and signal integrity problems for
high-speed signals which run adjacent to the power planes. To minimize these
problems, some decoupling capacitors should be placed between these split
power planes, to enhance RF return current path.
15. Any unused area of the top and bottom signal layers of the PCB can be filled
with copper that is connected to the ground plane through stitches of vias.
16. Example for BGA Power/ Ground routing:

13 EVA-X4300 System Design Guide
Chapter 2 Layout Guide
17. Every I/O connector must be isolated from the digital ground and power planes.
A clean or quiet ground must be located at the point where interconnects leave
the system. Connect (“Bridge”) those grounds with only one connection. Only
those signals required for operation or interconnect can run into the isolated
area.

EVA-X4300 System Design Guide 14
18. Ensure that any signal passing between those sections runs ONLY through the
“bridge”, and run the signals on a layer adjacent to the bridge to maintain RF
return path.
19. If analog or digital power is not required in the isolated area, the unused power
plane can be redefined as a second ground plane, referenced to the main
ground plane by stitches of vias within the isolated area.
20. Connect system Power-on and H/W Reset to “Power-good” input of EVA-
X4300, then use “/PCI_RST” output of EVA-X4300 to reset ALL peripherals.
21. The power-on-strap pins are combined with the memory address bus, which
belong to DRAM power category. So the pull-high resistors should connect to
the same supply (VCCO) of DRAM interface. That is:
For detail of power-on-straps function, please refer to the EVA-X4300 data sheet.
22. Do follow the power-on sequence to prevent excessive current from the power
supplies during power-up and power-down periods:
! Power-up core supply (VDD_CORE), and then power-up the I/O supply
(DVDD).
! Power-down I/O supply (DVDD), and then power-down the core supply
(VDD_CORE).
23. Recommend Termination:
24. Recommended PCB stack up:
a. 4 layers
DRAM type Supply (V) Note
SDR 3.3
DDR2 1.8
Signal Zs (Ω) Termination(Ω) Trace impedance (Ω)
Clocks 24M 26 22 60
PCI clock 7.2 22 60
PCI signal 13.2 51 60
DDR Clocks 19 33 90, Differential
DDR signal 19 33 60
Layer Type Description Material/ Thickness
1 Signal Top Routing Copper/ 0.5~1oz
FR4/ 5mil
2Plane Ground Copper/ 1oz
FR4/ 40mil
3 Plane Power Copper/ 1oz
FR4/ 5mil
4 Signal Bottom Routing Copper/ 0.5~1oz

15 EVA-X4300 System Design Guide
Chapter 2 Layout Guide
b. 6 layers
2.6 Crystal / External Oscillator
The EVA-X4300 requires a 14.318 MHz clock to generate all the internal and external
clocks. Connect an external 14.318 MHz crystal (Parallel-resonant) between Xtal_I
and Xtal_o pins to operate as a Pierce oscillator. The EVA-X4300 specification
requires a frequency tolerance of ±30 parts pre million (PPM).
The other way is to use an external 14.318MHz oscillator, and directly route the oscil-
lator is output into XTALi pin of EVA-X4300. A serial damping resistor and a bypass
capacitor are recommended for EMI reduction. The XTALo pin should leave uncon-
nected. The requirement of the clock is duty cycle should be between 40% ~60%.
Recommended Layout:
!Route the signal traces of the crystal to EVA-X4300 as SHORT as possible.
!When use external crystal with EVA-X4300 internal oscillation circuitry to work
as clock oscillator, be sure to put all the related components close to EVA-
X4300 chip. The ground area under the crystal circuitry should be physically
insolated from system ground plane with only a small bridge between them for
signals crossing. This isolation prevents noise located elsewhere on the PCB
from corrupting the oscillator circuitry.
!The power plane under the crystal/ oscillator area should be void, when no use,
or insolated with exactly the same pattern of ground plane.
!Do NOT run any signals under this area, for EMI and interference enhance-
ment.
Layer Type Description Material/ Thickness
1 Signal Top Routing Copper/ 0.5~1oz
FR4/ 5mil
2Plane Ground Copper/ 1oz
FR4/ 5mil
3Plane Power Copper/ 1oz
FR4/ 40mil
4 Signal Internal Routing Copper/ 1oz
FR4/ 5mil
5Plane Ground Copper/ 1oz
FR4/ 5mil
6 Signal Bottom Routing Copper/ 0.5~1oz

EVA-X4300 System Design Guide 16
2.7 DDR2 Interface
1. It is assumed that the reader is familiar with the specification and the basic elec-
trical operation of the DDR2 interface.
2. EVA-X4300 DDR2 interface substrate conductors’ length for signal integrality:
EVA-X4300 Substrate Conductor Length
Net Name Length in microns
MA[0] 13283.31
MA[1] 12989.16
MA[2] 8745.03
MA[3] 10321.07
MA[4] 10173.85
MA[5] 11728.8
MA[6] 12466.29
MA[7] 11480.64
MA[8] 7638.44
MA[9] 10753.84
MA[10] 13659.62
MA[11] 9367.04
MA[12] 7999.4
MA[13] 8948.06
MD[0] 12939.2
MD[1] 12379.26
MD[2] 12218.38
MD[3] 12868.28
MD[4] 13327.88
MD[5] 11731.55
MD[6] 11817.28
MD[7] 11681.94
MD[8] 11494.07
MD[9] 10379.54
MD[10] 10577.86
MD[11] 11902.14
MD[12] 11610.42
MD[13] 10048.32
MD[14] 10981.68
MD[15] 12062.12
BA0 10484.24
BA1 9914.61
BA2 9542.11
/CAS 9668.98
/CS0 10088.02
/CS1 10430.52
DQM0 12436.31
DQM1 10402.02
DQS0 10560.44
DQS1 9752.32