Alinx AXKU040 User manual

KINTEX UltraScale FPGA
Development Board
AXKU040
User Manual

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Version Record
Version
Date
Release By
Description
Rev 1.1
2021-09-13
Rachel Zhou
First Release

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Table of Contents
Version Record.......................................................................................................2
Part 1: FPGA Development Board Introduction............................................... 4
Part 2: FPGA Chip................................................................................................. 8
Part 3: DDR4 DRAM...........................................................................................10
Part 4: QSPI Flash.............................................................................................. 15
Part 5: Clock configuration.................................................................................16
Part 5.1: 200Mhz differential clock source..............................................16
Part 5.2: 125Mhz differential clock source..............................................16
Part 5.3: 156.25Mhz differential clock source........................................17
Part 6: USB to Serial Port.................................................................................. 19
Part 7: SFP+ Optical fiber interface................................................................. 20
Part 8: HDMI Video Output Interface............................................................... 22
Part 9: Gigabit Ethernet Interface.....................................................................24
Part 10: FMC Expansion Port........................................................................... 27
Part 11: SD Card Slot......................................................................................... 47
Part 12: SMA and SATA Interface.....................................................................49
Part 13: Temperature Sensor............................................................................ 51
Part 14: JTAG Interface......................................................................................52
Part 15: LED Light...............................................................................................53
Part 16: Keys........................................................................................................55
Part 17: Power Supply........................................................................................56
Part 18: Fan..........................................................................................................58
Part 19: Form Factory.........................................................................................59

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Part 1: FPGA Development Board Introduction
The AXKU040 FPGA development board is mainly composed of KINTEX
UltraScale+ chip. It meets users' requirements for high-speed data exchange,
data storage, Video transmission processing, deep learning, artificial
intelligence and industrial control, and it is a "professional" FPGA development
platform. For high-speed data transmission and exchange, pre-verification and
post-application of data processing is possible. This product is very suitable for
students, engineers and other groups engaged in FPGA development.
AXKU040 FPGA development board mounts four 1GB high-speed DDR4
SDRAM chips. FPGA chip configuration uses a 128Mb QSPI FLASH chip.
The AXKU040 FPGA development board expands the rich peripheral
interface, including four 10G optical SFP interfaces, three FMC expansion
interfaces, one UART serial interface, one SD card interface, one HDMI Output,
2 Gigabit Ethernet Interfaces, SAM and SATA Interfaces etc.
The following figure shows the structure of the entire development system:
Figure 1-1: The Schematic Diagram of the AXKU040

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Through this diagram, you can see the interfaces and functions that the
AXKU040 FPGA Development Board contains:
Xilinx KINTEX-7 UltraScale FPGA chip XCKU040
DDR4
With four large-capacity 1GB (4 GB total) high-speed DDR4 SDRAM,
used as FPGA data storage, image analysis cache, data processing.
QSPI FLASH
A 128Mbit QSPI FLASH memory chip can be used as a storage for
FPGA chip configuration files and user data;
4 SFP+ interfaces
The four high-speed transceivers of the GTX transceiver of the FPGA
are connected to the transmission and reception of four optical modules
to realize four high-speed optical fiber communication interfaces. Each
fiber optic data communication receives and transmits at speeds of up
to 12.5 Gb/s.
USB Uart interface
1-channel Uart to USB interface for communication with the computer
for user debugging. The serial port chip adopts the USB-UAR chip of
Silicon Labs CP2102GM, and the USB interface adopts the MINI USB
interface.
HDMI Output Interface
1 HDMI video output interface, using ADV7511 HDMI encoding chip
from ANALOG DEVICE, supports up to 1080P@60Hz output and 3D
output.
Gigabit Ethernet Interface
2-Channel 10/100M/1000M Ethernet RJ45 interface for Ethernet data
exchange with computers or other network devices. The network
interface chip uses Micrel's KSZ9031 industrial grade GPHY chip.
FMC Expansion Interface

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3 standard FMC expansion port, including 2 LPC FMC expansion ports
and 1 HPC FMC expansion port, which can be connected to various
FMC modules of XILINX or ALINX (HDMI input and output modules,
binocular camera modules, high-speed AD modules, etc.).
Micro SD slot
1 Micro SD card holder, used to store operating system image and file
system.
SMA Interface and SATA Interfaces
6 SMA external interfaces and 2 SATA interfaces, the pins are
connected to the transceiver for external high-speed input and output
signals.
Temperature and humidity sensor
Onboard a temperature and humidity sensor chip LM75 for detecting
the temperature and humidity of the environment around the board
EEPROM
One EEPROM 24LC04 with I2C interface, which is Used for IIC bus
communication and storage of some customer-defined information.
JTAG Interface
A 10-pin0.1 spacing standard JTAG ports for FPGA program download
and debugging. Users can debug and download FPGAs through
XILINX downloader.
Clock
A 200Mhz differential crystal onboard provides a stable clock source for
the FPGA system.
A 125Mhz differential crystal onboard provides reference clock for
optical fiber.
A 156.25Mhz differential crystal onboard provides reference clock for
transceiver

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LED Light
6LEDs, 1 power indicator, 1 DONE configuration indicator, 4 user
indicators
Key
2 user keys, 1 reset key, connect to the normal IO of the FPGA.

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Part 2: FPGA Chip
The FPGA development board uses Xilinx's KINTEX UltraScale FPGA
chip, model number XCKU040-2FFVA1156I. The speed class is 2 and the
temperature class is industrial. This model is a FFVA1156 package with 1156
pins and a 1.0mm pitch. The chip naming rules for Xilinx KINTEX UltraScale
FPGA are shown in Figure 2-1 below:
Figure 2-1: The Chip Model Definition of KINTEX UltraScale Series
The main parameters of the FPGA chip XCKU040 are as follows
Name
Specific parameters
Logic Cells
530,250
CLB Look-Up-Tables
242,400
CLB flip-flops
41,600
Block RAM（kb）
21.1
DSP Slices
1,920
PCIe Gen3 x 8
3
XADC
12bit, 1Mbps AD
GTP Transceiver
20, 16.3Gb/s max
Speed Grade
-2
Temperature Grade
Industrial

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FPGA power supply system
XCKU040 FPGA power supplies are VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO VCCO,
VMGTAVCC , VMGTAVTT, VMGTVCCAUK , VMGTAVTTRCAL, VCCADC. VCCINT is the FPGA core power
supply pin, which needs to be connected to 0.95V; VCCBRAM is the power supply
pin of FPGA Block RAM, connect to 0.95V; VCCAUX and VCCAUX_IO are FPGA
auxiliary power supply pin, connect 1.8V; VCCO is the voltage of each BANK of
FPGA, including BANK0, BANK44~48, BANK64~68. VMGTAVCC is the power
supply voltage of the GTH and GTY transceivers inside the FPGA, connected
to 1.0V; VMGTAVTT is the terminal voltage of GTH transmission and reception,
connected to 1.2V. VMGTAVTTRCAL is the transceiver resistance calibration voltage,
connect to 1.2V. VCCADC is the supply voltage of XADC, connected to 1.8V.
The XCKU040 FPGA system requires the power-on sequence as shown in
Figure 2-2.
Figure 2-2: Power-On/Off Power Supply Sequencing

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Part 3: DDR4 DRAM
The AXKU040 FPGA development board is equipped with four Micron
1GB DDR4 chips, model MT40A512M16LY-062EIT. Four DDR4 SDRAMs
form a 64-bit bus width. Because four DDR4 chips are connected to the FPGA,
the DDR4 SDRAM can run at speeds up to 1200MHz, and four DDR4 memory
systems are directly connected to the BANK44, BANK45, and BANK46
interfaces of the FPGA. The specific configuration of DDR4 SDRAM is shown
in Table 3-1.
Bit Number
Chip Model
Capacity
Factory
U45,U47,U48,U49
MT40A512M16LY-062EIT
512M x 16bit
Micron
Table 3-1: DDR4 SDRAM Configuration
The hardware design of DDR4 requires strict consideration of
signal integrity. We have fully considered the matching resistor/terminal
resistance, trace impedance control, and trace length control in circuit
design and PCB design to ensure high-speed and stable operation of
DDR3.
Figure 3-1: The DDR4 DRAM Schematic