Alinx AX7050 User manual

Spartan-7 FPGA
Development Board
AX7050
User Manual

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Version Record
Version
Date
Release By
Description
Rev 1.0
2019-04-25
Rachel Zhou
First Release

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Table of Contents
Version Record.......................................................................................... 2
Part 1: FPGA Development Board Introduction......................................... 6
Part 2: AC7050 core board...................................................................... 10
Part 2.1: AC7050 Core Board Introduction........................................10
Part 2.2: FPGA Chip..........................................................................12
Part 2.3: Active Differential Crystal....................................................13
Part 2.4: DDR3 DRAM ......................................................................15
Part 2.5: QSPI Flash .........................................................................19
Part 2.6: LED Light on Core Board....................................................20
Part 2.7: JTAG Interface....................................................................21
Part 2.8: Power Interface on the Core Board ....................................22
Part 2.9: Board to Board Connectors pin assignment .......................23
Part 2.10: Power Supply....................................................................27
Part 2.12: Structure Diagram.............................................................30
Part 3: Carrier Board ............................................................................... 32
Part 3.1: Carrier Board Introduction ..................................................32
Part 3.2: Gigabit Ethernet Interface...................................................33
Part 3.3: HDMI Output Interface........................................................35
Part 3.4: USB2.0 Interface ................................................................37
Part 3.5: SD Card Slot.......................................................................39
Part 3.6: USB to Serial Port...............................................................40
Part 3.7: EEPROM 24LC04...............................................................42
Part 3.8 : Real time clock DS1302 ....................................................43
Part 3.9: Expansion Header ..............................................................44
Part 3.10: JTAG Interface..................................................................46
Part 3.11: Camera Module Interface .................................................47
Part 3.12: Buttons..............................................................................48

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Part 3.13: LED Light..........................................................................49
Part 3.14: Power Supply....................................................................50
Part 3.15: Structure Diagram.............................................................52

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This Spartan7 FPGA development platform adopts the core board +
Carrier Board mode, which is convenient for users to use the core board for
secondary development.
In the design of Carrier Board, we have extended a wealth of interfaces for
users, such as Gigabit Ethernet interfaces, HDMI Output interface, USB2.0
communication interface, SD card slot, RTC circuit etc. It meets user's
requirements for high-speed data exchange, video transmission processing
and industrial control. It is a "Versatile" Spartan7 FPGA development platform.
It provides the possibility for high-speed video transmission, pre-validation and
post-application of network and USB communication and data processing. This
product is very suitable for students, engineers and other groups engaged in
ARTIX-7FPGA development.

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Part 1: FPGA Development Board Introduction
The entire structure of the AX7050 FPGA development board is inherited
from our consistent core board + Carrier Board model. A high-speed
inter-board connector is used between the core board and the Carrier Board.
The core board is mainly composed of FPGA + DDR3 + QSPI FLASH,
which undertakes the functions of high-speed data processing and storage of
FPGA, high-speed data reading and writing between FPGA and two DDR3s,
data bit width is 32 bits, and the bandwidth of the whole system is up to 10Gb.
/s(333.3M*32bit); The two DDR3 capacities are up to 8Gbit, which meets the
need for high buffers during data processing. The selected FPGA is the
XC7S50FGGA484 chip of XILINX's Spartan7 series, in FGGA484 package.
The AX7050 Carrier Board expands its rich peripheral interface, including
1 Gigabit Ethernet interface, 1 HDMI Output interface, 1 USB2.0 interface, 1
UART serial interface, 1 SD card slot, 1 JTAG debug interface, 1 camera
interface, 1-way 40-pin expansion header, RTC circuit and EEPROM.

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LED*4
摄像头
接口
HDMI输出
按键*4 SD Card
JTAG
XILINX
Spartan 7
FPGA
50Mhz
DDR3
QSPI
FLASH
核心板
40针IO扩展口
RTL8211
EG
以太网
网口
USB
UART
CP2102
USB 2.0
FT232HL
DDR3
Figure 1-1-1: The Schematic Diagram of the AX7050
Through this diagram, you can see the interfaces and functions that the
AX7050 FPGA Development Board contains:
AC7050 FPGA core board
The core board consists of XC7S50 + 2 pieces of 4Gb DDR3 + 128Mb
QSPI FLASH. In addition, there is a high precision 50Mhz crystal on the
board to provide a stable clock input for the FPGA system.
1-channel 10/100M/1000M Gigabit Ethernet Interface RJ-45 interface
The Gigabit Ethernet interface chip uses Realtek's RTL8211EG
Ethernet PHY chip to provide network communication services to users.
RTL8211EG chip supports 10/100/1000 Mbps network transmission

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rate. Full duplex and adaptive
1-channel HDMI Output
Use the FPGA's four LVDS differential signals (3-way data plus 1 clock)
interface to directly drive the HDMI output, providing different formats of
video output interfaces for the FPGA development board
1-channel USB2.0 Interface
Use FTDI Chip's FT232H single-channel USB chip for USB2.0
high-speed communication between development board and PC, up to
480Mb/s
1-channel Uart to USB interface
1 Uart to USB interface for communication with the computer for user
debugging. The serial port chip is the USB-UAR chip of Silicon Labs
CP2102GM, and the USB interface is the MINI USB interface.
Micro SD card slot
1-port Micro SD card holder, support SPI mode
EEPROM
Onboard an IIC interface EEPROM 24LC04
RTC real time clock
Onboard RTC real time clock with battery holder, battery model
CR1220
2-way 40-pin expansion port
2-way 40-pin 0.1inch spacing expansion port can be connected to
various ALINX modules (binocular camera, TFT LCD screen,
high-speed AD module, etc.). The expansion port contains 1 channel
5V power supply, 2 channel 3.3V power supply, 3 way ground, 34 IOs
port.
CMOS Interface
The 18-pin camera interface that can be connected to 5 million OV5640
camera module of ALINX

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JTAG Interface
The 10-pin 0.1 spacing standard JTAG ports for FPGA program
download and debugging.
Button
4 buttons; 1 reset button (on the core board)
LED Light
5 user LEDs (1 on the core board and 4 on the Carrier Board)

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Part 2: AC7050 core board
Part 2.1: AC7050 Core Board Introduction
AC7050 (core board model, the same below) FPGA core board, it is based
on XILINX's Spartan 7 series XC7S50FGGA484. It is a high-performance core
board with high speed, high bandwidth and high capacity. It is suitable for
high-speed data communication, video image processing, high-speed data
acquisition, etc.
This AC7050 core board uses two pieces of MICRON's
MT41J256M16HA-125 DDR3 chip, each DDR has a capacity of 4Gbit; two
DDR chips are combined into a 32-bit data bus width, data clock frequency up
to 333.3Mhz, such a configuration can meet the needs of high bandwidth data
processing. The model of the 128Mb QSPI FLASH chip on the board is
N25Q128, which is used to store the boot image file of the FPGA system
The AC7050 core board expands 114 standard IO ports of 3.3V level, of
which 65 IOs can change the level standard by modifying the LDO chip on the
core board. For users who need a lot of IO, this core board will be a good
choice. Moreover, the routing between the FPGA chip and the interface is equal
length and differential processing, and the core board size is only 45*55 (mm),
which is very suitable for secondary development.

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Figure 2-1-1: AC7050 Core Board (Front View)
Figure 2-1-2: AC7050 Core Board (Rear View)

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Part 2.2: FPGA Chip
As mentioned above, the FPGA model we use is XC7S50FGGA484,
which belongs to Xilinx's Spartan7 series. The speed grade is 1, and the
temperature grade is commercial grade. This model is a FGGA484 package
with 484 pins. Xilinx Spartan7 FPGA chip naming rules as below
Figure 2-2-1: The Specific Chip Model Definition of Spartan7 Series
Figure 2-2-2: FPGA chip on board

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The main parameters of the FPGA chip XC7S50 are as follows
FPGA power supply system
XILINX Spartan7 FPGA power supplies are VCCINT, VCCBRAM, VCCAUX, VCCIO.
VCCINT is the FPGA core power supply pin, which needs to be connected to 1.0V;
VCCBRAM is the power supply pin of FPGA block RAM, connect to 1.0V; VCCAUX is
FPGA auxiliary power supply pin, connect 1.8V; VCCO is the voltage of each
BANK of FPGA, including BANK0, BANK14, BANK15~16, BANK34~35. On
AC7050 FPGA core board, BANK34 and BANK35 need to be connected to
DDR3, the voltage connection of BANK is 1.5V, and the voltage of other BANK
is 3.3V. The VCCO of BANK15 and BANK16 is powered by the LDO, and can
be changed by replacing the LDO chip.
Part 2.3: Active Differential Crystal
The AC7050 core board is equipped with a 50Mhz active differential
crystal for the system's main clock of the FPGA. The crystal output is
connected to the clock input pin of the FPGA (IO_L13P_T2_MRCC_14, Pin
P15). This clock can be used to drive the user logic in the FPGA. Users can
configure the FPGA's internal PLLs to achieve a higher clock.

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Figure 2-3-1: 50Mhz Active Crystal Oscillator
Figure 2-3-2: 50Mhz Active Crystal Oscillator on the Core Board
Clock Pin Assignment
Signal Name
FPGA PIN
CLK_50MHZ
P15
In addition, an active differential crystal is reserved on the AC7050 core
board. The default is not installed. The differential crystal output is connected to
the BANK34 global clock pin MRCC (AA6 and AB6) of the FPGA. Users can
install their own clocks of different frequencies as needed.
Figure 2-3-3: Reserved Active Differential Crystal

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Reserved Differential Clock Pin Assignment
Signal Name
FPGA PIN
SYS_CLK_P
AA6
SYS_CLK_N
AB6
Part 2.4: DDR3 DRAM
The FPGA core board AC7050 is equipped with two Micron 4Gbit (512MB)
DDR3 chips, model is MT41J256M16HA-125 (compatible with
MT41K256M16HA-125). DDR bus width is a total of 32bit. The DDR3 SDRAM
has a maximum operating speed of 333.3MHz (data rate 667Mbps). The DDR3
memory system is directly connected to the memory interface of the BANK 34
and BANK35 of the FPGA. The specific configuration of DDR3 SDRAM is
shown in Table 2-4-1.
Bit Number
Chip Model
Capacity
Factory
U5,U6
MT41J256M16HA-125
256M x 16bit
Micron
Table 2-4-1: DDR3 SDRAM Configuration
The hardware design of DDR3 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR3.

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FPGA
DDR3
(MT41J256M16
HA)
Data[31:16]
U5
U1
BANK
34/35
DDR3
(MT41J256M16
HA)
U6
Data[15:0]
Addr/control
Figure 2-4-1: The DDR3 DRAM Schematic
Figure 2-4-2: The DDR3 on the Core Board

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DDR3 DRAM pin assignment:
Net Name
FPGA PIN Name
FPGA P/N
DDR3_DQS0_P
IO_L2N_T0_AD12N_35
J2
DDR3_DQS0_N
IO_L3P_T0_DQS_AD5P_35
J1
DDR3_DQS1_P
IO_L9P_T1_DQS_AD7P_35
L5
DDR3_DQS1_N
IO_L9N_T1_DQS_AD7N_35
K5
DDR3_DQS2_P
IO_L15P_T2_DQS_35
M2
DDR3_DQS2_N
IO_L15N_T2_DQS_35
M1
DDR3_DQS3_P
IO_L21P_T3_DQS_35
P6
DDR3_DQS3_N
IO_L21N_T3_DQS_35
N6
DDR3_DQ[0]
IO_L1N_T0_AD4N_35
H2
DDR3_DQ [1]
IO_L4N_T0_35
K2
DDR3_DQ [2]
IO_L2N_T0_AD12N_35
H3
DDR3_DQ [3]
IO_L5P_T0_AD13P_35
H6
DDR3_DQ [4]
IO_L5N_T0_AD13N_35
H5
DDR3_DQ [5]
IO_L6P_T0_35
K6
DDR3_DQ [6]
IO_L2P_T0_AD12P_35
H4
DDR3_DQ [7]
IO_L1P_T0_AD4P_35
J3
DDR3_DQ [8]
IO_L12P_T1_MRCC_35
M8
DDR3_DQ [9]
IO_L11P_T1_SRCC_35
L8
DDR3_DQ [10]
IO_L8N_T1_AD14N_35
L6
DDR3_DQ [11]
IO_L7P_T1_AD6P_35
J8
DDR3_DQ [12]
IO_L10N_T1_AD15N_35
K4
DDR3_DQ [13]
IO_L11N_T1_SRCC_35
K8
DDR3_DQ [14]
IO_L10P_T1_AD15P_35
L4
DDR3_DQ [15]
IO_L7N_T1_AD6N_35
J7
DDR3_DQ [16]
IO_L14P_T2_SRCC_35
L1
DDR3_DQ [17]
IO_L18P_T2_35
P3
DDR3_DQ [18]
IO_L14N_T2_SRCC_35
K1
DDR3_DQ [19]
IO_L16P_T2_35
N4
DDR3_DQ [20]
IO_L17N_T2_35
N1
DDR3_DQ [21]
IO_L17P_T2_35
P1
DDR3_DQ [22]
IO_L13N_T2_MRCC_35
M3
DDR3_DQ [23]
IO_L16N_T2_35
N3
DDR3_DQ [24]
IO_L24N_T3_35
R4

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DDR3_DQ [25]
IO_L23N_T3_35
R6
DDR3_DQ [26]
IO_L22P_T3_35
P7
DDR3_DQ [27]
IO_L20P_T3_35
N5
DDR3_DQ [28]
IO_L23P_T3_35
R7
DDR3_DQ [29]
IO_L22N_T3_35
N7
DDR3_DQ [30]
IO_L19P_T3_35
P8
DDR3_DQ [31]
IO_L24P_T3_35
R5
DDR3_DM0
IO_L4P_T0_35
K3
DDR3_DM1
IO_L8P_T1_AD14P_35
L7
DDR3_DM2
IO_L13P_T2_MRCC_35
M4
DDR3_DM3
IO_L20N_T3_35
M5
DDR3_A[0]
IO_L10N_T1_34
Y3
DDR3_A[1]
IO_L11N_T1_SRCC_34
U3
DDR3_A[2]
IO_L4P_T0_34
T5
DDR3_A[3]
IO_L2P_T0_34
T7
DDR3_A[4]
IO_L1P_T0_34
W5
DDR3_A[5]
IO_L2N_T0_34
T6
DDR3_A[6]
IO_L7N_T1_34
W1
DDR3_A[7]
IO_L4N_T0_34
U5
DDR3_A[8]
IO_L1N_T0_34
W4
DDR3_A[9]
IO_L14P_T2_SRCC_34
Y6
DDR3_A[10]
IO_L14N_T2_SRCC_34
Y5
DDR3_A[11]
IO_L8P_T1_34
W2
DDR3_A[12]
I O_L9N_T1_DQS_34
U1
DDR3_A[13]
IO_L11P_T1_SRCC_34
U4
DDR3_A[14]
IO_L15P_T2_DQS_34
Y4
DDR3_BA[0]
IO_L8N_T1_34
Y1
DDR3_BA[1]
IO_L9P_T1_DQS_34
U2
DDR3_BA[2]
IO_L10P_T1_34
W3
DDR3_S0
IO_L7P_T1_34
V1
DDR3_RAS
IO_L5P_T0_34
V7
DDR3_CAS
IO_L6P_T0_34
T8
DDR3_WE
IO_L6N_T0_VREF_34
U8
DDR3_ODT
IO_L5N_T0_34
V6
DDR3_RESET
IO_L17N_T2_34
AA1
DDR3_CLK_P
IO_L12P_T1_MRCC_34
T3

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DDR3_CLK_N
IO_L12N_T1_MRCC_34
T2
DDR3_CKE
IO_L3N_T0_DQS_34
V4
Part 2.5: QSPI Flash
The FPGA core board AC7050 is equipped with one 128MBit QSPI
FLASH, and the model is N25Q128, which uses the 3.3V CMOS voltage
standard. Due to the non-volatile nature of QSPI FLASH, it can be used as a
boot device for the system to store the boot image of the system. These
images mainly include FPGA bit files, ARM application code, core application
code and other user data files. The specific models and related parameters of
QSPI FLASH are shown in Table 2-5-1.
Position
Model
Capacity
Factory
U8
N25Q128
128M Bit
Numonyx
Table 2-5-1: QSPI FLASH Specification
QSPI FLASH is connected to the dedicated pins of BANK0 and BANK14 of
the FPGA chip. The clock pin is connected to CCLK0 of BANK0, and other data
and chip select signals are connected to D00~D03 and FCS pins of BANK14
respectively. Figure 2-5-1 shows the hardware connection of QSPI Flash.
Figure 2-5-1: QSPI Flash Schematic

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QSPI Flash pin assignments:
Net Name
FPGA PIN Name
FPGA P/N
QSPI_CLK
CCLK_0
D9
QSPI_CS
IO_L6P_T0_FCS_B_14
N17
QSPI_DQ0
IO_L1P_T0_D00_MOSI_14
M21
QSPI_DQ1
IO_L1N_T0_D01_DIN_14
M22
QSPI_DQ2
IO_L2P_T0_D02_14
N21
QSPI_DQ3
IO_L2N_T0_D03_14
N22
Figure 2-5-1: QSPI on the Core Board
Part 2.6: LED Light on Core Board
There are 3 red LED lights on the AC7050 FPGA core board, one of which
is the power indicator light (PWR), one is the configuration LED light (DONE),
and one is the user LED light. When the core board is powered, the power
indicator will illuminate; when the FPGA is configured, the configuration LED
will illuminate. The user LED light is connected to the IO of the BANK16, the
user can control the light on and off by the program. When the IO voltage
connected to the user LED is high, the user LED is off. When the connection IO
voltage is low, the user LED will be lit. The schematic diagram of the LED light
hardware connection is shown in Figure 2-6-1: