Alinx AX516 User manual

Spartan-6 FPGA
Development Board
AX516
User Manual

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Spartan-6 FPGA Development Board AX516 User Manual
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Version Record
Version
Date
Release By
Description
Rev 1.0
2019-04-28
Rachel Zhou
First Release

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Table of Contents
Part 1: FPGA Development Board Introduction.......................................... 4
Part 2: Structure Diagram........................................................................... 7
Part 3: Power.............................................................................................. 8
Part 4: FPGA Chip.................................................................................... 10
Part 4.1: JTAG Interface.................................................11
Part 4.2: FPGA Power Supply........................................12
Part 5: 50Mhz Clock ................................................................................. 14
Part 6: QSPI Flash.................................................................................... 15
Part 7: DDR3 DRAM................................................................................. 16
Part 8: EEPROM 24LC04......................................................................... 19
Part 9: Real time clock DS1302................................................................ 20
Part 10: Gigabit Ethernet Interface........................................................... 22
Part 11: USB to Serial Port....................................................................... 25
Part 12: VGA Port..................................................................................... 27
Part 13: USB 2.0....................................................................................... 29
Part 14: SD card slot ................................................................................ 32
Part 15: Expansion Header ...................................................................... 34
Part 16: LED............................................................................................. 36
Part 17: Buttons........................................................................................ 37
Part 18: Camera Module Interface ........................................................... 39
Part 19: PMOD interface (AX516 Reserved)............................................ 40
Part 20: SMA Interface ............................................................................. 42

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The AX516 FPGA development board uses the XILINX SPARTAN6 family
chips, model XC6SLX16-2CSG324. As a core processor, FPGA has rich
hardware resources and peripheral interfaces. In the design, adhere to the
"exquisite, practical, simple" design concept, it is very suitable for software radio,
industrial control, multimedia applications, IC verification, parallel computing
and other project development, and it can also be applied to college teaching,
FPGA training, personal research learning and DIY, etc.
The Photograph of FPGA Board
Part 1: FPGA Development Board Introduction
The FPGA chipset is Xilinx Spartan-6 XC6SLX16 device in FBGA324
package, the feature summary of this FPGA device are listed below:

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Table 1-1: The Feature Summary of FPGA Device
The main resources and features are listed (see Table 1-2):
Parameter
Value
Logic Cells
14579
DSP48 Slices （18 x 18 multiplier, an adder, and
accumulator）
32
Configurable Logic Blocks(CLBs)
136Kb
Block RAM Blocks
576Kb
CMTs
2
MAX User I/O
218
Core Power Supply
1.15V-1.25V (recommended 1.2V)
Operation Temperature
0-85℃
Table 1-2: The Main Resources and Feature of Xilinx Spartan6 XC6SLX9
The layout of the board that indicates the location of the connector and key
components, provide a quickly overview of AX516 board (see Figure 1-2)

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FPGA
XC6SLX16
128MByte
DDR3
50M
晶振 EEPROM
24LC04
实时时钟
128Mbit
FLASH
千兆以太网
芯片
USB2.0
芯片
USB转
串口
按键1按键2按键3按键4Micro
SD卡座
配置键 复位键
千兆
网口
65535色
VGA接口
摄像头
接口
40针扩展口（34个IO口，1路5V，2路3.3V，3路GND
USB
接口
串口
接口
+5V电源
接口
电源
开关
JTAG口
PMOD接口
3.3V电源
1.2V电源
1.5V电源
DDR电源
SMA
时钟
4个用户LED灯
2个配置指示灯
电源
指示灯 2.5V IO
电源
Figure 2-1: The Layout of the AX516 board
Through this diagram, we can see the functions that the development
platform can achieve.
+5V power input, maximum 2A current protection
A large 128Mbyte high-speed DD3 SDRAM can be used as a buffer for
data or as a memory for Microblaze
A 128Mbit QSPI FLASH that can be used as a storage for FPGA
configuration files and user data
One-way 10/100M/1000M Ethernet RJ-45 interface for Ethernet data
exchange with computers or other network devices;
One-way high-speed USB2.0 interface, can be used for USB2.0
high-speed communication between FPGA development board and PC
One USB Uart interface for serial communication with PC or external

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devices
A camera module interface that can connect 5 million OV5640 camera
One-port VGA interface, VGA interface is 16bit, can display 65,536
colors, can display color pictures, etc
A piece of RTC real time clock with battery holder, battery model CR1220
One piece of IIC interface EEPROM 24LC04
4 red user LEDs
4 independent user buttons
On-board 50M active crystal oscillator provides stable clock source for
FPGA development board
1-Way 40-pin ALINX expansion port (0.1”inch), 34 IO ports, one 5V
power supply, two 3.3V power supplies, three GND. Two expansion
modules can be connected at the same time, such as expansion
modules such as 4.3-inch TFT module and AD/DA module.
Reserved JTAG port for FPGA debugging and program curing
One way Micro SD card holder, support SD mode and SPI mode
Reserve a 2.5V power supply, optional IO voltage 3.3V and 2.5V for
FPGA
One SMA interface for input or output of an external clock
Part 2: Structure Diagram
The size of the development board is a compact 130mm x 90mm, and the
PCB is designed with an 8-layer board. There are 4 screw positioning holes
around the FPGA board for fixing the development board. The hole diameter of
the positioning hole is 3.3mm (diameter)

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Figure 2-1: Structure Diagram
Part 3: Power
The FPGA development board power supply input voltage is DC5V. The
power supply design diagram on the development board is as Figure 3-1:
5V 电源
输入
保险丝
MP1482
MP1482
TPS51200
3.3V/2A
1.2V/2A
VTT
VREF
MP1482
电源开关
1.5V/2A
CN1
F1
SW1
U15
U16
U17
U32
LT1117 2.5V/0.8A
Figure 3-1: Block Diagram of Power Design

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The development board is powered by +5V, and is converted into +3.3V,
+1.2V, +1.5V three-way power supply through three-way DC/DC power supply
chip MP1482. It generates +2.5V power supply through one LDO LT1117, and
VTT and VREF voltages (1.5V) required for DDR3 is generated by TPS51200 of
TI. The functions of each power distribution are shown in the following table:
Power Supply
Function
+1.2V
FPGA Core Voltage
+3.3V
FPGA, Ethernet, Serial port, RTC, FLASH, EEPROM, USB 2.0 and SD Card
+1.5V
DDR3, Bank3 of FPGA
VREF,VTT
DDR3
+2.5V
FPGA Bank2 optional
The IO voltage of FPGA BANK2 can be selected by two 0 ohm resistors
(R158, R159) on the board. When R158 is installed and R159 is not installed,
the IO level of Bank2 is 3.3V. When R158 is not installed and R159 is installed.
the IO level of Bank2 is 2.5V
FPGA BANK voltage distribution detailed as table 3-1:
XC6SLX16-
2CSG324
Bank0
Bank2
Bank1
Bank3
BANK
Function
Voltage
Description
BANK0
VGA, USB2.0, PMOD, UART
3.3V
BANK1
SD Card, Camera, Ethernet, VGA
3.3V
BANK2
Extend IO，QSPI FLASH, LED, KEY
3.3V/2.5V
BANK3
DDR3, Reset Button
1.5V
Table 3-1: FPGA BANK voltage distribution

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When designing the PCB, we used a 6-layer PCB and reserved a separate
Power layer and GND layer, which ensures the FPGA development board has
very good stability. On the PCB we have reserved test points for each power
supply so that the user can confirm the voltage on the board.
Figure 3-2: The Test Point of Power Voltage
Part 4: FPGA Chip
As mentioned earlier, the FPGA model we use is XC6SLX16-2CSG324,
which belongs to Xilinx Spartan-6. This model is a BGA package with 324 pins.
Again, explain the definition of the FPGA pin. Many people use FPGAs that are
not BGA-packaged, such as 144-pin, 208-pin FPGA chips. Their pin definitions
are made up of numbers, such as 1 to 144, 1 to 208, etc., and when we use
BGA packages. After the chip, the pin name becomes in the form of letters +
numbers, such as E3, G3, etc., so when we look at the schematic, we see the
letters + numbers, which represent the pins of the FPGA. Having said this, let's
look at the functions of the various parts of the FPGA.

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Figure 4-1: FPGA Chipset
Part 4.1: JTAG Interface
First, let's talk about the FPGA configuration and debug interface: the JTAG
interface. The function of the JTAG interface is to download the compiled
program (.bit) to the FPGA or download the FLASH configuration program (.mcs)
to the SPI FLASH. After the Bit file is downloaded to the FPGA, it will be lost
after power-off. It needs to be powered on and downloaded again. However,
after downloading the MCS file to FLASH, it will not be lost after power-off. After
power-on, the FPGA will read the configuration file in FLASH and run it.
The hardware design of JTAG connector is showed as Figure 4-2, JTAG
interface includes four signals (TCK,TDO,TMS,TDI). these four signals
connects between FPGA device and JTAG connector with 33ohm resistors, the
33ohm resistors will protect FPGA device to avoid damage。

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Figure 4-2: Hardware Design of JTAG Connector
JTAG connector is 14pin connectors, the pin pitch is 2.0mm.
Figure 4-3: Onboard JTAG Connector
Part 4.2: FPGA Power Supply
Next, let's talk about the power supply pin part of the FPGA, including the
power supply pin of each bank, the core voltage pin and the auxiliary voltage pin.

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VCCINT is the FPGA core power supply pin, connected to 1.2V; VCCAUX is the
FPGA auxiliary power supply pin, can be connected to 3.3V or 2.5V, here
connected to 3.3V; VCCINT and VCCAUX connection as shown in Figure 3-4
Figure 4-4: FPGA Power Supply
VCCIO is the supply voltage of each BANK of the FPGA. VCCIO0 is the
power supply pin of BANK0 of FPGA. Similarly, VCCIO1~VCCIO3 are the
power supply pins of BANK~BANK3 of FPGA respectively. In the FPGA
development board, VCCIO0 and VCCIO1 are connected to 3.3V, which means
that the corresponding FPGA pins are 3.3V input and output. VCCIO2 is also
connected to 3.3V by default, but the user can select 2.5V by changing the
resistance (R158 is not installed, R159 is installed). Because the pin of BANK3
is connected to a DDR3, VCCIO3 is connected to 1.5V. Figure 3.5 shows the
connection diagram of VCCIO of BANK2. Figure 3-5 is a connection diagram of
VCCIO of BANK2.

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Figure 4-5: FPGA power supply VCCIO pin
Part 5: 50Mhz Clock
Figure 5-1 is the clock circuit of the FPGA development board, an 50Mhz
crystal oscillator provides the clock source for the whole board. The output of
the crystal oscillator is connected to the FPGA global clock (GCLK Pin V10).
This GCLK can be used to drive the user's logic circuit inside the FPGA. Users
can configure the internal PLLs and DCMs of FPGA to achieve higher clocks.
Figure 5-1: 50Mhz Crystal Oscillator

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Figure 5-2: 50Mhz crystal oscillator onboard
Net Name
FPGA PIN
FPGA_GCLK
V10
Table 5-1: Clock Pin Assignment
Part 6: QSPI Flash
The AX516 FPGA development board is equipped with one 128MBit QSPI
FLASH, and the model is W25Q128 which uses the 3.3V CMOS voltage
standard. Due to the non-volatile nature of QSPI FLASH, it can be used as a
boot device for the system to store the boot image of the system. These images
mainly include FPGA bit files, ARM application code, core application code and
other user data files. The specific models and related parameters of QSPI
FLASH are shown in Table 6-1.
Position
Model
Capacity
Factory
U6
N25Q256BV
32M Bit
Winbond
Table 6-1: QSPI FLASH Specification

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Figure 6-1: QSPI Flash Schematic
QSPI Flash pin assignments:
Pin Name
FPGA Pin
QSPI_CLK
R15
QSPI_CS
V3
QSPI_MISO0
T13
QSPI_MISO1
R13
QSPI_MISO2
T14
QSPI_MISO3
V14
Part 7: DDR3 DRAM
The AX516 FPGA development board is equipped with one high speed
DDR3 DRAM, Model：MT41J64M16LA-187E, Capacity 128MByte (64M*16bit);
16bit bus. The FPGA and DDR3 DRAM on the development board are
connected to the IO of BANK3. The Spartan6 FPGA has a hard DDR3 controller
MCB inside. The configuration can make the MCB and DDR3 read and write
speeds reach 666Mb/s. The hardware design of DDR3 requires strict
consideration of signal integrity. We have fully considered the matching
resistor/terminal resistance, trace impedance control, and trace length control in
circuit design and PCB design to ensure high-speed and stable operation of

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DDR3.
Figure 7-1 detailed the DDR3 DRAM hardware connection
Figure 7-1: DDR3 DRAM Hardware Connection
Figure 7-2: DDR3 DRAM on the FPGA Board

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DDR3 DRAM Pin Assignment：
Pin Name
FPGA Pin
DDR3_LDQS_P
L4
DDR3_LDQS_N
L3
DDR3_UDQS_P
P2
DDR3_UDQS_N
P1
DDR3_DQ[0]
L2
DDR3_DQ [1]
L1
DDR3_DQ [2]
K2
DDR3_DQ [3]
K1
DDR3_DQ [4]
H2
DDR3_DQ [5]
H1
DDR3_DQ [6]
J3
DDR3_DQ [7]
J1
DDR3_DQ [8]
M3
DDR3_DQ [9]
M1
DDR3_DQ [10]
N2
DDR3_DQ [11]
N1
DDR3_DQ [12]
T2
DDR3_DQ [13]
T1
DDR3_DQ [14]
U2
DDR3_DQ [15]
U1
DDR3_LDM
K3
DDR3_UDM
K4
DDR3_A[0]
J7
DDR3_A [1]
J6
DDR3_A [2]
H5
DDR3_A [3]
L7
DDR3_A [4]
F3
DDR3_A [5]
H4
DDR3_A [6]
H3
DDR3_A [7]
H6
DDR3_A [8]
D2

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DDR3_A [9]
D1
DDR3_A [10]
F4
DDR3_A [11]
D3
DDR3_A [12]
G6
DDR3_A [13]
F6
DDR3_BA [0]
F2
DDR3_BA [1]
F1
DDR3_BA [2]
E1
DDR3_RAS_N
L5
DDR3_CAS_N
K5
DDR3_WE_N
E3
DDR3_ODT
K6
DDR3_RESET_N
E4
DDR3_CLK_P
G3
DDR3_CLK_N
G1
DDR3_CKE
H7
Part 8: EEPROM 24LC04
The development board contains an EEPROM, model 24LC04, and its
capacity is 4Kbit (2*256*8bit). It consists of two 256-byte blocks and
communicates via the IIC bus. The onboard EEPROM is to learn the
communication method of the IIC bus. EEPROM is generally used in the design
of instruments and meters, Used as a storage for some parameters, power-off is
not lost. This chip is simple to operate and has a very high cost performance, so
although the capacity ratio is high, the price is very cheap, which is a good
choice for those products that are costly. Figure 8-1 detailed the EEPROM
24LC04 schematic:

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Figure 8-1: EEPROM Design
Figure 8-2 shows the EEPROM on AX516 board：
Figure 8-2: EEPROM on AX516 board
Table 8-1 detailed the EEPROM PIN assignment
Net Name
FPGA PIN
SDA
N5
SCL
P6
Table 8-1: EEPROM PIN Assignment
Part 9: Real time clock DS1302
The FPGA development board contains a real-time clock RTC chip, model
DS1302. Its function is to provide the calendar function to 2099, with days,
minutes, minutes, seconds and weeks. If time is required in the system, the
RTC needs to be designed into the product. it need to connect a 32.768KHz