Alinx AX7021 User manual

ZYNQ7000 FPGA
Development Board
AX7021
User Manual

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Version Record
Version
Date
Release By
Description
Rev 1.0
2019-03-27
Rachel Zhou
First Release
Rev 1.1
2020-09-21
Rachel Zhou
Correct the corresponding pins of B34_L15_N/P.

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Table of Contents
Version Record............................................................................................................... 2
Part 1: FPGA Development Board Introduction..................................................... 6
Part 2: AC7021 Core Board....................................................................................... 8
2.1 Introduction........................................................................................................ 8
2.2 ZYQN Chip...................................................................................................... 10
2.3 DDR3 DRAM...................................................................................................13
2.4 QSPI Flash...................................................................................................... 16
2.5 eMMC Flash.................................................................................................... 17
2.6 Clock configuration.........................................................................................19
2.7 USB to serial port........................................................................................... 20
2.8 LED................................................................................................................... 22
2.9 Reset button.................................................................................................... 23
2.10 JTAGE Interface...........................................................................................24
2.11 DIP switch configuration............................................................................. 25
2.12 Power............................................................................................................. 25
2.13 Structure diagram.........................................................................................28
2.14 Connector pin definition.............................................................................. 28
Part 3: Carrier Board................................................................................................. 35
3.1 Introduction......................................................................................................35
3.2 Gigabit Ethernet interface............................................................................. 36
3.3 USB2.0 Host interface...................................................................................40
3.4 HDMI Output Interface...................................................................................42
3.5 USB to serial port........................................................................................... 44
3.6 SD card slot..................................................................................................... 45
3.7 JTAG Interface................................................................................................46
3.8 LED................................................................................................................... 47
3.9 User Button......................................................................................................48
3.10 Extension Port.............................................................................................. 49

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3.11 Power Supply................................................................................................52
3.12 Carrier Board Structure diagram............................................................... 54

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This ZYNQ7000 FPGA development platform adopts the core board +
carrier board mode, which is convenient for users to use the core board for
secondary development. The core board uses XILINX's Zynq7000 SOC chip
solution, which combines dual-core ARM Cortex-A9 and FPGA programmable
logic on a single chip using ARM+FPGA SOC technology. In addition, the core
board contains 2 pieces of 1GB high-speed DDR3 SDRAM chip, 1 piece 32GB
eMMC memory chip and 1 piece 256Mb QSPI FLASH chip.
In the design of the carrier board, the user has extended a wealth of
peripheral interfaces, such as 5-port Gigabit Ethernet interfaces, 4-port USB2.0
HOST interfaces, 1-port HDMI output interface, Uart serial port communication
interface, SD card holder, 40-pin carrier header, etc. It meets the requirements
of users for various Ethernet high-speed data exchange, data storage, video
transmission processing and industrial control. It is a "professional" ZYNQ
development platform. For high-speed Ethernet data transmission and
exchange, the pre-validation and post-application of data processing is possible.
This product is very suitable for students, engineers and other groups engaged
in ZYNQ development.

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Part 1: FPGA Development Board Introduction
Here, a brief introduction to the AX7021 ZYNQ FPGA development
platform.
The entire structure of the development board, the core board + carrier
board mode design. A high-speed inter-board connector is used between the
core board and the carrier board.
The core board is mainly composed of the minimum system of ZYNQ7020
+ 2 DDR3 + eMMC + QSPI FLASH. It undertakes the high-speed data
processing and storage function of the ZYNQ system. The data width between
the ZYNQ7020 and the two DDR3s is 32 bits, and the two DDR3 capacities up
to 1GB. The 32GB eMMC FLASH memory chip and 256Mb QSPI FLASH are
used to statically store the ZYNQ operating system, file system and user data.
Users can select different startup modes through the DIP switch on the core
board. The ZYNQ7020 uses Xilinx's Zynq7000 series of chips, model number
XC7Z020-2CLG484I. The ZYNQ7020 chip can be divided into processor
system part Processor System (PS) and programmable logic part
Programmable Logic (PL).
The carrier board expands the rich peripheral interface for the core board,
including 5 Gigabit Ethernet interfaces, 4-port USB2.0 HOST interfaces, 1-port
HDMI output interface, 1-port SD Card interface, 1-port UART USB serial port
interface, 1-port SD Card interface, 2-port 40-pin carrier headers and some
button LEDs.
Figure 1-1-1 is the block diagram of the FPGA development board AX7021:

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Figure 1-1-1: The block diagram of AX7021
The interfaces and features included in the development board.
ZYNQ7000 Core Board
It consists of XC7Z020+1GB DDR3+32GB eMMC FLASH + 256Mb QSPI
FLASH. In addition, two crystal oscillators provide clocks, one is 33.3333MHz
for PS system and the other is 50MHz for PL logic.
Gigabit Ethernet Interface
5 channels 10/100M/1000M Ethernet RJ45 interface for Ethernet data
exchange with computers or other network devices. The network interface chip
uses Micrel's KSZ9031 industrial grade GPHY chip, one Ethernet connection to
the PS end of the ZYNQ chip, and four Ethernet connections to the PL end of the
ZYNQ chip.
HDMI Output Display
One HDMI output interface uses SIL9134 HDMI encoding chip of Silion
Image Corporation, which supports up to 1080P@60Hz output and supports 3D
output.

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USB Interface
1 JTAG debug interface, using MINI USB interface, users can debug and
download ZYNQ system through USB cable and onboard JTAG circuit.
LED Light
9 LEDs, include 6 on the core board and 3 on the extension board. There
are 1 power indicator, 1 DONE configuration indicator, 2 user indicators and 2
serial port transceiver indicators on the core board. There are 1 power indicator
and 2 user indicators on the extension board.
Button
3 buttons, 1 reset button on the core board, and 2 user buttons on the
extension board.
Part 2: AC7021 Core Board
2.1 Introduction
The AC7021 (core board model, the same below) core board is an FPGA
development board based on the Zynq chip XC7Z020-2CLG484I of the XILINX
ZYNQ7000 series. The ZYNQ chip's PS system integrates two ARM CortexTM-
A9 processors, AMBA® interconnects, internal memory, external memory
interfaces and peripherals. The ZYNQ FPGA chip contains a wide range of
programmable logic cells, DSP and internal RAM.
The core board uses two SK Hynix DDR3 chips (H5TQ4G63AFR-PBI),
each with a 4Gbit DDR capacity; two DDR chips form a 32-bit data bus width,
and the read and write data clock frequency between ZYNQ FPGA and DDR3
is up to 533Mhz; such a configuration can meet the system's high bandwidth
data processing needs
In order to connect to the carrier board, the four board-to-board connectors
of the core board extend the USB interface of the PS side, the Gigabit Ethernet
interface, the SD card interface and other remaining MIO ports. As well as
almost all IO ports (198) of BANK13, BANK33, BAN34 and BANK35 on the PL
side, the level of IO of BANK33 and BANK34 can be modified by replacing the

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LDO chip on the core board to meet the requirements of users with different
level interfaces. For users who need a lot of IOs, this core board will be a good
choice. Moreover, the IOs connection part, the routing between the ZYNQ
FPGA chip and the interface is equal length and differential processing. The
core board size is only 2.36 inch* 2.36 inch, which is very suitable for
secondary development.
Figure 2-2-1: AC7021Core board Front View

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Figure 2-2-2:AC7021 core board rear view
2.2 ZYQN Chip
The development board uses Xilinx's Zynq7000 series chip, model
XC7Z020-2CLG484I. The chip's PS system integrates two ARM CortexTM-A9
processors, AMBA® interconnects, internal memory, external memory
interfaces and peripherals. These peripherals mainly include USB bus interface,
Ethernet interface, SD/SDIO interface, I2C bus interface, CAN bus interface,
UART interface, GPIO, etc. The PS can operate independently and start up at
power up or reset. Figure 2-2-3 detailed the Overall Block Diagram of the
ZYNQ7000 Chip.