Alinx Zynq UltraScale+MPSoC User manual

Zynq UltraScale+MPSoC
FPGA Development
Board
ACU19EG User Manual

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Content Modification Record
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Table of Contents
Version Record................................................................................................................. 2
Table of Contents.............................................................................................................................. 3
Part 1: FPGA Core Board Introduction....................................................................................4
Part 1.1 ZYNQ Chip................................................................................................................4
Part 1.2 DDR4 DRAM............................................................................................................ 6
Part 2.4: QSPI Flash..............................................................................................................14
Part 2.5: eMMC Flash..........................................................................................................16
Part 2.6: Clock configuration ........................................................................................... 17
Part 2.7: Power Supply....................................................................................................... 19
Part 2.8: ACU19EG Core Board Form Factors............................................................ 21

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Part 1: FPGA Core Board Introduction
ACU19EG (core board model name) FPGA core board, ZYNQ chipset is based on
XCZU19EG-2FFVC1760I of XILINX company Zynq UltraScale+ MPSoCs EG Family.
This core board uses 9 Micron DDR4 chips MT40A512M16GE, 5 pcs DDR4 is on
the PS side to form a 72-bit data bus bandwidth and 5GB capacity. 4 DDR4 chip is on
the PL side, which is a 64-bit data bus width and a capacity of 4GB. The high-test
speed of DDR4 SDRAM on the PS side and PL side is 1200MHz (data rate 2400Mbps).
In addition, two 512MBit QSPI FLASH and an 32GB eMMC FLASH chip are also
integrated on the core board.
Eight board-to-board connectors expand the IOs of USB2.0,Gigabit Ethernet, SD
card and other MIOs in PS side; also expand 4 pairs of PS MGT, 48 GTH/GTY
transceivers and almost all IO ports on the PL side (HP I/O:240，HD I/O：96). The core
board size is 80*80 (mm), which is very suitable for secondary development.
ACU19EG Front view of core board
Part 1.1 ZYNQ Chip
The development board uses a series of chips from Xilinx Company's Zynq

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UltraScale+MPSoCs EG series, with the model XCZU19EG-2FFVC1760I. The PS system
of the ZU19EG chip integrates four ARM Cortexs ™- A53 processor, with a speed of
up to 1.3Ghz, supporting Level 2 Cache; In addition, the ZU19EG also includes two
Cortex-R5 processors (with speeds up to 533Mhz).
The ZU19EG chip supports 32-bit or 64-bit DDR4, LPDDR4, DDR3, DDR3L, and
LPDDR3 storage chips, with rich high-speed interfaces on the PS side such as PCIE
Gen2, USB3.0, SATA 3.1, and DisplayPort; At the same time, it also supports interfaces
such as USB2.0, Gigabit Ethernet, SD/SDIO, I2C, CAN, UART, GPIO, etc. The PL terminal
contains rich programmable logic units, DSP, and internal RAM. The overall block
diagram of the ZU19EG chip is shown in Figures 2-2-1:
Figure 2-2-1 Overall Block Diagram of ZYNQ ZU19EG chip
The main parameters of the PS system part are as follows:
-ARM quad-core Cortex™-A53 processor, speed up to 1.3GHz, each CPU 32KB
level 1 instruction and data cache, 1MB level 2 cache, shared by 2 CPUs。
-ARM dual-core Cortex-R5 processor, speed up to 533MHz, each CPU 32KB
level 1 instruction and data cache, and 128K tightly coupled memory.

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-External Memory Interface, Support 32/64bit DDR4/3/3L、LPDDR4/3 interface.
-Static storage interface, Support NAND, 2xQuad-SPI FLASH.
-High speed connection interface, SupportPCIe Gen2 x4, 2xUSB3.0, Sata 3.1,
DisplayPort, 4x Tri-mode Gigabit Ethernet.
-Ordinary connection interface：2xUSB2.0, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x
I2C, 2x SPI, 4x 32b GPIO.
-Power management: Support division of four power sources Full/Low/PL/Battery
-Encryption algorithm: Support RSA, AES & SHA.
-System monitor: 10 bit 1Mbps AD sampling for temperature and voltage
detection.
The main parameters of the PL logic part are as follows：
- System Logic Cells：1143K；
- CLB flip-flops): 1045K；
- CLBLUTs : 523K；
- Block RAM：34.6Mb；
- Clock Management Unit(CMTs）: 11 pieces
- DSP Slices：1968 pieces
- GTH 16.3Gb/s Transceiver： 44 pieces
The speed level of XCZU19EG-2FFVC1760I chip is -2, industrial grade, and
packaged as FFVC1760.
Part 1.2 DDR4 DRAM
The ACU19EG core board is equipped with 9 Micron (Micron) 1GB DDR4 chips,
model MT40A1G16KD-062E, with 5 DDR4 chips mounted on the PS side, forming a 72
bit data bus bandwidth (supporting ECC), and each DDR chip has a capacity of 1GB.
Mount four DDR4 chips on the PL end to form a 64 bit data bus bandwidth, with each
DDR chip having a capacity of 1GB. The maximum operating speed of the DDR4
SDRAM on the PS side can reach 1200MHz (data rate 2400Mbps), and the four DDR4
storage systems are directly connected to the storage interface of the BANK504 on
the PS. The maximum operating speed of the DDR4 SDRAM on the PL side can reach
1200MHz (data rate 2400Mbps), and four DDR4 chips are connected to the
BANK69,70,71 interfaces of the FPGA. The specific configurations of DDR4 SDRAM on
the PS and PL ends are shown in Table 2-3-1.

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Position
Reference
Part number
Capacity
Factory
PS
U4,U5,U6,U7,U162
MT40A1G16KD-062E
1G x 16bit
Micron
PL
U18,U19,U20,U21
MT40A1G16KD-062E
1G x 16bit
Micron
Table 2-3-1: DDR4 SDRAM Configuration
The hardware design of DDR4 requires strict consideration of Signal integrity. We
have fully considered the matching resistance/terminal resistance, routing impedance
control, and routing equal length control in circuit design and PCB design to ensure
the high-speed and stable operation of DDR4.
The hardware connection method of DDR4 on the PS side is shown in Figure
2-3-1:
Figure 2-3-1: PS DDR4 DRAM block diagram
The block diagram of DDR4 SDRAM on the PL Side is shown in Figure 2-3-2:
Figure 2-3-2: PL DDR4 DRAM block diagram

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PS Side DDR4 DRAM pin assignment:
Signal name
Pin name
Pin number
PS_DDR4_DQS0_N
PS_DDR_DQS_N0_504
BA30
PS_DDR4_DQS0_P
PS_DDR_DQS_P0_504
AY30
PS_DDR4_DQS1_N
PS_DDR_DQS_N1_504
AY33
PS_DDR4_DQS1_P
PS_DDR_DQS_P1_504
AY32
PS_DDR4_DQS2_N
PS_DDR_DQS_N2_504
AT30
PS_DDR4_DQS2_P
PS_DDR_DQS_P2_504
AR30
PS_DDR4_DQS3_N
PS_DDR_DQS_N3_504
AT32
PS_DDR4_DQS3_P
PS_DDR_DQS_P3_504
AR32
PS_DDR4_DQS4_N
PS_DDR_DQS_N4_504
AR40
PS_DDR4_DQS4_P
PS_DDR_DQS_P4_504
AP40
PS_DDR4_DQS5_N
PS_DDR_DQS_N5_504
AK37
PS_DDR4_DQS5_P
PS_DDR_DQS_P5_504
AJ37
PS_DDR4_DQS6_N
PS_DDR_DQS_N6_504
AU41
PS_DDR4_DQS6_P
PS_DDR_DQS_P6_504
AU40
PS_DDR4_DQS7_N
PS_DDR_DQS_N7_504
AL41
PS_DDR4_DQS7_P
PS_DDR_DQS_P7_504
AL40
PS_DDR4_DQS8_N
PS_DDR_DQS_N8_504
AY40
PS_DDR4_DQS8_P
PS_DDR_DQS_P8_504
AY39
PS_DDR4_DQ0
PS_DDR_DQ0_504
AV29
PS_DDR4_DQ1
PS_DDR_DQ1_504
AW30
PS_DDR4_DQ2
PS_DDR_DQ2_504
AW29
PS_DDR4_DQ3
PS_DDR_DQ3_504
AW31
PS_DDR4_DQ4
PS_DDR_DQ4_504
BB31
PS_DDR4_DQ5
PS_DDR_DQ5_504
BB30
PS_DDR4_DQ6
PS_DDR_DQ6_504
BB29
PS_DDR4_DQ7
PS_DDR_DQ7_504
BA31
PS_DDR4_DQ8
PS_DDR_DQ8_504
BB33
PS_DDR4_DQ9
PS_DDR_DQ9_504
BA32
PS_DDR4_DQ10
PS_DDR_DQ10_504
BA33
PS_DDR4_DQ11
PS_DDR_DQ11_504
BB34
PS_DDR4_DQ12
PS_DDR_DQ12_504
AV31
PS_DDR4_DQ13
PS_DDR_DQ13_504
AW32
PS_DDR4_DQ14
PS_DDR_DQ14_504
AV32
PS_DDR4_DQ15
PS_DDR_DQ15_504
AV33

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PS_DDR4_DQ16
PS_DDR_DQ16_504
AN29
PS_DDR4_DQ17
PS_DDR_DQ17_504
AP29
PS_DDR4_DQ18
PS_DDR_DQ18_504
AP30
PS_DDR4_DQ19
PS_DDR_DQ19_504
AP31
PS_DDR4_DQ20
PS_DDR_DQ20_504
AT31
PS_DDR4_DQ21
PS_DDR_DQ21_504
AU30
PS_DDR4_DQ22
PS_DDR_DQ22_504
AU31
PS_DDR4_DQ23
PS_DDR_DQ23_504
AU29
PS_DDR4_DQ24
PS_DDR_DQ24_504
AV34
PS_DDR4_DQ25
PS_DDR_DQ25_504
AU33
PS_DDR4_DQ26
PS_DDR_DQ26_504
AT33
PS_DDR4_DQ27
PS_DDR_DQ27_504
AU34
PS_DDR4_DQ28
PS_DDR_DQ28_504
AN33
PS_DDR4_DQ29
PS_DDR_DQ29_504
AP32
PS_DDR4_DQ30
PS_DDR_DQ30_504
AN32
PS_DDR4_DQ31
PS_DDR_DQ31_504
AN31
PS_DDR4_DQ32
PS_DDR_DQ32_504
AN41
PS_DDR4_DQ33
PS_DDR_DQ33_504
AN42
PS_DDR4_DQ34
PS_DDR_DQ34_504
AP42
PS_DDR4_DQ35
PS_DDR_DQ35_504
AP41
PS_DDR4_DQ36
PS_DDR_DQ36_504
AN39
PS_DDR4_DQ37
PS_DDR_DQ37_504
AR38
PS_DDR4_DQ38
PS_DDR_DQ38_504
AP39
PS_DDR4_DQ39
PS_DDR_DQ39_504
AN38
PS_DDR4_DQ40
PS_DDR_DQ40_504
AL37
PS_DDR4_DQ41
PS_DDR_DQ41_504
AL38
PS_DDR4_DQ42
PS_DDR_DQ42_504
AK38
PS_DDR4_DQ43
PS_DDR_DQ43_504
AK39
PS_DDR4_DQ44
PS_DDR_DQ44_504
AJ36
PS_DDR4_DQ45
PS_DDR_DQ45_504
AL35
PS_DDR4_DQ46
PS_DDR_DQ46_504
AJ35
PS_DDR4_DQ47
PS_DDR_DQ47_504
AK35
PS_DDR4_DQ48
PS_DDR_DQ48_504
AR42
PS_DDR4_DQ49
PS_DDR_DQ49_504
AT41
PS_DDR4_DQ50
PS_DDR_DQ50_504
AT42
PS_DDR4_DQ51
PS_DDR_DQ51_504
AT40

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PS_DDR4_DQ52
PS_DDR_DQ52_504
AV42
PS_DDR4_DQ53
PS_DDR_DQ53_504
AV41
PS_DDR4_DQ54
PS_DDR_DQ54_504
AV39
PS_DDR4_DQ55
PS_DDR_DQ55_504
AV38
PS_DDR4_DQ56
PS_DDR_DQ56_504
AM39
PS_DDR4_DQ57
PS_DDR_DQ57_504
AM38
PS_DDR4_DQ58
PS_DDR_DQ58_504
AM40
PS_DDR4_DQ59
PS_DDR_DQ59_504
AM41
PS_DDR4_DQ60
PS_DDR_DQ60_504
AJ42
PS_DDR4_DQ61
PS_DDR_DQ61_504
AK42
PS_DDR4_DQ62
PS_DDR_DQ62_504
AK40
PS_DDR4_DQ63
PS_DDR_DQ63_504
AK41
PS_DDR4_DQ64
PS_DDR4_DQ64_504
BB40
PS_DDR4_DQ65
PS_DDR4_DQ65_504
BA41
PS_DDR4_DQ66
PS_DDR4_DQ66_504
BA42
PS_DDR4_DQ67
PS_DDR4_DQ67_504
BA40
PS_DDR4_DQ68
PS_DDR4_DQ68_504
AW42
PS_DDR4_DQ69
PS_DDR4_DQ69_504
AW40
PS_DDR4_DQ70
PS_DDR4_DQ70_504
AW41
PS_DDR4_DQ71
PS_DDR4_DQ71_504
AW39
PS_DDR4_DM0
PS_DDR_DM0_504
AY29
PS_DDR4_DM1
PS_DDR_DM1_504
AY34
PS_DDR4_DM2
PS_DDR_DM2_504
AR29
PS_DDR4_DM3
PS_DDR_DM3_504
AR33
PS_DDR4_DM4
PS_DDR_DM4_504
AR39
PS_DDR4_DM5
PS_DDR_DM5_504
AL36
PS_DDR4_DM6
PS_DDR_DM6_504
AU39
PS_DDR4_DM7
PS_DDR_DM7_504
AL42
PS_DDR4_DM8
PS_DDR_DM8_504
AY42
PS_DDR4_A0
PS_DDR_A0_504
BA38
PS_DDR4_A1
PS_DDR_A1_504
BB36
PS_DDR4_A2
PS_DDR_A2_504
BA35
PS_DDR4_A3
PS_DDR_A3_504
BB35
PS_DDR4_A4
PS_DDR_A4_504
BB38
PS_DDR4_A5
PS_DDR_A5_504
AY35
PS_DDR4_A6
PS_DDR_A6_504
AP37

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PS_DDR4_A7
PS_DDR_A7_504
AT36
PS_DDR4_A8
PS_DDR_A8_504
AR35
PS_DDR4_A9
PS_DDR_A9_504
AT35
PS_DDR4_A10
PS_DDR_A10_504
AU35
PS_DDR4_A11
PS_DDR_A11_504
AU36
PS_DDR4_A12
PS_DDR_A12_504
AW36
PS_DDR4_A13
PS_DDR_A13_504
AW37
PS_DDR4_ACT_B
PS_DDR_ACT_N_504
AR37
PS_DDR4_ALERT_B
PS_DDR_ALERT_N_504
AM36
PS_DDR4_BA0
PS_DDR_BA0_504
AN37
PS_DDR4_BA1
PS_DDR_BA1_504
AN36
PS_DDR4_BG0
PS_DDR_BG0_504
AP36
PS_DDR4_CAS_B
PS_DDR_A15_504
AW34
PS_DDR4_CKE0
PS_DDR_CKE0_504
AY38
PS_DDR4_CLK0_N
PS_DDR_CK_N0_504
BA37
PS_DDR4_CLK0_P
PS_DDR_CK0_504
BA36
PS_DDR4_CS0_B
PS_DDR_CS_N0_504
AY37
PS_DDR4_ODT0
PS_DDR_ODT0_504
BB39
PS_DDR4_PARITY
PS_DDR_PARITY_504
AM35
PS_DDR4_RAS_B
PS_DDR_A16_504
AR34
PS_DDR4_RESET_B
PS_DDR_RAM_RST_N_504
AM34
PS_DDR4_WE_B
PS_DDR_A14_504
AW35
PL Side DDR4 SDRAM pin assignment:
Signal name
Pin name
Pin number
PL_DDR4_DQS0_N
IO_L10N_T1U_N7_QBC_AD4N_70
G23
PL_DDR4_DQS0_P
IO_L10P_T1U_N6_QBC_AD4P_70
H23
PL_DDR4_DQS1_N
IO_L4N_T0U_N7_DBC_AD7N_70
K24
PL_DDR4_DQS1_P
IO_L4P_T0U_N6_DBC_AD7P_70
L24
PL_DDR4_DQS2_N
IO_L22N_T3U_N7_DBC_AD0N_70
B26
PL_DDR4_DQS2_P
IO_L22P_T3U_N6_DBC_AD0P_70
B25
PL_DDR4_DQS3_N
IO_L16N_T2U_N7_QBC_AD3N_70
E27
PL_DDR4_DQS3_P
IO_L16P_T2U_N6_QBC_AD3P_70
E26
PL_DDR4_DQS4_N
IO_L10N_T1U_N7_QBC_AD4N_69
A32
PL_DDR4_DQS4_P
IO_L10P_T1U_N6_QBC_AD4P_69
B31
PL_DDR4_DQS5_N
IO_L4N_T0U_N7_DBC_AD7N_69
F30

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PL_DDR4_DQS5_P
IO_L4P_T0U_N6_DBC_AD7P_69
G30
PL_DDR4_DQS6_N
IO_L22N_T3U_N7_DBC_AD0N_69
A40
PL_DDR4_DQS6_P
IO_L22P_T3U_N6_DBC_AD0P_69
A39
PL_DDR4_DQS7_N
IO_L16N_T2U_N7_QBC_AD3N_69
C34
PL_DDR4_DQS7_P
IO_L16P_T2U_N6_QBC_AD3P_69
D34
PL_DDR4_DQ0
IO_L12N_T1U_N11_GC_70
G25
PL_DDR4_DQ1
IO_L9N_T1L_N5_AD12N_70
J24
PL_DDR4_DQ2
IO_L11P_T1U_N8_GC_70
H25
PL_DDR4_DQ3
IO_L8N_T1L_N3_AD5N_70
J26
PL_DDR4_DQ4
IO_L12P_T1U_N10_GC_70
H24
PL_DDR4_DQ5
IO_L8P_T1L_N2_AD5P_70
K26
PL_DDR4_DQ6
IO_L11N_T1U_N9_GC_70
H26
PL_DDR4_DQ7
IO_L9P_T1L_N4_AD12P_70
J23
PL_DDR4_DQ8
IO_L2P_T0L_N2_70
M25
PL_DDR4_DQ9
IO_L6P_T0U_N10_AD6P_70
M23
PL_DDR4_DQ10
IO_L2N_T0L_N3_70
L25
PL_DDR4_DQ11
IO_L6N_T0U_N11_AD6N_70
L23
PL_DDR4_DQ12
IO_L3P_T0L_N4_AD15P_70
N24
PL_DDR4_DQ13
IO_L5N_T0U_N9_AD14N_70
N23
PL_DDR4_DQ14
IO_L3N_T0L_N5_AD15N_70
N25
PL_DDR4_DQ15
IO_L5P_T0U_N8_AD14P_70
P23
PL_DDR4_DQ16
IO_L20N_T3L_N3_AD1N_70
A28
PL_DDR4_DQ17
IO_L24P_T3U_N10_70
A24
PL_DDR4_DQ18
IO_L21N_T3L_N5_AD8N_70
B27
PL_DDR4_DQ19
IO_L23N_T3U_N9_70
C25
PL_DDR4_DQ20
IO_L20P_T3L_N2_AD1P_70
A27
PL_DDR4_DQ21
IO_L21P_T3L_N4_AD8P_70
C26
PL_DDR4_DQ22
IO_L24N_T3U_N11_70
A25
PL_DDR4_DQ23
IO_L23P_T3U_N8_70
C24
PL_DDR4_DQ24
IO_L15P_T2L_N4_AD11P_70
F27
PL_DDR4_DQ25
IO_L14P_T2L_N2_GC_70
F25
PL_DDR4_DQ26
IO_L17P_T2U_N8_AD10P_70
D27
PL_DDR4_DQ27
IO_L14N_T2L_N3_GC_70
E25
PL_DDR4_DQ28
IO_L15N_T2L_N5_AD11N_70
F28
PL_DDR4_DQ29
IO_L18P_T2U_N10_AD2P_70
F24
PL_DDR4_DQ30
IO_L17N_T2U_N9_AD10N_70
D28

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PL_DDR4_DQ31
IO_L18N_T2U_N11_AD2N_70
E24
PL_DDR4_DQ32
IO_L11N_T1U_N9_GC_69
D31
PL_DDR4_DQ33
IO_L9P_T1L_N4_AD12P_69
A29
PL_DDR4_DQ34
IO_L12P_T1U_N10_GC_69
C30
PL_DDR4_DQ35
IO_L9N_T1L_N5_AD12N_69
A30
PL_DDR4_DQ36
IO_L11P_T1U_N8_GC_69
E31
PL_DDR4_DQ37
IO_L8P_T1L_N2_AD5P_69
C29
PL_DDR4_DQ38
IO_L12N_T1U_N11_GC_69
C31
PL_DDR4_DQ39
IO_L8N_T1L_N3_AD5N_69
B30
PL_DDR4_DQ40
IO_L3N_T0L_N5_AD15N_69
F32
PL_DDR4_DQ41
IO_L5P_T0U_N8_AD14P_69
G28
PL_DDR4_DQ42
IO_L2N_T0L_N3_69
H30
PL_DDR4_DQ43
IO_L6P_T0U_N10_AD6P_69
J28
PL_DDR4_DQ44
IO_L2P_T0L_N2_69
J30
PL_DDR4_DQ45
IO_L6N_T0U_N11_AD6N_69
H28
PL_DDR4_DQ46
IO_L3P_T0L_N4_AD15P_69
F31
PL_DDR4_DQ47
IO_L5N_T0U_N9_AD14N_69
F29
PL_DDR4_DQ48
IO_L24P_T3U_N10_69
C42
PL_DDR4_DQ49
IO_L21N_T3L_N5_AD8N_69
A38
PL_DDR4_DQ50
IO_L23P_T3U_N8_69
B40
PL_DDR4_DQ51
IO_L20N_T3L_N3_AD1N_69
B37
PL_DDR4_DQ52
IO_L24N_T3U_N11_69
B42
PL_DDR4_DQ53
IO_L20P_T3L_N2_AD1P_69
B36
PL_DDR4_DQ54
IO_L23N_T3U_N9_69
B41
PL_DDR4_DQ55
IO_L21P_T3L_N4_AD8P_69
A37
PL_DDR4_DQ56
IO_L15N_T2L_N5_AD11N_69
C33
PL_DDR4_DQ57
IO_L17N_T2U_N9_AD10N_69
A35
PL_DDR4_DQ58
IO_L15P_T2L_N4_AD11P_69
D33
PL_DDR4_DQ59
IO_L14N_T2L_N3_GC_69
B33
PL_DDR4_DQ60
IO_L14P_T2L_N2_GC_69
B32
PL_DDR4_DQ61
IO_L18N_T2U_N11_AD2N_69
A34
PL_DDR4_DQ62
IO_L17P_T2U_N8_AD10P_69
B35
PL_DDR4_DQ63
IO_L18P_T2U_N10_AD2P_69
A33
PL_DDR4_DM0
IO_L7P_T1L_N0_QBC_AD13P_70
K27
PL_DDR4_DM1
IO_L1P_T0L_N0_DBC_70
P26
PL_DDR4_DM2
IO_L19P_T3L_N0_DBC_AD9P_70
C28

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PL_DDR4_DM3
IO_L13P_T2L_N0_GC_QBC_70
G26
PL_DDR4_DM4
IO_L7P_T1L_N0_QBC_AD13P_69
E29
PL_DDR4_DM5
IO_L1P_T0L_N0_DBC_69
K29
PL_DDR4_DM6
IO_L19P_T3L_N0_DBC_AD9P_69
C36
PL_DDR4_DM7
IO_L13P_T2L_N0_GC_QBC_69
E32
PL_DDR4_A0
IO_L6N_T0U_N11_AD6N_71
M21
PL_DDR4_A1
IO_L5N_T0U_N9_AD14N_71
N21
PL_DDR4_A2
IO_L16N_T2U_N7_QBC_AD3N_71
E20
PL_DDR4_A3
IO_L5P_T0U_N8_AD14P_71
P21
PL_DDR4_A4
IO_L17P_T2U_N8_AD10P_71
E21
PL_DDR4_A5
IO_L15N_T2L_N5_AD11N_71
E19
PL_DDR4_A6
IO_L6P_T0U_N10_AD6P_71
M22
PL_DDR4_A7
IO_L7N_T1L_N1_QBC_AD13N_71
J19
PL_DDR4_A8
IO_L9N_T1L_N5_AD12N_71
J21
PL_DDR4_A9
IO_L16P_T2U_N6_QBC_AD3P_71
F20
PL_DDR4_A10
IO_L8P_T1L_N2_AD5P_71
L20
PL_DDR4_A11
IO_L3P_T0L_N4_AD15P_71
M20
PL_DDR4_A12
IO_L4P_T0U_N6_DBC_AD7P_71
N20
PL_DDR4_A13
IO_L7P_T1L_N0_QBC_AD13P_71
K19
PL_DDR4_CS_B
IO_L4N_T0U_N7_DBC_AD7N_71
N19
PL_DDR4_ACT_B
IO_L8N_T1L_N3_AD5N_71
K20
PL_DDR4_ODT
IO_L9P_T1L_N4_AD12P_71
K21
PL_DDR4_WE_B
IO_L10N_T1U_N7_QBC_AD4N_71
J22
PL_DDR4_BA0
IO_L10P_T1U_N6_QBC_AD4P_71
K22
PL_DDR4_BA1
IO_L15P_T2L_N4_AD11P_71
F19
PL_DDR4_CAS_B
IO_L11N_T1U_N9_GC_71
H19
PL_DDR4_RAS_B
IO_L11P_T1U_N8_GC_71
H20
PL_DDR4_CLK_N
IO_L13N_T2L_N1_GC_QBC_71
G21
PL_DDR4_CLK_P
IO_L13P_T2L_N0_GC_QBC_71
G22
PL_DDR4_BG0
IO_L14N_T2L_N3_GC_71
F22
PL_DDR4_CKE
IO_L17N_T2U_N9_AD10N_71
D21
PL_DDR4_RST
IO_L14P_T2L_N2_GC_71
F23
Part 2.4: QSPI Flash
The ACU19EG core board is equipped with two 512Mbit Quad SPI FLASH chips to

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form an 8-bit bandwidth data bus. The FLASH model is MT25QU512ABB1EW9-0SIT,
which uses the 1.8V CMOS voltage standard. Due to the non volatile nature of QSPI
FLASH, it can be used as a boot device to store the system's boot image during use.
These images mainly include FPGA bit files, ARM application code, and other user
data files. The specific models and related parameters of QSPI FLASH are shown in
Table 2-4-1.
Reference
Part number
Capacity
Factory
U2,U3
MT25QU512ABB1EW9-0SIT
512M bit
Micron
Table 2-4-1: QSPI FLASH Specification
QSPI FLASH is connected to the GPIO port of BANK500 in the PS part of the
ZYNQ chip. In the system design, it is necessary to configure these GPIO ports on the
PS side to function as QSPI FLASH interfaces. Figure 4-1 shows the part of QSPI Flash
in the schematic diagram.
Figure 2-4-1: QSPI Flash in the schematic
Configure chip pin assignments:
Signal Name
Pin Name
Pin Number
MIO5_QSPI0_SS_B
PS_MIO5_500
AL32
MIO0_QSPI0_SCLK
PS_MIO0_500
AM33
MIO4_QSPI0_IO0
PS_MIO4_500
AL33
MIO1_QSPI0_IO1
PS_MIO1_500
AM29

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MIO2_QSPI0_IO2
PS_MIO2_500
AM31
MIO3_QSPI0_IO3
PS_MIO3_500
AM30
MIO7_QSPI1_SS_B
PS_MIO7_500
AL30
MIO12_QSPI1_SCLK
PS_MIO12_500
AJ34
MIO8_QSPI1_IO0
PS_MIO8_500
AK33
MIO9_QSPI1_IO1
PS_MIO9_500
AK34
MIO10_QSPI1_IO2
PS_MIO10_500
AK30
MIO11_QSPI1_IO3
PS_MIO11_500
AK32
Part 2.5: eMMC Flash
The ACU19EG core board is equipped with a large capacity 32GB eMMC FLASH
chip, model MTFC32GAPALBH-IT, which supports the JEDEC e-MMC V5.0 standard
HS-MMC interface and supports levels of 1.8V or 3.3V. The data width for eMMC
FLASH and ZYNQ connections is 8 bits. Due to the large capacity and non volatile
characteristics of eMMC FLASH, it can be used as a system storage device for large
capacity in the ZYNQ system, such as storing ARM applications, system files, and
other user data files. The specific models and related parameters of eMMC FLASH are
shown in Table 2-5-1.
Reference
Part Number
Capacity
Factory
U8
MTFC32GAPALBH-IT
32G Byte
Micron
Table 2-5-1: eMMC FLASH Specification
The eMMC FLASH is connected to MIOs PS side of the ZYNQ UltraScale+. In the
system design, it is necessary to configure these GPIO ports on the PS end as EMMC
interfaces. Figure 2-5-1 shows the part of eMMC Flash in the schematic diagram.
Table 2-5-1: eMMC FLASH Specification

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Configuration Chip pin assignment：
Signal Name
Pin Name
Pin Number
MMC_CCLK
PS_MIO22_500
AH32
MMC_CMD
PS_MIO21_500
AF35
MMC_DAT0
PS_MIO13_500
AD34
MMC_DAT1
PS_MIO14_500
AJ32
MMC_DAT2
PS_MIO15_500
AD35
MMC_DAT3
PS_MIO16_500
AJ31
MMC_DAT4
PS_MIO17_500
AJ30
MMC_DAT5
PS_MIO18_500
AE34
MMC_DAT6
PS_MIO19_500
AE35
MMC_DAT7
PS_MIO20_500
AH34
MMC_RSTN
PS_MIO23_500
AG35
Part 2.6: Clock configuration
The core board provides reference clock and RTC real-time clock for PS system
and PL logic respectively, so that PS system and PL logic can work independently. The
schematic diagram of the clock circuit design is shown in Figure 2-6-1:
Figure 2-6-1: Core Board Clock Source
PS System RTC Real Time Clock
The crystal of Y1 on the core board provides a 32.768KHz clock source for the RTC
real-time. The schematic diagram is shown in Figure 2-6-2:

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Figure 2-6-2: Crystal Oscillator for RTC
Clock pin assignment：
Signal Name
Pin
PS_PADI_503
AE28
PS_PADO_503
AE27
PS System Clock Source
The X1 crystal on the core board provides a 33.333MHz clock input for the PS
part. The clock input is connected to the PS_REF_CLK_503 pin of BANK503 of the
ZYNQ chip. The schematic diagram is shown in Figure 2-6-3:
Figure 2-6-3: Active Crystal in PS part
Clock pin assignment:
Signal Name
Pin
PS_REF_CLK
AC27
PL System Clock Source
The core board provides a differential 200MHz clock source for the reference
clock of the DDR4 controller. The clock is connected to the global clock (MRCC) of PL
BANK71. The schematic diagram of this clock source is shown in Figure 2-6-4:

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Figure 2-6-4: PL system clock source
PL Clock pin assignment:
Signal Name
Pin
PL_CLK0_P
H21
PL_CLK0_N
G20
Part 2.7: Power Supply
The power supply voltage of the ACU19EG core board is DC12V, which is
supplied by the carrier board. The core board uses a DC/DC power of
MAX20796GFB+ to provide the core power of 0.85V. a PMIC chip TPS6508640 is used
to generate all other power supplies required by the XCZU9EG chip. For the
TPS6508640 power supply design, please refer to the power supply chip manual. The
design block diagram is as follows :

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