Alinx ACU3EG User manual

ZYNQ UltraScale+
FPGA Development Board
ACU3EG
System on Module

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Version Record
Version
Date
Release By
Description
Rev 1.0
2021-04-23
Rachel Zhou
First Release

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Table of Contents
Version Record.......................................................................................................2
Part 1: ACU3EG Core Board Introduction.........................................................4
Part 2: ZYNQ Chip.................................................................................................6
Part 3: DDR4 DRAM............................................................................................. 8
Part 4: QSPI Flash.............................................................................................. 15
Part 5: eMMC Flash............................................................................................ 17
Part 6: Clock Configuration................................................................................19
Part 7: LED........................................................................................................... 22
Part 8: Power Supply.......................................................................................... 23
Part 9: ACU3EG Core Board Size Dimension............................................... 25
Part 10: Board to Board Connectors Pin Assignment...................................26

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Part 1: ACU3EG core board Introduction
ACU3EG (core board model, the same below) FPGA core board, ZYNQ
chip is based on XCZU3EG-1SFVC784I of XILINX company Zynq UltraScale+
MPSoCs EG series.
This core board uses 5 Micron DDR4 chips MT40A512M16GE, of which 4
DDR4 chips are mounted on the PS side to form a 64-bit data bus bandwidth
and 4GB capacity. One DDR4 chip is mounted on the PL end, which is a 16-bit
data bus width and a capacity of 1GB. The highest operating speed of DDR4
SDRAM on the PS side can reach 1200MHz (data rate 2400Mbps), and the
highest operating speed of DDR4 SDRAM on the PL side can reach 1066MHz
(data rate 2132Mbps). In addition, a 256MBit QSPI FLASH and an 8GB eMMC
FLASH chip are also integrated on the core board to start storage configuration
and system files.
In order to connect with the carrier board, the four board-to-board
connectors of this core board expand the PS side USB2.0 interface, Gigabit
Ethernet interface, SD card interface and other remaining MIO ports; also
expand 4 pairs of PS MGT high-speed transceiver interface; and almost all IO
ports on the PL side (HP I/O: 96, HD I/O: 84). The wiring between the CZU3EG
chip and the interface has been processed with equal length and differential,
and the core board size is only 3.15*2.36 (inch), which is very suitable for
secondary development.

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Figure 1-1: ACU3EG Core Board (Front View)

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Part 2: ZYNQ Chip
The FPGA core board ACU3Eg uses Xilinx's Zynq UltraScale+ MPSoCs
EG series chip, module XCZU3EG-1SFVC784I. The PS system of the ZU3EG
chip integrates 4 ARM Cortex™-A53 processors with a speed of up to 1.2Ghz
and supports Level 2 Cache; it also contains 2 Cortex-R5 processors with a
speed of up to 500Mhz
The ZU3EG chip supports 32-bit or 64-bit DDR4, LPDDR4, DDR3, DDR3L,
LPDDR3 memory chips, with rich high-speed interfaces on the PS side such as
PCIE Gen2, USB3.0, SATA 3.1, DisplayPort; it also supports USB2.0 , Gigabit
Ethernet, SD/SDIO, I2C, CAN, UART, GPIO and other interfaces. The PL end
contains a wealth of programmable logic units, DSP and internal RAM. .
Figure 2-1 detailed the Overall Block Diagram of the ZU3EG Chip.
Figure 2-1: Overall Block Diagram of the ZYNQ ZU3EG Chip

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The main parameters of the PS system part are as follows:
ARM quad-core Cortex ™-A53 processor, speed up to 1.2GHz, each
CPU 32KB level 1 instruction and data cache, 1MB level 2 cache,
shared by 2 CPUs
ARM dual-core Cortex-R5 processor, speed up to 500MHz, each CPU
32KB level 1 instruction and data cache, and 128K tightly coupled
memory.
External storage interface, support 32/64bit DDR4/3/3L, LPDDR4/3
interface
Static storage interface, support NAND, 2xQuad-SPI FLASH.
High-speed connection interface, support PCIe Gen2 x 4, 2 x USB3.0,
Sata 3.1, Display Port, 4 x Tri-mode Gigabit Ethernet
Common connection interfaces: 2 x USB2.0, 2 x SD/SDIO, 2 x UART,
2 x CAN 2.0B, 2 x I2C, 2 x SPI, 4 x 32b GPIO
Power management: Supports the division of four parts of power
supply Full/Low/PL/Battery.
Encryption algorithm: support RSA, AES and SHA.
System monitoring: 10-bit 1Mbps AD sampling for temperature and
voltage detection.
The main parameters of the PL logic part are as follows:
Logic Cells: 154K
Flip-flops: 141K
Look-up-tables (LUTs): 71K
 Block RAM : 240KB
Clock Management Units (CMTs): 3
18x25MACCs: 360
XCZU3EG-1SFVC784I chip speed grade is -1, industrial grade, package
is SFVC784

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Part 3: DDR4 DRAM
The ACU3EG core board is equipped with 5 Micron (Micron) 1GB DDR4
chips, model MT40A512M16LY-062E, of which 4 DDR4 chips are mounted on
the PS side to form a 64-bit data bus bandwidth and 4GB capacity. One DDR4
chip is mounted on the PL end, which is a 16-bit data bus width and a capacity
of 1GB. The maximum operating speed of the DDR4 SDRAM on the PS side
can reach 1200MHz (data rate 2400Mbps), and the 4 DDR4 storage systems
are directly connected to the memory interface of the PS BANK504. The
highest operating speed of the DDR4 SDRAM on the PL side can reach
1066MHz (data rate 2133Mbps), and a piece of DDR4 is connected to the
BANK64 interface of the FPGA. The specific configuration of DDR4 SDRAM is
shown in Table 3-1 below:
Bit Number
Chip Model
Capacity
Factory
U12,U14,U15,U16
MT40A512M16LY-062E
512M x 16bit
Micron
Table 3-1: DDR4 SDRAM Configuration
The hardware design of DDR4 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR4.
The hardware connection of DDR4 SDRAM on the PS Side is shown in
Figure 3-1:

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Figure 3-1: DDR3 DRAM schematic diagram
The hardware connection of DDR4 SDRAM on the Pl Side is shown in
Figure 3-2:
Figure 3-2: DDR3 DRAM schematic diagram

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PS Side DDR4 DRAM pin assignment:
Signal Name
Pin Name
Pin Number
PS_DDR4_DQS0_P
PS_DDR_DQS_P0_504
AF21
PS_DDR4_DQS0_N
PS_DDR_DQS_N0_504
AG21
PS_DDR4_DQS1_P
PS_DDR_DQS_P1_504
AF23
PS_DDR4_DQS1_N
PS_DDR_DQS_N1_504
AG23
PS_DDR4_DQS2_P
PS_DDR_DQS_P2_504
AF25
PS_DDR4_DQS2_N
PS_DDR_DQS_N2_504
AF26
PS_DDR4_DQS3_P
PS_DDR_DQS_P3_504
AE27
PS_DDR4_DQS3_N
PS_DDR_DQS_N3_504
AF27
PS_DDR4_DQS4_P
PS_DDR_DQS_P4_504
N23
PS_DDR4_DQS4_N
PS_DDR_DQS_N4_504
M23
PS_DDR4_DQS5_P
PS_DDR_DQS_P5_504
L23
PS_DDR4_DQS5_N
PS_DDR_DQS_N5_504
K23
PS_DDR4_DQS6_P
PS_DDR_DQS_P6_504
N26
PS_DDR4_DQS6_N
PS_DDR_DQS_N6_504
N27
PS_DDR4_DQS7_P
PS_DDR_DQS_P7_504
J26
PS_DDR4_DQS7_N
PS_DDR_DQS_N7_504
J27
PS_DDR4_DQ0
PS_DDR_DQ0_504
AD21
PS_DDR4_DQ1
PS_DDR_DQ1_504
AE20
PS_DDR4_DQ2
PS_DDR_DQ2_504
AD20
PS_DDR4_DQ3
PS_DDR_DQ3_504
AF20
PS_DDR4_DQ4
PS_DDR_DQ4_504
AH21
PS_DDR4_DQ5
PS_DDR_DQ5_504
AH20
PS_DDR4_DQ6
PS_DDR_DQ6_504
AH19
PS_DDR4_DQ7
PS_DDR_DQ7_504
AG19
PS_DDR4_DQ8
PS_DDR_DQ8_504
AF22
PS_DDR4_DQ9
PS_DDR_DQ9_504
AH22
PS_DDR4_DQ10
PS_DDR_DQ10_504
AE22
PS_DDR4_DQ11
PS_DDR_DQ11_504
AD22
PS_DDR4_DQ12
PS_DDR_DQ12_504
AH23
PS_DDR4_DQ13
PS_DDR_DQ13_504
AH24
PS_DDR4_DQ14
PS_DDR_DQ14_504
AE24
PS_DDR4_DQ15
PS_DDR_DQ15_504
AG24
PS_DDR4_DQ16
PS_DDR_DQ16_504
AC26
PS_DDR4_DQ17
PS_DDR_DQ17_504
AD26