Alinx ACU15EG User manual

ZYNQ UltraScale+ MPSoC
FPGA Core Board
ACU15EG
User Manual

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Version Record
Version
Date
Release By
Description
Rev 1.1
2021-06-24
Rachel Zhou
First Release

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Table of Contents
Version Record .............................................................................................2
ACU15EG Core Board .................................................................................4
Part 1: ACU15EG Core Board Introduction ..........................................4
Part 2: ZYNQ Chip ................................................................................ 5
Part 3: DDR4 DRAM ............................................................................. 7
Part 4: QSPI Flash .............................................................................. 14
Part 5: eMMC Flash ............................................................................ 16
Part 6: Clock configuration ..................................................................17
Part 7: Power Supply .......................................................................... 20
Part 8: ACU15EG Core Board Size Dimension ..................................22
Part 10: Board to Board Connectors pin assignment.........................22

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ACU15EG Core Board
Part 1: ACU15EG Core Board Introduction
ACU15EG (core board model, the same below) FPGA core board, ZYNQ
chip is based on XCZU15EG-2FFVB1156I of XILINX company Zynq
UltraScale+ MPSoCs EG Family.
This core board uses 6 Micron DDR4 chips MT40A512M16GE, of which 4
DDR4 chips are mounted on the PS side to form a 64-bit data bus bandwidth
and 4GB capacity. 2 DDR4 chip is mounted on the PL end, which is a 32-bit
data bus width and a capacity of 2GB. The highest operating speed of DDR4
SDRAM on the PS side can reach 1200MHz (data rate 2400Mbps), and the
highest operating speed of DDR4 SDRAM on the PL side can reach 1200MHz
(data rate 2400Mbps). In addition, two 256MBit QSPI FLASH and an 8GB
eMMC FLASH chip are also integrated on the core board to start storage
configuration and system files.
In order to connect with the carrier board, the four board-to-board
connectors of this core board expand the PS side USB2.0 interface, Gigabit
Ethernet interface, SD card interface and other remaining MIO ports; also
expand 4 pairs of PS MGT high-speed transceiver interface; and 16 GTH
transceivers and almost all IO ports on the PL side (HP I/O: 96, HD I/O: 84).
The wiring between the XCZU15EG chip and the interface has been processed
with equal length and differential, and the core board size is only 3.15*2.36
(inch), which is very suitable for secondary development.

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Figure 2-1-1: ACU15EG Core Board (Front View)
Part 2: ZYNQ Chip
The FPGA core board ACU15EG uses Xilinx's Zynq UltraScale+ MPSoCs
EG family chip, module XCZU15EG-2FFVB1156I. The PS system of the
ZU15EG chip integrates 4 ARM Cortex™-A53 processors with a speed of up to
1.3Ghz and supports Level 2 Cache; it also contains 2 Cortex-R5 processors
with a speed of up to 533Mhz
The ZU15EG chip supports 32-bit or 64-bit DDR4, LPDDR4, DDR3,
DDR3L, LPDDR3 memory chips, with rich high-speed interfaces on the PS
side such as PCIE Gen2, USB3.0, SATA 3.1, DisplayPort; it also supports
USB2.0, Gigabit Ethernet, SD/SDIO, I2C, CAN, UART, GPIO and other
interfaces. The PL end contains a wealth of programmable logic units, DSP and
internal RAM. .

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Figure 2-2-1 detailed the Overall Block Diagram of the ZU15EG Chip.
Figure 2-2-1: Overall Block Diagram of the ZYNQ ZU15EG Chip
The main parameters of the PS system part are as follows:
ARM quad-core Cortex ™-A53 processor, speed up to 1.3GHz, each
CPU 32KB level 1 instruction and data cache, 1MB level 2 cache,
shared by 2 CPUs
ARM dual-core Cortex-R5 processor, speed up to 533MHz, each CPU
32KB level 1 instruction and data cache, and 128K tightly coupled
memory.
External storage interface, support 32/64bit DDR4/3/3L, LPDDR4/3
interface
Static storage interface, support NAND, 2xQuad-SPI FLASH.

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High-speed connection interface, support PCIe Gen2 x 4, 2 x USB3.0,
Sata 3.1, Display Port, 4 x Tri-mode, Gigabit Ethernet
Common connection interfaces: 2 x USB2.0, 2 x SD/SDIO, 2 x UART,
2 x CAN 2.0B, 2 x I2C, 2 x SPI, 4 x 32b GPIO
Power management: Support the four-part division of power supply
Full/Low/PL/Battery
Encryption algorithm: support RSA, AES and SHA.
System monitoring: 10-bit 1Mbps AD sampling for temperature and
voltage detection.
The main parameters of the PL logic part are as follows:
Logic Cells: 746K
CLB Flip-flops: 682K
Look-up-tables (LUTs): 341K
 Block RAM : 26.2Mb
Clock Management Units (CMTs): 4
 DSP Slices: 3528
GTH 16.3Gb/s Transceiver: 24
XCZU15EV-2FFVB1156I chip speed grade is -2, industrial grade, package
is FFVB1156.
Part 3: DDR4 DRAM
The ACU15EG core board is equipped with 6 Micron (Micron) 1GB DDR4
chips, model MT40A512M16LY-062E, of which 4 DDR4 chips are mounted on
the PS side to form a 64-bit data bus bandwidth and 4GB capacity. Two DDR4
chip is mounted on the PL end, which is a 32-bit data bus width and a capacity
of 2GB. The maximum operating speed of the DDR4 SDRAM on the PS side

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can reach 1200MHz (data rate 2400Mbps), and the 4 DDR4 storage systems
are directly connected to the memory interface of the PS BANK504. The
highest operating speed of the DDR4 SDRAM on the PL side can reach
1200MHz (data rate 2400Mbps), and two piece of DDR4 is connected to the
BANK64,65 interface of the FPGA. The specific configuration of DDR4 SDRAM
is shown in Table 2-3-1 below:
Bit Number
Chip Model
Capacity
Factory
U4,U5,U6,U7
MT40A512M16LY-062E
512M x 16bit
Micron
Table 2-3-1: DDR4 SDRAM Configuration
The hardware design of DDR4 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR4.
The hardware connection of DDR4 SDRAM on the PS Side is shown in
Figure 2-3-1:
Figure 2-3-1: DDR3 DRAM schematic diagram
The hardware connection of DDR4 SDRAM on the Pl Side is shown in

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Figure 2-3-2:
Figure 2-3-2: DDR4 DRAM schematic diagram
PS Side DDR4 DRAM pin assignment:
Signal Name
Pin Name
Pin Number
PS_DDR4_DQS0_N
PS_DDR_DQS_N0_504
AN19
PS_DDR4_DQS0_P
PS_DDR_DQS_P0_504
AN18
PS_DDR4_DQS1_N
PS_DDR_DQS_N1_504
AN22
PS_DDR4_DQS1_P
PS_DDR_DQS_P1_504
AN21
PS_DDR4_DQS2_N
PS_DDR_DQS_N2_504
AJ19
PS_DDR4_DQS2_P
PS_DDR_DQS_P2_504
AH19
PS_DDR4_DQS3_N
PS_DDR_DQS_N3_504
AH23
PS_DDR4_DQS3_P
PS_DDR_DQS_P3_504
AH22
PS_DDR4_DQS4_N
PS_DDR_DQS_N4_504
AH29
PS_DDR4_DQS4_P
PS_DDR_DQS_P4_504
AH28
PS_DDR4_DQS5_N
PS_DDR_DQS_N5_504
AE29
PS_DDR4_DQS5_P
PS_DDR_DQS_P5_504
AE28
PS_DDR4_DQS6_N
PS_DDR_DQS_N6_504
AK32
PS_DDR4_DQS6_P
PS_DDR_DQS_P6_504
AJ32
PS_DDR4_DQS7_N
PS_DDR_DQS_N7_504
AE33
PS_DDR4_DQS7_P
PS_DDR_DQS_P7_504
AE32

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PS_DDR4_DQ0
PS_DDR_DQ0_504
AP20
PS_DDR4_DQ1
PS_DDR_DQ1_504
AP18
PS_DDR4_DQ2
PS_DDR_DQ2_504
AP19
PS_DDR4_DQ3
PS_DDR_DQ3_504
AP17
PS_DDR4_DQ4
PS_DDR_DQ4_504
AM20
PS_DDR4_DQ5
PS_DDR_DQ5_504
AM19
PS_DDR4_DQ6
PS_DDR_DQ6_504
AM18
PS_DDR4_DQ7
PS_DDR_DQ7_504
AL18
PS_DDR4_DQ8
PS_DDR_DQ8_504
AP22
PS_DDR4_DQ9
PS_DDR_DQ9_504
AP21
PS_DDR4_DQ10
PS_DDR_DQ10_504
AP24
PS_DDR4_DQ11
PS_DDR_DQ11_504
AN23
PS_DDR4_DQ12
PS_DDR_DQ12_504
AL21
PS_DDR4_DQ13
PS_DDR_DQ13_504
AL22
PS_DDR4_DQ14
PS_DDR_DQ14_504
AM23
PS_DDR4_DQ15
PS_DDR_DQ15_504
AL23
PS_DDR4_DQ16
PS_DDR_DQ16_504
AL20
PS_DDR4_DQ17
PS_DDR_DQ17_504
AK20
PS_DDR4_DQ18
PS_DDR_DQ18_504
AJ20
PS_DDR4_DQ19
PS_DDR_DQ19_504
AK18
PS_DDR4_DQ20
PS_DDR_DQ20_504
AG20
PS_DDR4_DQ21
PS_DDR_DQ21_504
AH18
PS_DDR4_DQ22
PS_DDR_DQ22_504
AG19
PS_DDR4_DQ23
PS_DDR_DQ23_504
AG18
PS_DDR4_DQ24
PS_DDR_DQ24_504
AG21
PS_DDR4_DQ25
PS_DDR_DQ25_504
AH21
PS_DDR4_DQ26
PS_DDR_DQ26_504
AG24
PS_DDR4_DQ27
PS_DDR_DQ27_504
AG23
PS_DDR4_DQ28
PS_DDR_DQ28_504
AK22
PS_DDR4_DQ29
PS_DDR_DQ29_504
AJ21
PS_DDR4_DQ30
PS_DDR_DQ30_504
AJ22
PS_DDR4_DQ31
PS_DDR_DQ31_504
AK23
PS_DDR4_DQ32
PS_DDR_DQ32_504
AG31
PS_DDR4_DQ33
PS_DDR_DQ33_504
AG30
PS_DDR4_DQ34
PS_DDR_DQ34_504
AG29
PS_DDR4_DQ35
PS_DDR_DQ35_504
AG28

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PS_DDR4_DQ36
PS_DDR_DQ36_504
AJ30
PS_DDR4_DQ37
PS_DDR_DQ37_504
AK29
PS_DDR4_DQ38
PS_DDR_DQ38_504
AK30
PS_DDR4_DQ39
PS_DDR_DQ39_504
AJ29
PS_DDR4_DQ40
PS_DDR_DQ40_504
AE27
PS_DDR4_DQ41
PS_DDR_DQ41_504
AF28
PS_DDR4_DQ42
PS_DDR_DQ42_504
AF30
PS_DDR4_DQ43
PS_DDR_DQ43_504
AF31
PS_DDR4_DQ44
PS_DDR_DQ44_504
AD28
PS_DDR4_DQ45
PS_DDR_DQ45_504
AD27
PS_DDR4_DQ46
PS_DDR_DQ46_504
AD29
PS_DDR4_DQ47
PS_DDR_DQ47_504
AD30
PS_DDR4_DQ48
PS_DDR_DQ48_504
AH33
PS_DDR4_DQ49
PS_DDR_DQ49_504
AJ34
PS_DDR4_DQ50
PS_DDR_DQ50_504
AH34
PS_DDR4_DQ51
PS_DDR_DQ51_504
AH32
PS_DDR4_DQ52
PS_DDR_DQ52_504
AK34
PS_DDR4_DQ53
PS_DDR_DQ53_504
AK33
PS_DDR4_DQ54
PS_DDR_DQ54_504
AL32
PS_DDR4_DQ55
PS_DDR_DQ55_504
AL31
PS_DDR4_DQ56
PS_DDR_DQ56_504
AG33
PS_DDR4_DQ57
PS_DDR_DQ57_504
AG34
PS_DDR4_DQ58
PS_DDR_DQ58_504
AF32
PS_DDR4_DQ59
PS_DDR_DQ59_504
AF33
PS_DDR4_DQ60
PS_DDR_DQ60_504
AD31
PS_DDR4_DQ61
PS_DDR_DQ61_504
AD32
PS_DDR4_DQ62
PS_DDR_DQ62_504
AD34
PS_DDR4_DQ63
PS_DDR_DQ63_504
AD33
PS_DDR4_DM0
PS_DDR_DM0_504
AG20
PS_DDR4_DM1
PS_DDR_DM0_504
AN17
PS_DDR4_DM2
PS_DDR_DM1_504
AM21
PS_DDR4_DM3
PS_DDR_DM2_504
AK19
PS_DDR4_DM4
PS_DDR_DM3_504
AH24
PS_DDR4_DM5
PS_DDR_DM4_504
AH31
PS_DDR4_DM6
PS_DDR_DM5_504
AE30
PS_DDR4_DM7
PS_DDR_DM6_504
AJ31

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PS_DDR4_A0
PS_DDR_A0_504
AP29
PS_DDR4_A1
PS_DDR_A1_504
AP30
PS_DDR4_A2
PS_DDR_A2_504
AP26
PS_DDR4_A3
PS_DDR_A3_504
AP27
PS_DDR4_A4
PS_DDR_A4_504
AP25
PS_DDR4_A5
PS_DDR_A5_504
AN24
PS_DDR4_A6
PS_DDR_A6_504
AM29
PS_DDR4_A7
PS_DDR_A7_504
AM28
PS_DDR4_A8
PS_DDR_A8_504
AM26
PS_DDR4_A9
PS_DDR_A9_504
AM25
PS_DDR4_A10
PS_DDR_A10_504
AL28
PS_DDR4_A11
PS_DDR_A11_504
AK27
PS_DDR4_A12
PS_DDR_A12_504
AJ25
PS_DDR4_A13
PS_DDR_A13_504
AL25
PS_DDR4_WE_B
PS_DDR_A14_504
AK25
PS_DDR4_CAS_B
PS_DDR_A15_504
AK24
PS_DDR4_RAS_B
PS_DDR_A16_504
AM24
PS_DDR4_ACT_B
PS_DDR_ACT_N_504
AG25
PS_DDR4_ALERT_B
PS_DDR_ALERT_N_504
AF22
PS_DDR4_BA0
PS_DDR_BA0_504
AH26
PS_DDR4_BA1
PS_DDR_BA1_504
AG26
PS_DDR4_BG0
PS_DDR_BG0_504
AK28
PS_DDR4_CS0_B
PS_DDR_CS_N0_504
AN28
PS_DDR4_ODT0
PS_DDR_ODT0_504
AM30
PS_DDR4_PARITY
PS_DDR_PARITY_504
AF20
PS_DDR4_RESET_B
PS_DDR_RST_N_504
AF21
PS_DDR4_CLK0_P
PS_DDR_CK0_504
AN26
PS_DDR4_CLK0_N
PS_DDR_CK_N0_504
AN27
PS_DDR4_CKE0
PS_DDR_CKE0_504
AN29
PL Side DDR4 DRAM pin assignment:
Signal Name
Pin Name
Pin Number
PL_DDR4_DQS0_N
IO_L22N_T3U_N7_DBC_AD0N_65
AF1
PL_DDR4_DQS0_P
IO_L22P_T3U_N6_DBC_AD0P_65
AJ1
PL_DDR4_DQS1_N
IO_L16N_T2U_N7_QBC_AD3N_65
AH1

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PL_DDR4_DQS1_P
IO_L16P_T2U_N6_QBC_AD3P_65
AJ5
PL_DDR4_DQS2_N
IO_L10N_T1U_N7_QBC_AD4N_65
AJ6
PL_DDR4_DQS2_P
IO_L10P_T1U_N6_QBC_AD4P_65
AF8
PL_DDR4_DQS3_N
IO_L4N_T0U_N7_DBC_AD7N_65
AE8
PL_DDR4_DQS3_P
IO_L4P_T0U_N6_DBC_AD7P_65
AG11
PL_DDR4_DQ0
IO_L24P_T3U_N10 _I2C_SDA_65
AE2
PL_DDR4_DQ1
IO_L20P_T3L_N2_AD1P_65
AG3
PL_DDR4_DQ2
IO_L23N_T3U_N9_65
AD1
PL_DDR4_DQ3
IO_L21P_T3L_N4_AD8P_65
AF2
PL_DDR4_DQ4
IO_L23P_T3U_N8_I2C_SCLK_65
AD2
PL_DDR4_DQ5
IO_L20N_T3L_N3_AD1N_65
AH3
PL_DDR4_DQ6
IO_L24N_T3U_N11_PERSTN0_65
AE1
PL_DDR4_DQ7
IO_L21N_T3L_N5_AD8N_65
AF1
PL_DDR4_DQ8
IO_L17P_T2U_N8_AD10P_65
AE3
PL_DDR4_DQ9
IO_L15P_T2L_N4_AD11P_65
AH4
PL_DDR4_DQ10
IO_L18P_T2U_N10_AD2P_65
AD4
PL_DDR4_DQ11
IO_L14N_T2L_N3_GC_65
AG4
PL_DDR4_DQ12
IO_L18N_T2U_N11_AD2N_65
AE4
PL_DDR4_DQ13
IO_L14P_T2L_N2_GC_65
AG5
PL_DDR4_DQ14
IO_L17N_T2U_N9_AD10N_65
AF3
PL_DDR4_DQ15
IO_L15N_T2L_N5_AD11N_65
AJ4
PL_DDR4_DQ16
IO_L9N_T1L_N5_AD12N_65
AD6
PL_DDR4_DQ17
IO_L8P_T1L_N2_AD5P_65
AG8
PL_DDR4_DQ18
IO_L11P_T1U_N8_GC_65
AF6
PL_DDR4_DQ19
IO_L12N_T1U_N11_GC_65
AF7
PL_DDR4_DQ20
IO_L9P_T1L_N4_AD12P_65
AD7
PL_DDR4_DQ21
IO_L8N_T1L_N3_AD5N_65
AH8
PL_DDR4_DQ22
IO_L12P_T1U_N10_GC_65
AE7
PL_DDR4_DQ23
IO_L11N_T1U_N9_GC_65
AG6
PL_DDR4_DQ24
IO_L3P_T0L_N4_AD15P_65
AE12
PL_DDR4_DQ25
IO_L5N_T0U_N9_AD14N_65
AG9
PL_DDR4_DQ26
IO_L2N_T0L_N3_65
AH11
PL_DDR4_DQ27
IO_L6N_T0U_N11_AD6N_65
AE9
PL_DDR4_DQ28
IO_L2P_T0L_N2_65
AH12
PL_DDR4_DQ29
IO_L5P_T0U_N8_AD14P_65
AG10
PL_DDR4_DQ30
IO_L3N_T0L_N5_AD15N_65
AF12

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PL_DDR4_DQ31
IO_L6P_T0U_N10_AD6P_65
AD10
PL_DDR4_DM0
IO_L19P_T3L_N0_DBC_AD9P_65
AH2
PL_DDR4_DM1
IO_L13P_T2L_N0_GC_QBC_65
AE5
PL_DDR4_DM2
IO_L7P_T1L_N0_QBC_AD13P_65
AH7
PL_DDR4_DM3
IO_L1P_T0L_N0_DBC_65
AE10
PL_DDR4_A0
IO_L5P_T0U_N8_AD14P_64
AN9
PL_DDR4_A1
IO_L16P_T2U_N6_QBC_AD3P_64
AN6
PL_DDR4_A2
IO_L10P_T1U_N6_QBC_AD4P_64
AN7
PL_DDR4_A3
IO_L15P_T2L_N4_AD11P_64
AP5
PL_DDR4_A4
IO_L11P_T1U_N8_GC_64
AK8
PL_DDR4_A5
IO_L10N_T1U_N7_QBC_AD4N_64
AP7
PL_DDR4_A6
IO_L3N_T0L_N5_AD15N_64
AM10
PL_DDR4_A7
IO_L7P_T1L_N0_QBC_AD13P_64
AN8
PL_DDR4_A8
IO_L11N_T1U_N9_GC_64
AK7
PL_DDR4_A9
IO_L4N_T0U_N7_DBC_AD7N_64
AP10
PL_DDR4_A10
IO_L14P_T2L_N2_GC_64
AM6
PL_DDR4_A11
IO_L8N_T1L_N3_AD5N_64
AM8
PL_DDR4_A12
IO_L15N_T2L_N5_AD11N_64
AP4
PL_DDR4_A13
IO_L7N_T1L_N1_QBC_AD13N_64
AP8
PL_DDR4_BA0
IO_L6P_T0U_N10_AD6P_64
AJ10
PL_DDR4_BA1
IO_L5N_T0U_N9_AD14N_64
AP9
PL_DDR4_RAS_B
IO_L4P_T0U_N6_DBC_AD7P_64
AP11
PL_DDR4_CAS_B
IO_L16N_T2U_N7_QBC_AD3N_64
AP6
PL_DDR4_WE_B
IO_L9P_T1L_N4_AD12P_64
AJ9
PL_DDR4_ACT_B
IO_L8P_T1L_N2_AD5P_64
AM9
PL_DDR4_CS_B
IO_L17N_T2U_N9_AD10N_64
AN4
PL_DDR4_CKE
IO_L6N_T0U_N11_AD6N_64
AK10
PL_DDR4_OTD
IO_L9N_T1L_N5_AD12N_64
AK9
PL_DDR4_BG0
IO_L3P_T0L_N4_AD15P_64
AL10
PL_DDR4_CLK_N
IO_L13N_T2L_N1_GC_QBC_64
AL5
PL_DDR4_CLK_P
IO_L13P_T2L_N0_GC_QBC_64
AL6
PL_DDR4_RST
IO_L14N_T2L_N3_GC_64
AM5
Part 4: QSPI Flash
The FPGA core board ACU15EG is equipped with two 256MBit Quad-SPI

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FLASH chip to form an 8-bit bandwidth data bus, the flash model is
MT25QU256ABA1EW9, which uses the 1.8V CMOS voltage standard. Due to
the non-volatile nature of QSPI FLASH, it can be used as a boot device for the
system to store the boot image of the system. These images mainly include
FPGA bit files, ARM application code, and other user data files. The specific
models and related parameters of QSPI FLASH are shown in Table 2-4-1.
Position
Model
Capacity
Factory
U2, U3
MT25QU256ABA1EW9
256Mbit
Winbond
Table 2-4-1: QSPI FLASH Specification
QSPI FLASH is connected to the GPIO port of the BANK500 in the PS
section of the ZYNQ chip. In the system design, the GPIO port functions of
these PS ports need to be configured as the QSPI FLASH interface. Figure
2-4-1 shows the QSPI Flash in the schematic.
Figure 2-4-1: QSPI Flash in the schematic
Configure chip pin assignments:

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Signal Name
Pin Name
Pin Number
MIO5_QSPI0_SS_B
PS_MIO5_500
AM15
MIO0_QSPI0_SCLK
PS_MIO0_500
AF16
MIO1_QSPI0_IO1
PS_MIO1_500
AJ16
MIO1_QSPI0_IO2
PS_MIO2_500
AD16
MIO1_QSPI0_IO3
PS_MIO3_500
AG16
MIO1_QSPI0_IO0
PS_MIO4_500
AH16
MIO7_QSPI1_SS_B
PS_MIO7_500
AD17
MIO12_QSPI1_SCLK
PS_MIO12_500
AJ17
MIO8_QSPI1_IO0
PS_MIO8_500
AE17
MIO8_QSPI1_IO1
PS_MIO9_500
AP15
MIO8_QSPI1_IO2
PS_MIO10_500
AH17
MIO8_QSPI1_IO3
PS_MIO11_500
AF17
Part 5: eMMC Flash
The ACU15EG core board is equipped with a large-capacity 8GB eMMC
FLASH chip, the model is MTFC8GAKAJCN-4M, it supports the HS-MMC
interface of the JEDEC e-MMC V5.0 standard, and the level supports 1.8V or
3.3V. The data width of eMMC FLASH and ZYNQ connection is 8bit. Due to the
large-capacity and non-volatile characteristics of eMMC FLASH, it can be used
as a large-capacity storage device in the ZYNQ system, such as storing ARM
applications, system files and other user data files The specific models and
related parameters of eMMC FLASH are shown in Table 2-5-1.
Position
Model
Capacity
Factory
U19
MTFC8GAKAJCN-4M
8G Byte
Micron
Table 2-5-1: eMMC FLASH Specification
The eMMC FLASH is connected to the GPIO port of the BANK500 of the
PS part of the ZYNQ UltraScale+. In the system design, it is necessary to
configure the GPIO port function of the PS side as an EMMC interface. Figure
2-5-1 shows the part of eMMC Flash in the schematic diagram.

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Figure 2-5-1: eMMC Flash in the schematic
Configuration Chip pin assignment:
Signal Name
Pin Name
Pin Number
MMC_CCLK
PS_MIO22_500
AD20
MMC_CMD
PS_MIO21_500
AF18
MMC_DAT0
PS_MIO13_500
AK17
MMC_DAT1
PS_MIO14_500
AL16
MMC_DAT2
PS_MIO15_500
AN16
MMC_DAT3
PS_MIO16_500
AM16
MMC_DAT4
PS_MIO17_500
AP16
MMC_DAT5
PS_MIO18_500
AE18
MMC_DAT6
PS_MIO19_500
AL17
MMC_DAT7
PS_MIO20_500
AD18
MMC_CCLK
PS_MIO22_500
AD20
Part 6: Clock configuration
The core board provides reference clock and RTC real-time clock for PS
system and PL logic respectively, so that PS system and PL logic can work
independently. The schematic diagram of the clock circuit design is shown in
Figure 2-6-1:

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Figure 2-6-1: Core Board Clock Source
PS System RTC Real Time Clock
The passive crystal Y1 on the core board provides a 32.768KHz real-time
clock source for the PS system. The crystal is connected to the PS_PADI_503
and PS_PADO_503 pins of BANK503 of the ZYNQ chip. The schematic
diagram is shown in Figure 2-6-2:
Figure 2-6-2: Passive Crystal Oscillator for RTC
Clock pin assignment:
Signal Name
Pin
PS_PADI_503
V21
PS_PADO_503
V22

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PS System Clock Source
The X1 crystal on the core board provides a 33.333MHz clock input for the
PS part. The clock input is connected to the PS_REF_CLK_503 pin of
BANK503 of the ZYNQ chip. The schematic diagram is shown in Figure 2-6-3:
Figure 2-6-3: Active Crystal in PS part
Clock pin assignment:
Signal Name
Pin
PS_REF_CLK
U24
PL System Clock Source
The core board provides a differential 200MHz PL system clock source for
the reference clock of the DDR4 controller. The crystal oscillator output is
connected to the global clock (MRCC) of PL BANK64. This global clock can be
used to drive the DDR4 controller and user logic circuits in the FPGA. The
schematic diagram of this clock source is shown in Figure 2-6-4

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Figure 2-6-4: PL system clock source
Clock pin assignment:
Signal Name
Pin
PL_CLK0_P
AL8
PL_CLK0_N
AL7
Part 7: Power Supply
The power supply voltage of the ACU15EG core board is DC12V, which is
supplied by connecting the carrier board. The core board uses 2
MYMGM1R824 power chips in parallel to achieve a 50A current to provide the
core power of the XCZU15EG with 0.85V. In addition, a PMIC chip
TPS6508640 is used to generate all other power supplies required by the
XCZU15EG chip. For the TPS6508640 power supply design, please refer to
the power supply chip manual. The design block diagram is as follows :