Alinx ZYNQ7000 FPGA User manual

ZYNQ7000 FPGA
Development Board
AX7010
User Manual

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Version Record
Revision
Date
Release By
Description
Rev 1.0
2020-09-06
Rachel Zhou
First Release

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Table of Contents
Version Record......................................................................................... 2
Part 1: FPGA Development Board Introduction .........................................6
Part 2: Dimensional structure ....................................................................8
Part 3: Power Supply.................................................................................9
Part 4: ZYNQ Chip ..................................................................................11
Part 4.1: JTAG Interface...................................................................14
Part 4.2: FPGA Power System .........................................................16
Part 4.3: ZYNQ boot configuration ...................................................17
Part 5: Clock Configuration......................................................................17
Part 5.1: PS system clock source.....................................................17
Part 5.2: PL system clock source .....................................................18
Part 6：ZYNQ Processor System (PS) peripherals.................................19
Part 6.1: QSPI Flash ........................................................................19
Part 6.2: DDR3 DRAM .....................................................................21
Part 6.3: Gigabit Ethernet Interface..................................................25
Part 6.4: USB2.0 Interface ...............................................................27
Part 6.5: USB to Serial Port..............................................................29
Part 6.6: SD Card Slot......................................................................31
Part 6.7: PS PMOD connector..........................................................32
Part 6.8: User LEDs .........................................................................33
Part 6.9: User Buttons......................................................................34
Part 7：ZYNQ Programmable Logic (PL) peripherals .............................35
Part 7.1: HDMI Interface...................................................................35
Part 7.2: EEPROM 24LC04..............................................................37
Part 7.3: Real Time Clock DS1302...................................................39
Part 7.4: Expansion Port J10............................................................40

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Part 7.5: Expansion Port J11............................................................43
Part 7.6: User LEDs .........................................................................46
Part 7.7: User Buttons......................................................................47

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The ZYNQ7000 FPGA development platform uses XILINX's Zynq7000
SOC chip XC7Z010 solution, which uses ARM+FPGA SOC technology to
integrate dual-core ARM Cortex-A9 and FPGA programmable logic on a single
chip. The Xilinx Zynq7000 series XC7Z010-1CLG400C is used as the core
processor, which has rich hardware resources and peripheral interfaces on
ARM and FPGA respectively. Adhering to the "exquisite, practical, and concise"
design concept, it is not only suitable for software verification of software
workers, but also for hardware design of hardware developers, that is, system
cooperation of software and hardware, and accelerate the development
process of the project.

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Part 1: FPGA Development Board Introduction
The AX7010 FPGA development board uses Xilinx's Zynq7000 series of
chips, model XC7Z010-1CLG400C, in a 400-pin FBGA package. The
ZYNQ7000 chip can be divided into a processor system part (PS) and a
programmable logic part (PL). On the AX7010 development board, the PS and
PL sections of the ZYNQ7000 are equipped with a wealth of external interfaces
and devices for user convenience and functional verification. In addition, the
Xilinx USB Cable downloader circuit is integrated on the AX7010 FPGA
development board, so users can download and debug the AX7010 FPGA
development board with a USB cable.
Figure 1-1 is the Schematic diagram of the entire AX7010 FPGA
development board:
Micro
SD卡座
ZYNQ7000
XC7Z010-
1CLG400C
256MByte
DDR3
50M
晶振
EEPROM
24LC04
实时时钟
电平
转换
千兆以太网
芯片
USB2.0
芯片
USB转
串口
千兆
网口
40针扩展口（34个IO口，1路5V，2路3.3V，3路GND
USB
接口
串口
接口
+5V
电源
接口
电源
开关 PMOD接口
3.3V电源
1.0V电源
1.5V电源
DDR电源
2个PS LED灯，4个PL LED灯
电源
指示灯
1.8V 电源
256MByte
DDR3
40针扩展口（34个IO口，1路5V，2路3.3V，3路GND
USB
OTG
QSPI
FLASH
Micro SD
卡槽
USB
调试口 HDMI
输出
1个复位键，2个PS按键，4个PL按键
JTAG调试
芯片
33.33M
晶振
Figure 1-1: The Schematic Diagram of the AX7010
Through this diagram, you can see the interfaces and functions that the
AX7010 FPGA Development Board contains:

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+5V power input, maximum 2A current protection
Xilinx ARM+FPGA chip Zynq-7000 XC7Z010-1CLG400C
DDR3
Two large-capacity 2Gbit (A total of 4Gbit) high-speed DDR3 SDRAMs
can be used as a cache for ZYNQ chip data or as a memory for the
operating system
QSPI FLASH
A 256Mbit QSPI FLASH memory chip can be used as a Uboot file for
ZYNQ chips, storage of system files and user data;
Gigabit Ethernet Interface
1-channel 10/100M/1000M Ethernet RJ45 interface for Ethernet data
exchange with computers or other network devices.
HDMI Input/Output Interface
The 1-channel HDMI image video input and output interface, can realize
1080P video image transmission
USB2.0 HOST Interface
1-channel USB HOST interface, to connect with external USB slave
devices, such as connecting a mouse, keyboard, USB flash drive etc.
The USB interface uses a flat USB interface (USB Type A).
USB OTG Interface
1-channel high-speed USB2.0 OTG interface for OTG communication
with PC or USB devices
USB Uart Interface
1-channel USB Uart interface for serial communication with PC or
external devices
RTC real time clock
One of RTC real time clock with battery holders, battery model CR1220.
EEPROM 24LC04
One piece of IIC interface EEPROM 24LC04

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LED Light
9 LEDs, 1 power indicator; 1 DONE configuration indicator; 2 serial
communication indicators, 1 PS control LED, 4 PL control indicators.
Button
6 buttons, 2 buttons controlled by PS, 4 buttons controlled by PL.
Clock
An on-board 33.333Mhz active crystal oscillator provides a stable clock
source for the PS system, a 50MHz active crystal oscillator that
provides additional clocking for the PL logic
2-way 40-pin expansion port
2-way 40-pin 0.1inch spacing expansion port for extending the IOs of
ZYNQ PL parts, and can be connect to various ALINX modules
(binocular camera, TFT LCD screen, high-speed AD module, etc.)
1-way 12-pin expansion port
1-way 12-pin 0.1inch spacing expansion port for extending the MIO of
ZYNQ PS system
USB JTAG Interface
One way USB JTAG port, debug and download ZYNQ system through
USB cable and onboard JTAG circuit
Micro SD card holder
1-channel Micro SD card holder, to insert SD card for stores operating
system images and file systems.
Part 2: Dimensional structure
The size of the development board is 130mm x 90mm, and the PCB is
designed with an 8-layer board. There are 4 screw positioning holes around the
board for fixing the development board. The holes diameter of the positioning
hole is 3.5mm, and the dxf structure diagram is provided in the documents.

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Figure 2-1: FPGA Size Dimension
Part 3: Power Supply
The power input voltage of the development board is DC5V, The
schematic diagram of the power supply design on the AX7010 FPGA
development board is shown in Figure 3-1
5V 电源
输入
保险丝
TLV62130R
GT
TLV62130R
GT
TPS51200
3.3V/3A
1.5V/3A
VTT
VREF
TLV62130R
GT
电源开关
1.8V/3A
CN1
F1
SW1
U26
U25
U24
U32
1.0V/3A
TLV62130R
GT
U23
SPX3819M5
-3-3
VCCIO/0.5A
Figure 3-1: Power Supply Schematic

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The development board is powered by +5V, and is converted into +3.3V,
+1.5V, +1.8V, +1.0V four-way power supply through four DC/DC power supply
chip TLV62130RGT. Each output current can be up to 3A. VCCIO power is
generated by one LDO SPX3819M5-3-3, and VCCIO is mainly used to power
the BANK35 of ZYNQ. By replacing other LDO chips, the BANK35's IO can be
adapted to different voltage standards. VTT and VREF Voltage required by
DDR3 are generated by 1.5V via TI's TPS51200. The functions of each power
distribution are shown in the following table below:
Power Supply
Function
+1.0V
ZYNQ Core Voltage
+1.5V
DDR3, ZYNQ Bank502
+1.8V
ZYNQ auxiliary voltage, ZYNQ PLL, ZYNQ BANK501, VCCIO,
Ethernet, USB 2.0
+3.3V
ZYNQ VCCIO, Gigabit Ethernet, Serial Port, HDMI, RTC,
FLASH,EEPROM SD Card
VREF, VTT
DDR3
VCCIO
ZYNQ Bank35
Because the power supply of the ZYNQ FPGA has the power-on
sequence requirements, in the circuit design, we have designed according to
the power requirements of the chip. The power-on sequence is
+1.0V->+1.8V->+1.5 V->+3.3V->VCCIO, circuit design to ensure the normal
operation of the chip. Figure 3-2 shows the circuit design of the power supply: