Alinx ZYNQ UltraScale+ User manual

ZYNQ UltraScale+
FPGA Development Board
AXU9EG
User Manual

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Version Record
Version
Date
Release By
Description
Rev 1.1
2021-07-21
Rachel Zhou
First Release

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Table of Contents
Version Record.......................................................................................................2
Part 1: FPGA Development Board Introduction............................................... 7
Part 2: ACU9EG Core Board.............................................................................12
Part 2.1: ACU9EG Core Board Introduction...........................................12
Part 2.2: ZYNQ Chip...................................................................................13
Part 2.3: DDR4 DRAM............................................................................... 15
Part 2.4: QSPI Flash...................................................................................22
Part 2.5: eMMC Flash.................................................................................24
Part 2.6: Clock configuration..................................................................... 25
Part 2.7: Power Supply...............................................................................28
Part 2.8: ACU9EG Core Board Size Dimension....................................30
Part 2.9: Board to Board Connectors pin assignment..........................30
Part 3: Carrier Board...........................................................................................39
Part 3.1: Carrier Board Introduction.........................................................39
Part 3.2: M.2 Interface................................................................................39
Part 3.3: DP Interface................................................................................. 40
Part 3.4: USB3.0 Interface.........................................................................42
Part 3.5: Gigabit Ethernet Interface......................................................... 43
Part 3.6: USB to Serial Port.......................................................................46
Part 3.7: SD Card Slot Interface...............................................................47
Part 3.8: SFP Interface...............................................................................48
Part 3.9: CAN Communication Interface.................................................49
Part 3.10: 485 Communication Interface................................................ 50
Part 3.11: MIPI Camera Interface.............................................................51
Part 3.12: FMC Interface............................................................................52
Part 3.13: 40-Pin Expansion Headers..................................................... 57
Part 3.14: JTAG Debug Port......................................................................58

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Part 3.15: Real-time Clock.........................................................................59
Part 3.16: EEPROM and Temperature Sensor......................................60
Part 3.17: User LEDs..................................................................................61
Part 3.18: Keys............................................................................................ 62
Part 3.19: DIP Switch Configuration........................................................ 62
Part 3.20: Power Supply............................................................................ 63
Part 3.21: ALINX Customized Fan........................................................... 64
Part 3.22: Carrier Board Size Dimension................................................66

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This MPSoCs FPGA development platform adopts the core board + carrier
board mode, which is convenient for users to use the core board for secondary
development. The core board uses XILINX Zynq UltraScale+ EG chip ZU9EV
solution, uses Processing System(PS)+Programmable Logic(PL) technology to
integrate dual-core ARM ARM Cortex-A53 and FPGA programmable logic on a
single chip. In addition, the PS side of the core board has 4 pieces of 1GB
high-speed DDR4 SDRAM chips, 1 piece of 8GB eMMC memory chip and 1
piece of 256Mb QSPI FLASH chip; the PL side of the core board has 2 pieces
of 1GB DDR4 SDRAM chip
In the design of carrier board, we have extended a wealth of interfaces for
users, such as 1 FMC LPC interface, 1 SATA M.2 interface, 1 DP interface, 1
PCIe x 2.0, 4 USB 3.0 Interface, 2 Gigabit Ethernet interfaces, 1 HDMI Output,
1 HDMI Input, 2 Uart, 1 SD card slot, 2-Channel CAN bus interfaces,
2-Channel RS485 bus interfaces, 1 MIPI Camera Interface. It meets users'
requirements for high-speed data exchange, data storage, Video transmission
processing, deep learning, artificial intelligence and industrial control. It is a
"professional" ZYNQ development platform. For high-speed data transmission
and exchange, pre-verification and post-application of data processing is
possible. This product is very suitable for students, engineers and other groups
engaged in MPSoCs development.

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Part 1: FPGA Development Board Introduction
The entire structure of the AXU9EG PGA development board is inherited
from our consistent core board + carrier board model. A high-speed inter-board
connector is used between the core board and the carrier board.
The core board is mainly composed of the smallest system of ZU9EG +
6 DDR4 + eMMC + 2 QSPI FLASH, the main FPGA chip is Xilinx's Zynq
UltraScale+ MPSoCs family chip, the model number is XCZU9EG-2FFVB1156I.
ZU9EG chip can be divided into processor system part Processor System (PS)
and programmable logic part Programmable Logic (PL). On the PS side and PL
side of the ZU9EV chip, there are 4 DDR4 and 2 DDR4 respectively, each with
a capacity of up to 1GB, which enables the ARM system and FPGA system to
independently process and store data. The 8GB eMMC FLASH memory chip
and two 256Mb QSPI FLASH which are on the PS side, used to statically store
the operating system, file system and user data of MPSoCs.
The AXU9EG carrier board expands its rich peripheral interface, including
1 M.2 interface, 1 DP output interface, 4 USB 3.0 Interface, 2 Gigabit Ethernet
interfaces, 2 SFP Interfaces, 2 SATA Interfaces, 2 UART, 1 SD card slot, 1 FMC
Interface, 2-Channel CAN bus interfaces, 2-Channel RS485 bus interfaces, 1
MIPI Camera Interface, 40-pin expansion ports and some keys and LEDs.
The following figure shows the structure of the entire development system:

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Figure 1-1-1: The Schematic Diagram of the AXU9EG
Through this diagram, you can see the interfaces and functions that the
AXU9EG FPGA Development Board contains:
ZU9EG core board
It consists of ZU9EV +4GB DDR4（PS）+2GB DDR4（PL）+8GB eMMC
FLASH + 512Mb QSPI FLASH, and there are 2 crystal oscillators to
provide the clock, a single-ended 33.3333MHz crystal oscillator for the
PS system, and a differential 200MHz crystal oscillator for the PL logic
DDR reference clock.
M.2 Interface
1 PCIEx1 standard M.2 interface, used to connect M.2 SSD solid state
drives, with a communication speed of up to 6Gbps.
DP Output Interface

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1 standard Display Port output display interface, used for video image
display. Supports up to 4K@30Hz or 1080P@60Hz output
USB 3.0 Interface
4-channel USB3.0 HOST interface, USB interface type is TYPE A. Used
to connect external USB peripherals, such as connecting a mouse,
keyboard, U disk, etc.
Gigabit Ethernet Interface
2-Channel 10/100M/1000M Ethernet RJ45 interface for Ethernet data
exchange with computers or other network devices. The network
interface chip uses Micrel's KSZ9031 industrial grade GPHY chip.
USB Uart Interface
2-Channel Uart to USB interfaces for communication with the computer,
for user debugging. The serial port chip adopts the USB-UAR chip of
Silicon Labs CP2102GM, and the USB interface adopts the MINI USB
interface.
2-Channel SFP Fiber Interface
The two high-speed transceivers of the GTH transceiver are connected
to the transmitting and receiving of two optical modules, realizing two
high-speed optical fiber communication interfaces. The transmitting and
sending speed of each optical fiber data communication is as high as
12.5Gb/s.
SD Card Slot Interface
1 Micro SD card holder, used to store operating system image and file
system.
FMC Expansion Interface
1 standard FMC LPC expansion port, which can be connected to
various FMC modules of XILINX or ALINX (HDMI input and output
modules, binocular camera modules, high-speed AD modules, etc.).
CAN Communication Interface

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Two-way CAN bus interface, using TI's SN65HVD232 chip, the
interface uses 4Pin green terminal blocks.
485 Communication Interface
Two-way 485 communication interface, using MAX3485 chip of MAXIM
company. The interface uses 6Pin green terminal blocks.
MIPI Interface
2 Lane MIPI camera input interfaces, used to connect MIPI camera
module (AN5641).
40-pin Expansion Header
The 40-pin 2.54mm pitch expansion port use for external ALINX
modules (binocular camera, TFT LCD screen, high-speed AD module,
etc.). The expansion port includes 1 channel of 5V power supply, 2
channels of 3.3V power supply, 3 channels of ground, and 34 channels
of IO port.
JTAG debug port
A 10-pin 0.1 spacing standard JTAG ports for FPGA program download
and debugging. Users can debug and download the ZU4EV system
through the XILINX downloader.
Temperature and humidity sensor chip LM75
On-board temperature and humidity sensor chip LM75, used to detect
the temperature and humidity of the surrounding environment around
the FPGA development board
EEPROM
One EEPROM 24LC04 with I2C interface
Real Time Clock (RTC)
1 built-in RTC real-time clock
LED Lights
5 LEDs, include 1 LED on the core board, 4 LEDs on the carrier board.
There are 1 power indicator and on the core board. There are 1 power

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indicator,1 DONE Configuration indicator and 2 user indicators on the
carrier board.
KEYs
3 KEYs, include 1 Rest KEY and 2 User KEYs.

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Part 2: ACU9EG Core Board
Part 2.1: ACU9EG Core Board Introduction
ACU9EG (core board model, the same below) FPGA core board, ZYNQ
chip is based on XCZU9EG-2FFVB1156I of XILINX company Zynq UltraScale+
MPSoCs EG Family.
This core board uses 6 Micron DDR4 chips MT40A512M16GE, of which 4
DDR4 chips are mounted on the PS side to form a 64-bit data bus bandwidth
and 4GB capacity. 2 DDR4 chip is mounted on the PL end, which is a 32-bit
data bus width and a capacity of 2GB. The highest operating speed of DDR4
SDRAM on the PS side can reach 1200MHz (data rate 2400Mbps), and the
highest operating speed of DDR4 SDRAM on the PL side can reach 1200MHz
(data rate 2400Mbps). In addition, two 256MBit QSPI FLASH and an 8GB
eMMC FLASH chip are also integrated on the core board to start storage
configuration and system files.
In order to connect with the carrier board, the four board-to-board
connectors of this core board expand the PS side USB2.0 interface, Gigabit
Ethernet interface, SD card interface and other remaining MIO ports; also
expand 4 pairs of PS MGT high-speed transceiver interface; and 16 GTH
transceivers and almost all IO ports on the PL side (HP I/O: 96, HD I/O: 84).
The wiring between the XCZU9EG chip and the interface has been processed
with equal length and differential, and the core board size is only 3.15*2.36
(inch), which is very suitable for secondary development.

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Figure 2-1-1: ACU9EG Core Board (Front View)
Part 2.2: ZYNQ Chip
The FPGA core board ACU9EG uses Xilinx's Zynq UltraScale+ MPSoCs
EG family chip, module XCZU9EG-2FFVB1156I. The PS system of the ZU9EG
chip integrates 4 ARM Cortex™-A53 processors with a speed of up to 1.3Ghz
and supports Level 2 Cache; it also contains 2 Cortex-R5 processors with a
speed of up to 533Mhz
The ZU9EG chip supports 32-bit or 64-bit DDR4, LPDDR4, DDR3, DDR3L,
LPDDR3 memory chips, with rich high-speed interfaces on the PS side such as
PCIE Gen2, USB3.0, SATA 3.1, DisplayPort; it also supports USB2.0, Gigabit
Ethernet, SD/SDIO, I2C, CAN, UART, GPIO and other interfaces. The PL end
contains a wealth of programmable logic units, DSP and internal RAM. .
Figure 2-2-1 detailed the Overall Block Diagram of the ZU9EG Chip.

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Figure 2-2-1: Overall Block Diagram of the ZYNQ ZU9EG Chip
The main parameters of the PS system part are as follows:
ARM quad-core Cortex ™-A53 processor, speed up to 1.3GHz, each
CPU 32KB level 1 instruction and data cache, 1MB level 2 cache,
shared by 2 CPUs
ARM dual-core Cortex-R5 processor, speed up to 533MHz, each CPU
32KB level 1 instruction and data cache, and 128K tightly coupled
memory.
External storage interface, support 32/64bit DDR4/3/3L, LPDDR4/3
interface
Static storage interface, support NAND, 2xQuad-SPI FLASH.
High-speed connection interface, support PCIe Gen2 x 4, 2 x USB3.0,
Sata 3.1, Display Port, 4 x Tri-mode, Gigabit Ethernet

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Common connection interfaces: 2 x USB2.0, 2 x SD/SDIO, 2 x UART,
2 x CAN 2.0B, 2 x I2C, 2 x SPI, 4 x 32b GPIO
Power management: Support the four-part division of power supply
Full/Low/PL/Battery
Encryption algorithm: support RSA, AES and SHA.
System monitoring: 10-bit 1Mbps AD sampling for temperature and
voltage detection.
The main parameters of the PL logic part are as follows:
Logic Cells: 600K
CLB Flip-flops: 548K
Look-up-tables (LUTs): 274K
 Block RAM : 32.1Mb
Clock Management Units (CMTs): 4
 DSP Slices: 2520
GTH 16.3Gb/s Transceiver: 24
XCZU9EG-2FFVB1156I chip speed grade is -2, industrial grade, package
is FFVB1156.
Part 2.3: DDR4 DRAM
The ACU9EG core board is equipped with 6 Micron (Micron) 1GB DDR4
chips, model MT40A512M16LY-062E, of which 4 DDR4 chips are mounted on
the PS side to form a 64-bit data bus bandwidth and 4GB capacity. Two DDR4
chip is mounted on the PL end, which is a 32-bit data bus width and a capacity
of 2GB. The maximum operating speed of the DDR4 SDRAM on the PS side
can reach 1200MHz (data rate 2400Mbps), and the 4 DDR4 storage systems
are directly connected to the memory interface of the PS BANK504. The

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highest operating speed of the DDR4 SDRAM on the PL side can reach
1200MHz (data rate 2400Mbps), and two piece of DDR4 is connected to the
BANK64,65 interface of the FPGA. The specific configuration of DDR4 SDRAM
is shown in Table 2-3-1 below:
Bit Number
Chip Model
Capacity
Factory
U4,U5,U6,U7
MT40A512M16LY-062E
512M x 16bit
Micron
Table 2-3-1: DDR4 SDRAM Configuration
The hardware design of DDR4 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR4.
The hardware connection of DDR4 SDRAM on the PS Side is shown in
Figure 2-3-1:
Figure 2-3-1: DDR3 DRAM schematic diagram
The hardware connection of DDR4 SDRAM on the Pl Side is shown in
Figure 2-3-2:

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Figure 2-3-2: DDR4 DRAM schematic diagram
PS Side DDR4 DRAM pin assignment:
Signal Name
Pin Name
Pin Number
PS_DDR4_DQS0_N
PS_DDR_DQS_N0_504
AN19
PS_DDR4_DQS0_P
PS_DDR_DQS_P0_504
AN18
PS_DDR4_DQS1_N
PS_DDR_DQS_N1_504
AN22
PS_DDR4_DQS1_P
PS_DDR_DQS_P1_504
AN21
PS_DDR4_DQS2_N
PS_DDR_DQS_N2_504
AJ19
PS_DDR4_DQS2_P
PS_DDR_DQS_P2_504
AH19
PS_DDR4_DQS3_N
PS_DDR_DQS_N3_504
AH23
PS_DDR4_DQS3_P
PS_DDR_DQS_P3_504
AH22
PS_DDR4_DQS4_N
PS_DDR_DQS_N4_504
AH29
PS_DDR4_DQS4_P
PS_DDR_DQS_P4_504
AH28
PS_DDR4_DQS5_N
PS_DDR_DQS_N5_504
AE29
PS_DDR4_DQS5_P
PS_DDR_DQS_P5_504
AE28
PS_DDR4_DQS6_N
PS_DDR_DQS_N6_504
AK32
PS_DDR4_DQS6_P
PS_DDR_DQS_P6_504
AJ32
PS_DDR4_DQS7_N
PS_DDR_DQS_N7_504
AE33
PS_DDR4_DQS7_P
PS_DDR_DQS_P7_504
AE32
PS_DDR4_DQ0
PS_DDR_DQ0_504
AP20
PS_DDR4_DQ1
PS_DDR_DQ1_504
AP18

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PS_DDR4_DQ2
PS_DDR_DQ2_504
AP19
PS_DDR4_DQ3
PS_DDR_DQ3_504
AP17
PS_DDR4_DQ4
PS_DDR_DQ4_504
AM20
PS_DDR4_DQ5
PS_DDR_DQ5_504
AM19
PS_DDR4_DQ6
PS_DDR_DQ6_504
AM18
PS_DDR4_DQ7
PS_DDR_DQ7_504
AL18
PS_DDR4_DQ8
PS_DDR_DQ8_504
AP22
PS_DDR4_DQ9
PS_DDR_DQ9_504
AP21
PS_DDR4_DQ10
PS_DDR_DQ10_504
AP24
PS_DDR4_DQ11
PS_DDR_DQ11_504
AN23
PS_DDR4_DQ12
PS_DDR_DQ12_504
AL21
PS_DDR4_DQ13
PS_DDR_DQ13_504
AL22
PS_DDR4_DQ14
PS_DDR_DQ14_504
AM23
PS_DDR4_DQ15
PS_DDR_DQ15_504
AL23
PS_DDR4_DQ16
PS_DDR_DQ16_504
AL20
PS_DDR4_DQ17
PS_DDR_DQ17_504
AK20
PS_DDR4_DQ18
PS_DDR_DQ18_504
AJ20
PS_DDR4_DQ19
PS_DDR_DQ19_504
AK18
PS_DDR4_DQ20
PS_DDR_DQ20_504
AG20
PS_DDR4_DQ21
PS_DDR_DQ21_504
AH18
PS_DDR4_DQ22
PS_DDR_DQ22_504
AG19
PS_DDR4_DQ23
PS_DDR_DQ23_504
AG18
PS_DDR4_DQ24
PS_DDR_DQ24_504
AG21
PS_DDR4_DQ25
PS_DDR_DQ25_504
AH21
PS_DDR4_DQ26
PS_DDR_DQ26_504
AG24
PS_DDR4_DQ27
PS_DDR_DQ27_504
AG23
PS_DDR4_DQ28
PS_DDR_DQ28_504
AK22
PS_DDR4_DQ29
PS_DDR_DQ29_504
AJ21
PS_DDR4_DQ30
PS_DDR_DQ30_504
AJ22
PS_DDR4_DQ31
PS_DDR_DQ31_504
AK23
PS_DDR4_DQ32
PS_DDR_DQ32_504
AG31
PS_DDR4_DQ33
PS_DDR_DQ33_504
AG30
PS_DDR4_DQ34
PS_DDR_DQ34_504
AG29
PS_DDR4_DQ35
PS_DDR_DQ35_504
AG28
PS_DDR4_DQ36
PS_DDR_DQ36_504
AJ30
PS_DDR4_DQ37
PS_DDR_DQ37_504
AK29

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PS_DDR4_DQ38
PS_DDR_DQ38_504
AK30
PS_DDR4_DQ39
PS_DDR_DQ39_504
AJ29
PS_DDR4_DQ40
PS_DDR_DQ40_504
AE27
PS_DDR4_DQ41
PS_DDR_DQ41_504
AF28
PS_DDR4_DQ42
PS_DDR_DQ42_504
AF30
PS_DDR4_DQ43
PS_DDR_DQ43_504
AF31
PS_DDR4_DQ44
PS_DDR_DQ44_504
AD28
PS_DDR4_DQ45
PS_DDR_DQ45_504
AD27
PS_DDR4_DQ46
PS_DDR_DQ46_504
AD29
PS_DDR4_DQ47
PS_DDR_DQ47_504
AD30
PS_DDR4_DQ48
PS_DDR_DQ48_504
AH33
PS_DDR4_DQ49
PS_DDR_DQ49_504
AJ34
PS_DDR4_DQ50
PS_DDR_DQ50_504
AH34
PS_DDR4_DQ51
PS_DDR_DQ51_504
AH32
PS_DDR4_DQ52
PS_DDR_DQ52_504
AK34
PS_DDR4_DQ53
PS_DDR_DQ53_504
AK33
PS_DDR4_DQ54
PS_DDR_DQ54_504
AL32
PS_DDR4_DQ55
PS_DDR_DQ55_504
AL31
PS_DDR4_DQ56
PS_DDR_DQ56_504
AG33
PS_DDR4_DQ57
PS_DDR_DQ57_504
AG34
PS_DDR4_DQ58
PS_DDR_DQ58_504
AF32
PS_DDR4_DQ59
PS_DDR_DQ59_504
AF33
PS_DDR4_DQ60
PS_DDR_DQ60_504
AD31
PS_DDR4_DQ61
PS_DDR_DQ61_504
AD32
PS_DDR4_DQ62
PS_DDR_DQ62_504
AD34
PS_DDR4_DQ63
PS_DDR_DQ63_504
AD33
PS_DDR4_DM0
PS_DDR_DM0_504
AG20
PS_DDR4_DM1
PS_DDR_DM0_504
AN17
PS_DDR4_DM2
PS_DDR_DM1_504
AM21
PS_DDR4_DM3
PS_DDR_DM2_504
AK19
PS_DDR4_DM4
PS_DDR_DM3_504
AH24
PS_DDR4_DM5
PS_DDR_DM4_504
AH31
PS_DDR4_DM6
PS_DDR_DM5_504
AE30
PS_DDR4_DM7
PS_DDR_DM6_504
AJ31
PS_DDR4_A0
PS_DDR_A0_504
AP29
PS_DDR4_A1
PS_DDR_A1_504
AP30

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PS_DDR4_A2
PS_DDR_A2_504
AP26
PS_DDR4_A3
PS_DDR_A3_504
AP27
PS_DDR4_A4
PS_DDR_A4_504
AP25
PS_DDR4_A5
PS_DDR_A5_504
AN24
PS_DDR4_A6
PS_DDR_A6_504
AM29
PS_DDR4_A7
PS_DDR_A7_504
AM28
PS_DDR4_A8
PS_DDR_A8_504
AM26
PS_DDR4_A9
PS_DDR_A9_504
AM25
PS_DDR4_A10
PS_DDR_A10_504
AL28
PS_DDR4_A11
PS_DDR_A11_504
AK27
PS_DDR4_A12
PS_DDR_A12_504
AJ25
PS_DDR4_A13
PS_DDR_A13_504
AL25
PS_DDR4_WE_B
PS_DDR_A14_504
AK25
PS_DDR4_CAS_B
PS_DDR_A15_504
AK24
PS_DDR4_RAS_B
PS_DDR_A16_504
AM24
PS_DDR4_ACT_B
PS_DDR_ACT_N_504
AG25
PS_DDR4_ALERT_B
PS_DDR_ALERT_N_504
AF22
PS_DDR4_BA0
PS_DDR_BA0_504
AH26
PS_DDR4_BA1
PS_DDR_BA1_504
AG26
PS_DDR4_BG0
PS_DDR_BG0_504
AK28
PS_DDR4_CS0_B
PS_DDR_CS_N0_504
AN28
PS_DDR4_ODT0
PS_DDR_ODT0_504
AM30
PS_DDR4_PARITY
PS_DDR_PARITY_504
AF20
PS_DDR4_RESET_B
PS_DDR_RST_N_504
AF21
PS_DDR4_CLK0_P
PS_DDR_CK0_504
AN26
PS_DDR4_CLK0_N
PS_DDR_CK_N0_504
AN27
PS_DDR4_CKE0
PS_DDR_CKE0_504
AN29
PL Side DDR4 DRAM pin assignment:
Signal Name
Pin Name
Pin Number
PL_DDR4_DQS0_N
IO_L22N_T3U_N7_DBC_AD0N_65
AF1
PL_DDR4_DQS0_P
IO_L22P_T3U_N6_DBC_AD0P_65
AJ1
PL_DDR4_DQS1_N
IO_L16N_T2U_N7_QBC_AD3N_65
AH1
PL_DDR4_DQS1_P
IO_L16P_T2U_N6_QBC_AD3P_65
AJ5
PL_DDR4_DQS2_N
IO_L10N_T1U_N7_QBC_AD4N_65
AJ6