AMD M56 User manual

M56
Register Reference Guide
Technical Reference Manual
Rev 0.03o
P/N: RRG-216M56-03oOEM
© 2007 Advanced Micro Devices, Inc.

Trademarks
AMD, the AMD Arrow logo, Athlon, and combinations thereof, ATI, ATI logo, Radeon, and Crossfire are trademarks of Advanced Micro Devices,
Inc.
Microsoft and Windows are registered trademarks of Microsoft Corporation.
Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Disclaimer
The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or
warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications
and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel, or otherwise, to any intellectual
property rights are granted by this publication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no liability
whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of
merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or
in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a situation
where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its
products at any time without notice.
© 2007 Advanced Micro Devices, Inc. All rights reserved.

© 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual
Proprietary TOC-1
Table of Contents
Chapter 1: Introduction
1.1 About this Manual .................................................................................................................................................................................1-1
1.2 Nomenclature and Conventions ..........................................................................................................................................................1-1
1.2.1 Numeric Representations .....................................................................................................................................................1-1
1.2.2 Register Description..............................................................................................................................................................1-1
Chapter 2: Registers Description
2.1 Memory Controller Registers ..............................................................................................................................................................2-2
2.2 Bus Interface Registers .......................................................................................................................................................................2-58
2.3 PCIE Registers ...................................................................................................................................................................................2-107
2.4 VIP/I2C Registers..............................................................................................................................................................................2-116
2.4.1 I2C Registers ......................................................................................................................................................................2-116
2.4.2 Video Interface Port Host Port Registers ......................................................................................................................2-119
2.4.3 Capture Registers...............................................................................................................................................................2-126
2.4.4 VIP Host Port DMA Registers ........................................................................................................................................2-136
2.4.5 GPIO Registers ..................................................................................................................................................................2-143
2.4.6 VIP Miscellaneous Registers...........................................................................................................................................2-147
2.5 Clock Generator Registers ...............................................................................................................................................................2-155
2.6 VGA Registers ...................................................................................................................................................................................2-165
2.6.1 VGA Control/Status Registers ........................................................................................................................................2-165
2.6.2 VGA DAC Control Registers..........................................................................................................................................2-168
2.6.3 VGA Sequencer Registers ...............................................................................................................................................2-169
2.6.4 VGA CRT Registers .........................................................................................................................................................2-171
2.6.5 VGA Graphics Registers..................................................................................................................................................2-178
2.6.6 VGA Attribute Registers ..................................................................................................................................................2-181
2.6.7 VGA Miscellaneous Registers ........................................................................................................................................2-186
2.7 Display Controller Registers............................................................................................................................................................2-198
2.7.1 Primary Display Graphics Controller Registers...........................................................................................................2-198
2.7.2 Primary Display Video Overlay Control Registers .....................................................................................................2-203
2.7.3 Primary Display Video Overlay Transform Registers ................................................................................................2-206
2.7.4 Primary Display Video Overlay Gamma Correction Registers.................................................................................2-209
2.7.5 Primary Display Graphics and Overlay Blending Registers......................................................................................2-213
2.7.6 Primary Display Color Matrix Transform Registers ...................................................................................................2-217
2.7.7 Primary Display Subsampling Registers .......................................................................................................................2-221
2.7.8 Primary Display Hardware Cursor Registers................................................................................................................2-222
2.7.9 Primary Display Hardware Icon Registers....................................................................................................................2-224
2.7.10 Display Look Up Table Control Registers ....................................................................................................................2-226
2.7.11 Display Controller Look Up Table A Registers...........................................................................................................2-228
2.7.12 Secondary Display Graphics Control Registers ...........................................................................................................2-231
2.7.13 Secondary Display Video Overlay Control Registers.................................................................................................2-236
2.7.14 Secondary Display Video Overlay Transform Registers............................................................................................2-239
2.7.15 Secondary Display Video Overlay Gamma Correction Registers ............................................................................2-242
2.7.16 Secondary Display Graphics and Overlay Blending Registers .................................................................................2-246
2.7.17 Secondary Display Color Matrix Transform Registers...............................................................................................2-250
2.7.18 Secondary Display Subsampling Registers...................................................................................................................2-254

M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc.
TOC-2 Proprietary
2.7.19 Secondary Display Hardware Cursor Registers ...........................................................................................................2-255
2.7.20 Secondary Display Hardware Icon Registers ...............................................................................................................2-257
2.7.21 Display Controller Look Up Table B Registers ...........................................................................................................2-259
2.7.22 Display Controller CRC Registers..................................................................................................................................2-262
2.7.23 Display/Memory Interface Control and Status registers.............................................................................................2-264
2.7.24 MCIF Control Registers ...................................................................................................................................................2-265
2.7.25 Display Controller to Line Buffer Control Registers ..................................................................................................2-266
2.8 CRTC Registers .................................................................................................................................................................................2-267
2.9 Display Output Registers..................................................................................................................................................................2-295
2.9.1 Display Output Miscellaneous Registers.......................................................................................................................2-338
2.10 LVDS Registers ...............................................................................................................................................................................2-340
Appendix A: Cross Referenced Index
A.1 Quick Cross-Reference Index............................................................................................................................................................ A-1
A.2 Configuration Registers Sorted by Name ........................................................................................................................................ A-2
A.3 Configuration Registers Sorted by Address .................................................................................................................................... A-5
A.4 Clock Registers Sorted by Name ...................................................................................................................................................... A-8
A.5 Clock Registers Sorted by Address .................................................................................................................................................. A-9
A.6 Display Registers Stored by Name ................................................................................................................................................. A-10
A.7 Display Registers Stored by Address ............................................................................................................................................. A-23
A.8 Host Interface Decode Space Registers Sorted by Name ........................................................................................................... A-36
A.9 Memory Controller Registers Sorted By Name............................................................................................................................ A-37
A.10 Memory Controller Registers Sorted By Address ..................................................................................................................... A-41
A.11 PCIE Registers Sorted By Name .................................................................................................................................................. A-45
A.12 PCIE Registers Sorted By Address .............................................................................................................................................. A-49
A.13 VIP Registers Sorted By Name..................................................................................................................................................... A-53
A.14 VIP Registers Sorted By Address................................................................................................................................................. A-56
A.15 VGA ATTR Registers Sorted By Name...................................................................................................................................... A-59
A.16 VGA CRT Registers Sorted By Name......................................................................................................................................... A-60
A.17 VGA GRPH Registers Sorted By Name ..................................................................................................................................... A-61
A.18 VGA SEQ Registers Sorted By Name......................................................................................................................................... A-62
A.19 All Registers Sorted by Name ....................................................................................................................................................... A-63
Appendix B: Revision History

© 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual
Proprietary 1-1
Chapter 1
Introduction
1.1 About this Manual
This manual serves as a register reference guide to the M56 graphics controller.
•Chapter 1 outlines the notations and conventions used throughout this manual.
•Chapter 2 provides a detailed description of the registers.
•Appendix A provides several cross-referenced lists (sorted by Register Name and Address).
1.2 Nomenclature and Conventions
1.2.1 Numeric Representations
•Hexadecimal numbers are appended with “h” whenever there is a risk of ambiguity. Other numbers are assumed to be
in decimal.
•Registers (or fields) of identical function are sometimes indicated by a single expression in which the part of the
signal name that differs is enclosed in [ ] brackets. For example, the eight Host Data registers — HOST_DATA0
through to HOST_DATA7 — are represented by the single expression HOST_DATA[7:0].
1.2.2 Register Description
All registers in this document are described with the format of the sample table below. All offsets are in hexadecimal
notation, while programmed bits are in either binomial or hexadecimal notation.
DST_HEIGHT_WIDTH_8 - W - 32 bits - [MMReg:0x158C]
Field Name Bits Default Description
DST_WIDTH
(mirror bits 0:7 of DST_WIDTH:DST_WIDTH)
23:16 0x0 Destination Width Note: This is an initiator register. Y is incremented
at end of blit. Write 15: 0 to E2_DST_X, Write 31: 16 to
E2_DST_WIDTH, then signal blit_start. E2_DST_Y = E2_DEST_Y
(+/-) E2_DST_HEIGHT as function of direction after blit is complete
DST_HEIGHT
(mirror bits 0:7 of DST_HEIGHT:DST_HEIGHT)
31:24 0x0 Destination Height Write 15: 0 to E2_DST_Y, Write 31: 16 to
E2_DST_HEIGHT
[ W] (Reserved) 15: 0 DST_WIDTH 23: 16 Destination width: range 0 to 256 (ZERO extent)

M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc.
1-2 Proprietary
Nomenclature and Conventions
Table 1-1 Register description table notation
Register Information Example
Register name DST_HEIGHT_WIDTH_8
Read / Write capability
R = Readable
W = Writable
RW = Readable and Writable
W
Register size 32 bits
Register address(es)* MMReg:0x158C
Field name DST_WIDTH
Field position/size 23:16
Field default value 0x0
Field description Destination....complete
Field mirror information (mirror bits 0:7 of DST_WIDTH:DST_WIDTH)
Brief register description [ W] (Reserved) 15: 0 DST_WIDTH 23: 16 Destination width: range 0 to
256 (ZERO extent)
* Note:
There may be more than one address; the convention used is as follows:
[aperName:offset] - single mapping, to one aperture/decode and one offset
[aperName1, aperName2, …, aperNameN:offset] - multiple mappings to different apertures/decodes but same offset
[aperName:startOffset-endOffset] - mapped to an offset range in the same aperture/decode

© 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual
Proprietary 2-1
Chapter 2
Registers Description
To link to a topic of interest, use the following list of hypertext linked cross references:
“Memory Controller Registers” on page 2-2
“Bus Interface Registers” on page 2-58
“PCIE Registers” on page 2-107
“VIP/I2C Registers” on page 2-116
“Clock Generator Registers” on page 2-155
“VGA Registers” on page 2-165
“Display Controller Registers” on page 2-198
“CRTC Registers” on page 2-267
“Display Output Registers” on page 2-295
“LVDS Registers” on page 2-340

M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc.
2-2 Proprietary
Memory Controller Registers
2.1 Memory Controller Registers
NOTE: Channels A0, A1, B0 and B1 are also known as Channels A, B, C and D respectively.
MC_IND_INDEX - RW - 32 bits - MCDEC:0x70
Field Name Bits Default Description
MC_IND_ADDR 15:0 0x0
MC_IND_SEQ_RBS_0 16 0x0 0=Do not access sequencer+gfx return bus block 0 (channels
A0+A1)
1=Access sequencer+gfx return bus block 0 (channels A0+A1)
MC_IND_SEQ_RBS_1 17 0x0 0=Do not access sequencer+gfx return bus block 1 (channels
B0+B1)
1=Access sequencer+gfx return bus block 1 (channels B0+B1)
MC_IND_SEQ_RBS_2 18 0x0 0=Reserved - do not program
1=Reserved - do not program
MC_IND_SEQ_RBS_3 19 0x0 0=Reserved - do not program
1=Reserved - do not program
MC_IND_AIC_RBS 20 0x0 0=Do not access aic+cpvf and glb return bus block
1=Access aic+cpvf and glb return bus block
MC_IND_CITF_ARB0 21 0x0 0=Do not access client MCT interface+arbitration block
1=Access client MCT interface+arbitration block
MC_IND_CITF_ARB1 22 0x0 0=Do not access client MCB interface+arbitration block
1=Access client MCB interface+arbitration block
MC_IND_WR_EN 23 0x0 0=Disable write capability (read only)
1=Enable write capability
MC_IND_RD_INV 24 0x0 0=Do not invert data on return bus
1=Invert data on return bus
Within MC_IND_INDEX, there are 16 bits of address, and 7 bits of mask. Each of the 7 bits of mask designates a physically distinct group of reg-
isters (in separate physical tile). One bit each for the four sequencer blocks (SQ), the AC block, MCT and MCB. A write may be done in a broad-
cast fashion, simultaneously programming all registers with the same indirect address in the 7 different blocks. The indirect address space is
semantically non-overlapping, such that writes can typically be done with all mask bits being set to “on”. Reads tend to be from single registers, so
only one mask bit is set. If more than one mask bit is set, the resulting return data will be the bitwise logical OR of all matching registers. If the
MC_IND_RD_INV bit is set, with a single read mask, the return data will be bitwise inverted; if the bit is set with more than one mask bit set, the
inverted data will then return the bitwise logical NAND of all matching registers. Thus this “collect” read could be useful for polling status bits with
either a logical and or an or.
MC_IND_DATA - RW - 32 bits - MCDEC:0x74
Field Name Bits Default Description
MC_IND_DATA 31:0 0x0
This is the Indirect memory controller Data registers – aka the indirect data register
MC_STATUS - RW - 8 bits - MCIND:0x0
Field Name Bits Default Description
MEM_PWRUP_COMPL (R) 0 0x0 0=SDRAM Init in Process
1=Ready
MC_IDLE (R) 1 0x0 Indicates that there are no pending or in-process requests in the MC
0=Not Idle
1=Idle
Status register for memory controller

Memory Controller Registers
© 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual
Proprietary 2-3
MC_TIMING_CNTL_2 - RW - 32 bits - MCIND:0x3
Field Name Bits Default Description
MEM_REFRESH_RATE 23:16 0x0
Unused and invalid
MC_FB_LOCATION - RW - 32 bits - MCIND:0x4
Field Name Bits Default Description
MC_FB_START 15:0 0x0 NOTE: Bits 0:7 of this field are hardwired to ZERO.
MC_FB_TOP 31:16 0xff NOTE: Bits 0:7 of this field are hardwired to ONE.
This register defines the location of the frame buffer in the internal address space. The internal address space has 32 address bits. Minimum
Frame buffer size for M56 is 16 MB, and the start location is required to be on a 16 MB boundary. Therefore START(23:0) must be 0x000000 and
TOP(23:0) must be 0xFFFFFF. Only the 16 MSBs of each are loaded in the register.
MC_AGP_LOCATION - RW - 32 bits - MCIND:0x5
Field Name Bits Default Description
MC_AGP_START 15:0 0x0 Defines the lowest address of the AGP Aperture
MC_AGP_TOP 31:16 0x0 Defines the highest address of the AGP Aperture
This register defines the location of the AGP space within the internal address space. The internal address space has 32 address bits (for a 4
Gbytes address range). The minimum AGP aperture granularity for M56 is 4 MB (same as Rage 6?). The start address is required to be on a 4
Mbytes boundary and the size is specified in 2 Mbytes chunks. Therefore START (21:0) must be 0x000000 and TOP (21:0) must be 0x3FFFFF.
Only the 16 MSBs of each are loaded in the register. If the Start is specified to be higher than the Top, then the AGP Aperture will be non-existent
and all addresses will be the PCI and/or Frame Buffer. Note that if the Frame Buffer Aperture is also non-existent, then all addresses will be PCI.
There is also an AGP_BASE_ADDRESS, which is used to remap the AGP addresses before sending to the AIC. When a request occurs, the
address sent to AIC = requested address - AGP_START + AGP_BASE_ADDRESS.
AGP_BASE - RW - 32 bits - MCIND:0x6
Field Name Bits Default Description
AGP_BASE_ADDR 31:0 0x0 Defines the base address of the AGP aperture. Bits 21:0 must be '0'
This register is used to remap the AGP addresses before sending to the AIC. When a request occurs, the address sent to the AIC =
Requested_Address - AGP_START + AGP_BASE_ADDRESS.
AGP_BASE_2 - RW - 32 bits - MCIND:0x7
Field Name Bits Default Description
AGP_BASE_ADDR_2 3:0 0x0
This is used for handling 32 Gbytes AGP Base Address. The 4 bits field represents the 4 MSBs. It extends the AGP_BASE to 36 bits instead of 32
bits.

M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc.
2-4 Proprietary
Memory Controller Registers
MC_CNTL0 - RW - 32 bits - MCIND:0x8
Field Name Bits Default Description
MEM_ADDR_MAP_ROWS 2:0 0x1 0=2**10 rows
1=2**11 rows
2=2**12 rows
3=2**13 rows
4=2**14 rows
5=reserved
6=reserved
7=reserved
MEM_MC_BLACKOUT 3 0x0 0=Enable MC requests - PM controlled
1=Disable MC requests - PM controlled
MEM_ADDR_MAP_COLS 5:4 0x0 0=2**8 columns
1=2**9 columns
2=2**10 columns
3=reserved
MC_CHANNEL_0_MAP 12:8 0x1 Ignored if NUM_CHANNELS = 0
0=Bit 7
1=Bit 8
2=Bit 9
3=Bit 10
4=Bit 11
5=Bit 12
6=Bit 13
7=Bit 14
8=Bit 15
9=Bit 16
10=Bit 17
11=Bit 18
12=Bit 19
13=Bit 20
14=Bit 21
15=Bit 22
16=Bit 23
17=Bit 24
18=Bit 25
19=Bit 26
20=Bit 27
21=Bit 28
22=Bit 29
23=Bit 30
24=Bit 31

Memory Controller Registers
© 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual
Proprietary 2-5
MC_CHANNEL_1_MAP 17:13 0x2 Ignored if NUM_CHANNELS = 0 | 1
0=Bit 7
1=Bit 8
2=Bit 9
3=Bit 10
4=Bit 11
5=Bit 12
6=Bit 13
7=Bit 14
8=Bit 15
9=Bit 16
10=Bit 17
11=Bit 18
12=Bit 19
13=Bit 20
14=Bit 21
15=Bit 22
16=Bit 23
17=Bit 24
18=Bit 25
19=Bit 26
20=Bit 27
21=Bit 28
22=Bit 29
23=Bit 30
24=Bit 31
MC_CHANNEL_2_MAP 22:18 0x3 Unused & Invalid.
0=Bit 7
1=Bit 8
2=Bit 9
3=Bit 10
4=Bit 11
5=Bit 12
6=Bit 13
7=Bit 14
8=Bit 15
9=Bit 16
10=Bit 17
11=Bit 18
12=Bit 19
13=Bit 20
14=Bit 21
15=Bit 22
16=Bit 23
17=Bit 24
18=Bit 25
19=Bit 26
20=Bit 27
21=Bit 28
22=Bit 29
23=Bit 30
24=Bit 31
MC_CHANNEL_SIZE 23 0x0 64-bit per channel (not supported by M56 sequencer)
0=32-bit per channel
1=64-bit per channel
MEM_NUM_CHANNELS 25:24 0x0 0=One channel
1=Two channels
2=Four channels
3=Reserved
MEM_USE_XX_CH_ONLY 27:26 0x0 0=ChanA0 if NumofChan=1, A0B0 if 2, Reserved, Reserved
1=ChanB0 if NumofChan=1, A1B1 if 2, Reserved, Reserved
2=ChanA1 if NumofChan=1, A0A1 if 2, A0A1B0B1 if 4, Reserved
3=ChanB1 if NumofChan=1, B0B1 if 2, Reserved, Reserved
AIC_IDLE_DET 28 0x1 0=Ignore AIC idle signal when determining mc_idle signal
1=Use AIC idle signal when determining mc_idle signal

M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc.
2-6 Proprietary
Memory Controller Registers
MC_INIT_COMPLETE 31 0x0 MC_INIT_COMPLETE is only to be set after all MC registers are
properly programmed and at least 32 sclk cycles have elapsed since
the last register was programmed.
0=Register Initialization Not Complete
1=Register Initialization Complete
Basic DRAM configuration (channel, rows and columns) and channel address mapping.
MC_CNTL1 - RW - 32 bits - MCIND:0x9
Field Name Bits Default Description
MC_BANK_0_MAP 4:0 0x4 0=Bit 7
1=Bit 8
2=Bit 9
3=Bit 10
4=Bit 11
5=Bit 12
6=Bit 13
7=Bit 14
8=Bit 15
9=Bit 16
10=Bit 17
11=Bit 18
12=Bit 19
13=Bit 20
14=Bit 21
15=Bit 22
16=Bit 23
17=Bit 24
18=Bit 25
19=Bit 26
20=Bit 27
21=Bit 28
22=Bit 29
23=Bit 30
24=Bit 31
MC_BANK_1_MAP 9:5 0x5 0=Bit 7
1=Bit 8
2=Bit 9
3=Bit 10
4=Bit 11
5=Bit 12
6=Bit 13
7=Bit 14
8=Bit 15
9=Bit 16
10=Bit 17
11=Bit 18
12=Bit 19
13=Bit 20
14=Bit 21
15=Bit 22
16=Bit 23
17=Bit 24
18=Bit 25
19=Bit 26
20=Bit 27
21=Bit 28
22=Bit 29
23=Bit 30
24=Bit 31

Memory Controller Registers
© 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual
Proprietary 2-7
MC_BANK_2_MAP 14:10 0x6 Ignored if MEM_ADDR_MAP_BANK = 0
0=Bit 7
1=Bit 8
2=Bit 9
3=Bit 10
4=Bit 11
5=Bit 12
6=Bit 13
7=Bit 14
8=Bit 15
9=Bit 16
10=Bit 17
11=Bit 18
12=Bit 19
13=Bit 20
14=Bit 21
15=Bit 22
16=Bit 23
17=Bit 24
18=Bit 25
19=Bit 26
20=Bit 27
21=Bit 28
22=Bit 29
23=Bit 30
24=Bit 31
MEM_ADDR_MAP_BANK 15 0x0 0=4 banks
1=8 banks
MC_RANK_MAP 20:16 0x7 Ignored if MEM_ADDR_MAP_RANK = 0
0=Bit 7
1=Bit 8
2=Bit 9
3=Bit 10
4=Bit 11
5=Bit 12
6=Bit 13
7=Bit 14
8=Bit 15
9=Bit 16
10=Bit 17
11=Bit 18
12=Bit 19
13=Bit 20
14=Bit 21
15=Bit 22
16=Bit 23
17=Bit 24
18=Bit 25
19=Bit 26
20=Bit 27
21=Bit 28
22=Bit 29
23=Bit 30
24=Bit 31
MEM_ADDR_MAP_RANK 21 0x0 0=1 rank
1=2 ranks
MC_BIST_ENABLE 24 0x0 Passes gfx generated bist signals to NPL
0=MC bist disabled
1=MC bist enabled
MC_RST_CTRL 25 0x0 0=MC soft-reset passthru
1=MC soft-reset force
ENABLE_PAGE_TABLES 26 0x0 0=disable page tables to dram interface
1=enable page tables to dram interface
Basic DRAM configuration and rank/bank address mapping.

M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc.
2-8 Proprietary
Memory Controller Registers
MC_RFSH_CNTL - RW - 32 bits - MCIND:0xA
Field Name Bits Default Description
MC_RFSH_RATE 7:0 0x1e average (64*NUM) sclk cycles between dram refreshes when
pm_slorate is deasserted (full system clock speed)
MC_RFSH_SLORATE 15:8 0xf average (32*NUM) sclk cycles between dram refreshes when
pm_slorate is asserted (dynamic clock mode)
MC_RFSH_URG 20:16 0x6 number of pending refreshes before urgency is asserted
MC_RFSH_DISABLE 21 0x1 0=DRAM Refreshes Enabled
1=DRAM Refreshes Disabled
Controls DRAM refresh timing. Example: 0x1E = 30 * 64 = 1920 cycles = 7.68nS @ 250MHz
MC_ARB_MIN - RW - 32 bits - MCIND:0x10
Field Name Bits Default Description
MC_MIN_RD_CLKS 7:0 0x60 Try to stay reading for this many clocks
MC_MIN_RD_REQS 15:8 0x0 Number of pending reads required before switching away from writ-
ing
MC_MIN_WR_CLKS 23:16 0x60 Try to stay writing for this many clocks
MC_MIN_WR_REQS 31:24 0x0 Number of pending writes required before switching away from
reading
These are global parameters that help determine when to switch between reading and writing. Should be tuned for optimal dram efficiency and cli-
ent latency; but it is not necessary to modify defaults for functional bringup.
MC_ARB_TIMERS - RW - 32 bits - MCIND:0x12
Field Name Bits Default Description
MC_IDLE_RD_CLKS 7:0 0x1 Number of elapsed clocks with no read requests before considering
reads idle
MC_IDLE_WR_CLKS 15:8 0x1 Number of elapsed clocks with no write requests before considering
writes idle
MC_WCMB_TIMEOUT 23:16 0xff Number of clocks to wait in trying to combine 4Byte read requests
into single 32B requests. For these clients only: CP, IDCT, VIP, MCIF
See MC_ARB_RDWR_SWITCH description for more information on IDLE fields. Should be tuned for optimal dram efficiency and client latency;
but it is not necessary to modify defaults for functional bringup.
MC_ARB_DRAM_PENALTIES - RW - 32 bits - MCIND:0x13
Field Name Bits Default Description
MC_RAS2RAS 6:0 0x2f tRC
MC_SHORT_BURST_PENALTY 13:8 0x3 ~1/2 MC_ACTIVATION_PENALTY
MC_ACTIVATION_PENALTY 21:16 0x8 (tRAR + tRAW) / 2
MC_NOT_MIN_PENALTY 29:24 0x20 ~ 3/4 tRC
In HCLK units. Using DRAM timing parameters.
MC_ARB_DRAM_PENALTIES2 - RW - 32 bits - MCIND:0x14
Field Name Bits Default Description
MC_SHORT_TO_COVER_PENALTY 5:0 0x4 ~ 1/2 MC_ACTIVATION_PENALTY
MC_READ_ACTIVATION 13:8 0xe tRAR
MC_WRITE_ACTIVATION 21:16 0xb tRAW
MC_PRECHARGE 29:24 0xc tRP

Memory Controller Registers
© 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual
Proprietary 2-9
In HCLK units. Using DRAM timing parameters.
MC_ARB_DRAM_PENALTIES3 - RW - 32 bits - MCIND:0x15
Field Name Bits Default Description
MC_MIN_PENAL_ISSUE 5:0 0x23 ~tRC
MC_RATIO_CLK_MODE 9:8 0x2 If 0 < (hclk / sclk) <= 1, = 0 If 1 < (hclk / sclk) <= 2, = 1 If 2 < (hclk
/ sclk) <= 3, = 2 If 3 < (hclk / sclk) <= 4, = 3
In HCLK units. Using DRAM timing parameters.
MC_ARB_RATIO_CLK_SEQ - RW - 32 bits - MCIND:0x16
Field Name Bits Default Description
MC_RATIO_CLK_SEQ 31:0 0x0 Magic field, please use the excel programming guide. Sets the
hclk/sclk ratio in the arbiter.
MC_ARB_RDWR_SWITCH - RW - 32 bits - MCIND:0x17
Field Name Bits Default Description
MC_RDWR_SWITCH_MODE 3:0 0x0 Read v. Write decision algorithm (see register description)
2'b00 => ~wrwt_gt_rdwt & (~|rwtimer_reg | idle_wrs);
2'b01 => ~wrwt_gt_rdwt & (~|rwtimer_reg | idle_wrs | (enough_rds &
~enough_wrs));
2'b10 => ~wrwt_gt_rdwt & ~|rwtimer_reg & (enough_rds | idle_wrs);
2'b11 => ~|rwtimer_reg | idle_wrs;
MC_RD2WR_HYST 15:8 0x1 Read hysteresis
MC_WR2RD_HYST 23:16 0x1 Write hysteresis
Read v. Write decision algorithm. Should be tuned for optimal dram efficiency and client latency; but it is not necessary to modify defaults for func-
tional bringup.
MC_SW_CNTL - RW - 8 bits - MCIND:0x18
Field Name Bits Default Description
MC_BUBBLE_INSERT 2:0 0x1 Insert this many dead cycles between each burst of requests to the
sequencer. Must not be set to 0.
Increasing this value may prevent inefficient requests from clogging the sequencer, and may provide for a smaller worst-case latency. Unverified
for values other than 0x1.
MC_WRITE_AGE1 - RW - 32 bits - MCIND:0x37
Field Name Bits Default Description
MC_CBW_AGEDIV 4:0 0x8
MC_CBW_USEAGE 7 0x1 0=Do not age CB write requests
1=Age CB write requests
MC_ZBW_AGEDIV 12:8 0x8
MC_ZBW_USEAGE 15 0x1 0=Do not age ZB write requests
1=Age ZB write requests
MC_MCIF_AGEDIV 20:16 0x8
MC_MCIF_USEAGE 23 0x1 0=Do not age MCIF write requests
1=Age MCIF write requests

M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc.
2-10 Proprietary
Memory Controller Registers
MC_VIP_AGEDIV 28:24 0x8
MC_VIP_USEAGE 31 0x1 0=Do not age VIP write requests
1=Age VIP write requests
Arbitration parameters for these clients. Should be tuned for optimal dram efficiency and client latency; but it is not necessary to modify defaults for
functional bringup.
MC_WRITE_AGE2 - RW - 32 bits - MCIND:0x38
Field Name Bits Default Description
MC_DCT_AGEDIV 4:0 0x8
MC_DCT_USEAGE 7 0x1 0=Do not age DCT write requests
1=Age DCT write requests
MC_HDP_AGEDIV 12:8 0x8
MC_HDP_USEAGE 15 0x1 0=Do not age HDP write requests
1=Age HDP write requests
MC_CP_AGEDIV 20:16 0x8
MC_CP_USEAGE 23 0x1 0=Do not age CP write requests
1=Age CP write requests
Arbitration parameters for these clients. Should be tuned for optimal dram efficiency and client latency; but it is not necessary to modify defaults for
functional bringup.
MC_SEQ_DRAM - RW - 32 bits - MCIND:0x60
Field Name Bits Default Description
ADR_2CK 0 0x0 Number of cycle(s) to send an address. One cycle for non-DDR4.
Two cycles for DDR4.
0=One-cycle address
1=Two-cycle address
ADR_MUX 1 0x0 Address bus is shared between two channels or not. Not shared for
DDR4. Shared for non-DDR4.
0=Address bus is not shared
1=Address bus is shared
ADR_DF1 2 0x0 Default value for address bus (during NOP).
0=Address default low
1=Address default high
AP8 3 0x0 Location of auto-precharge bit.
0=AP bit starts at MSB+1
1=AP bit is bit 8
DAT_DF1 4 0x0 Default value for data bus.
0=DAT default low
1=DAT default high
DQS_DF1 5 0x0 Default value for write strobes.
0=DQS default low
1=DQS default high
DQM_DF1 6 0x0 Default value for write mask.
0=DQM default low
1=DQM default high
DQM_ACT 7 0x0 Polarity of data mask. Active low for DDR4. Active high for
non-DDR4.
0=DQM active low
1=DQM active high
STB_CNT 11:8 0xf DRAM standby counter. Number of idle cycles before dynamic CKE
is enabled. This prevents the CKE from turning off too easily.
CKE_DYN 12 0x0 Dynamic CKE.
0=Disable
1=Enable

Memory Controller Registers
© 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual
Proprietary 2-11
CKE_ACT 13 0x1 Polarity of clock enable. Active low for DDR4. Active high for
non-DDR4.
0=Active low
1=Active high
BO4 14 0x0 DRAM burst size.
0=DRAM is burst of 8
1=DRAM is burst of 4
DLL_CNT 19:16 0xf DRAM DLL lock time in multiples of 16 mclk cycles.
DLL_CLR 20 0x0 Resets DLL lock timer. DRAM power up is completed once the DLL
lock time is reached. If the DLL lock timer is reset, the DRAM power
up flag is deasserted.
0=Not reset DLL timer
1=Reset DLL timer
DAT_INV 24 0x0 Enables/disables DDR write data inversion mode.
0=Disable write data inversion
1=Enable write data inversion
INV_ACM 25 0x1 Selects DDR write data inversion mode.
0=DC mode
1=AC mode
ODT_ENB 26 0x0 0=Disable ODT
1=Enable ODT
ODT_ACT 27 0x1 0=ODT active low
1=ODT active high
RST_CTL 28 0x0 Controls DRAM reset pin. Channel pair B only.
0=Drive reset low
1=Drive reset high
This register specifies the character of the DRAM interface.
MC_SEQ_RAS_TIMING - RW - 32 bits - MCIND:0x61
Field Name Bits Default Description
TRCDW 4:0 0x0 Number of cycles from active to write - 1.
TRCDWA 9:5 0x0 Number of cycles from active to write with auto-precharge - 1. A spe-
cial case for DDR1. Otherwise the same as TRCDW.
TRCDR 14:10 0x0 Number of cycles from active to read - 1.
TRCDRA 19:15 0x0 Number of cycles from active to read with auto-precharge - 1. A spe-
cial case for DDR1. Otherwise the same as TRCDR.
TRRD 23:20 0x0 Number of cycles from active bank a to active bank b - 1.
TRC 30:24 0x0 Number of cycles from active to active/auto refresh - 1.
RAS related parameters in hclk cycles.
MC_SEQ_CAS_TIMING - RW - 32 bits - MCIND:0x62
Field Name Bits Default Description
TNOPW 1:0 0x0 Extra cycle(s) between successive write bursts. For debugging pur-
pose only.
TNOPR 3:2 0x0 Extra cycle(s) between successive read bursts. For debugging pur-
pose only.
TR2W 8:4 0x0 Read to write turn around time - 1.
TR2R 15:12 0x0 Read to read time - 1 (different rank).
TW2R 20:16 0x0 Write to read turn around time - 1.
TCL 28:24 0x0 CAS to data return latency - 2 (0 to 20).
CAS related parameters in hclk cycles.

M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc.
2-12 Proprietary
Memory Controller Registers
MC_SEQ_MISC_TIMING - RW - 32 bits - MCIND:0x63
Field Name Bits Default Description
TRP_WRA 5:0 0x0 From write with auto-precharge to active - 1.
TRP_RDA 13:8 0x0 From read with auto-precharge to active - 1.
TRP 19:16 0x0 Precharge command period - 1.
TRFC 26:20 0x0 Auto-refresh command period - 1.
TCKE 31:28 0x0 CKE power down exit timer.
Misc. DRAM parameters in hclk cycles.
MC_SEQ_RD_CTL_I0 - RW - 32 bits - MCIND:0x64
Field Name Bits Default Description
RCV_DLY 2:0 0x0 Delay to turn on receive enable.
0=Turn on receive enable at CL-2
1=Turn on receive enable at CL-1
2=Turn on receive enable at CL
3=Turn on receive enable at CL+1
4=Turn on receive enable at CL+2
5=Turn on receive enable at CL+3
6=Turn on receive enable at CL+4
7=Turn on receive enable at CL+5
RCV_EXT 7:4 0x0 Extends receive enable signal to cover clock drift.
0=DQS receive enable not extended
1=DQS receive enable extended by 1 cycle
2=DQS receive enable extended by 2 cycles
3=DQS receive enable extended by 3 cycles
4=DQS receive enable extended by 4 cycles
5=DQS receive enable extended by 5 cycles
6=DQS receive enable extended by 6 cycles
7=DQS receive enable extended by 7 cycles
8=DQS receive enable always on
RST_SEL 9:8 0x0 NPL FIFO pointer reset mode.
0=Reset pointers off
1=Reset pointers on
2=Reset pointers before read
3=Reset pointers during refresh
RST_HLD 15:12 0x0 Disables NPL FIFO pointer reset after a read command for a certain
period of time. This prevents the pointers (read and write) from reset-
ting before the FIFO is read.
0=Disable reset by 11 cycles
1=Disable reset by 12 cycles
2=Disable reset by 13 cycles
3=Disable reset by 14 cycles
4=Disable reset by 15 cycles
5=Disable reset by 16 cycles
6=Disable reset by 17 cycles
7=Disable reset by 18 cycles
8=Disable reset by 19 cycles
9=Disable reset by 20 cycles
10=Disable reset by 21 cycles
11=Disable reset by 22 cycles
12=Disable reset by 23 cycles
13=Disable reset by 24 cycles
14=Disable reset by 25 cycles
STR_PRE 16 0x0 Creates an extra strobe in the preamble of a burst. This is needed if
DQS is default high and its falling edge is used as a trigger.
0=No read pre strobe
1=Extra read pre strobe

Memory Controller Registers
© 2007 Advanced Micro Devices, Inc. M56 Register Reference Manual
Proprietary 2-13
STR_PST 17 0x0 Creates an extra strobe in the postamble of a burst. This is needed if
DQS is default high and its rising edge is used as a trigger.
0=No read post strobe
1=Extra read post strobe
RBS_DLY 24:20 0x0 Delay to read data out of a NPL FIFO. This is used to cover the NPL
FIFO's write to read latency.
0=Assert RBS valid at CL+8
1=Assert RBS valid at CL+9
2=Assert RBS valid at CL+10
3=Assert RBS valid at CL+11
4=Assert RBS valid at CL+12
5=Assert RBS valid at CL+13
6=Assert RBS valid at CL+14
7=Assert RBS valid at CL+15
8=Assert RBS valid at CL+16
9=Assert RBS valid at CL+17
10=Assert RBS valid at CL+18
11=Assert RBS valid at CL+19
12=Assert RBS valid at CL+20
13=Assert RBS valid at CL+21
14=Assert RBS valid at CL+22
15=Assert RBS valid at CL+23
16=Assert RBS valid at CL+24
17=Assert RBS valid at CL+25
Channel 0's read command parameters in hclk.
MC_SEQ_RD_CTL_I1 - RW - 32 bits - MCIND:0x65
Field Name Bits Default Description
RCV_DLY 2:0 0x0 0=Turn on receive enable at CL-2
1=Turn on receive enable at CL-1
2=Turn on receive enable at CL
3=Turn on receive enable at CL+1
4=Turn on receive enable at CL+2
5=Turn on receive enable at CL+3
6=Turn on receive enable at CL+4
7=Turn on receive enable at CL+5
RCV_EXT 7:4 0x0 0=DQS receive enable not extended
1=DQS receive enable extended by 1 cycle
2=DQS receive enable extended by 2 cycles
3=DQS receive enable extended by 3 cycles
4=DQS receive enable extended by 4 cycles
5=DQS receive enable extended by 5 cycles
6=DQS receive enable extended by 6 cycles
7=DQS receive enable extended by 7 cycles
8=DQS receive enable always on
RST_SEL 9:8 0x0 0=Reset pointers off
1=Reset pointers on
2=Reset pointers before read
3=Reset pointers during refresh

M56 Register Reference Manual © 2007 Advanced Micro Devices, Inc.
2-14 Proprietary
Memory Controller Registers
RST_HLD 15:12 0x0 0=Disable reset by 11 cycles
1=Disable reset by 12 cycles
2=Disable reset by 13 cycles
3=Disable reset by 14 cycles
4=Disable reset by 15 cycles
5=Disable reset by 16 cycles
6=Disable reset by 17 cycles
7=Disable reset by 18 cycles
8=Disable reset by 19 cycles
9=Disable reset by 20 cycles
10=Disable reset by 21 cycles
11=Disable reset by 22 cycles
12=Disable reset by 23 cycles
13=Disable reset by 24 cycles
14=Disable reset by 25 cycles
STR_PRE 16 0x0 0=No read pre strobe
1=Extra read pre strobe
STR_PST 17 0x0 0=No read post strobe
1=Extra read post strobe
RBS_DLY 24:20 0x0 0=Assert RBS valid at CL+8
1=Assert RBS valid at CL+9
2=Assert RBS valid at CL+10
3=Assert RBS valid at CL+11
4=Assert RBS valid at CL+12
5=Assert RBS valid at CL+13
6=Assert RBS valid at CL+14
7=Assert RBS valid at CL+15
8=Assert RBS valid at CL+16
9=Assert RBS valid at CL+17
10=Assert RBS valid at CL+18
11=Assert RBS valid at CL+19
12=Assert RBS valid at CL+20
13=Assert RBS valid at CL+21
14=Assert RBS valid at CL+22
15=Assert RBS valid at CL+23
16=Assert RBS valid at CL+24
17=Assert RBS valid at CL+25
Channel 1's read command parameters in hclk. See MC_SEQ_RD_CTL_I0.
MC_SEQ_WR_CTL_I0 - RW - 32 bits - MCIND:0x66
Field Name Bits Default Description
DAT_DLY 3:0 0x0 Write command to data output latency.
DQS_DLY 7:4 0x0 Write command to DQS latency.
DQS_XTR 8 0x0 Controls write preamble.
0=No write preamble
1=Write preamble
OEN_DLY 15:12 0x0 Write command to output enable latency.
OEN_EXT 16 0x0 Extend output enable after data burst.
0=output enable not extended
1=output enable extended by one cycle
OEN_SEL 21:20 0x0 Output enable select mask (for debug only).
ODT_DLY 27:24 0x0 Write command to on-die-termination enable latency.
ODT_EXT 28 0x0 Extends on-die-termination enable after data burst.
0=ODT not extended
1=ODT extended by one cycle
Channel 0's write command parameters in hclk.
MC_SEQ_WR_CTL_I1 - RW - 32 bits - MCIND:0x67