ARTERY AT32F402 Series User manual

AT32F402/405 Series Reference Manual
2023.08.31 Page 1 Ver 2.00
ARM®-based 32-bit Cortex®-M4F MCU+FPU, with 128 to 256 KB Flash, sLib,
USBFS/HS-OTG, 12 timers, 1 ADC, 20 communication interfaces
Core: ARM® 32-bit Cortex®-M4F CPU with FPU
−216 MHz maximum frequency, with a Memory
Protection Unit (MPU), single-cycle multiplication
and hardware division
−Floating Point Unit (FPU)
−DSP instructions
Memories
−128 to 256 Kbytes of Flash memory
−20 Kbytes of boot memory used as a Bootloader or
as a general instruction/data memory (one-time
configured)
−sLib: configurable part of main Flash as a library
area with code executable but secured, non-
readable
−70 to 102 Kbytes of SRAM
Power control (PWC)
−2.4 V to 3.6 V power supply
−Power-on reset (POR)/low voltage reset (LVR), and
power voltage monitor (PVM)
−Low-power modes: Sleep, Deepsleep and Standby
modes
−20 x 32-bit RTC data registers (BPR)
Clock and reset management (CRM)
−4 to 25 MHz crystal (HEXT)
−48 MHz internal factory-trimmed HICK (1% at
TA=25 °C, 2% at TA=-40 °C to +105 °C), with
automatic clock calibration (ACC)
−PLL with configurable frequency multiplication and
division factors
−32.768 kHz crystal (LEXT)
−Low speed internal clock (LICK)
Analog
−1 x 12-bit 2 MSPS A/D converter, up to 16 input
channels, hardware over-sampling up to equivalent
16-bit resolution
−Temperature sensor (VTS), internal reference voltage
(VINTR)
DMA
−2 x 7-channel DMA controllers
Up to 56 fast GPIOs
−All mappable on 16 external interrupts
−Almost 5 V-tolerant
Up to 14 timers (TMR)
−1 x 16-bit 4-channel advanced timer, each channel
PWM output with dead-time generator and
emergency break
−Up to 1 x 32-bit and 7 x 16-bit general-purpose
timers, each with 4 IC/OC/PWM or pulse counter
and incremental encoder input; including 5 timers
supporting complementary output with dead-time
generator and emergency brake
−2 x 16-bit basic timers
−2 x watchdog timers (WDT and WWDT)
−SysTick timer: 24-bit downcounter
ERTC: Enhanced RTC, with auto wakeup, alarm,
subsecond accuracy, hardware calendar, and
calibration feature
Up to 19 communication interfaces
−Up to 3 x I2C interfaces (SMBus/PMBus)
−Up to 8 x USARTs/UARTs (ISO7816 interface, LIN,
IrDA capability, modem control and RS485 drive
enable, TX/RX swap)
−3 x SPIs, all with I2S interface multiplexed, any
combination of two interfaces support full-duplex,
with 1 full-duplex I2SF interface
−1 x CAN interface (2.0B Active)
−USB2.0 FS/host/OTG device interface, supporting
crystal-less in device mode
−USB2.0 HS/host/OTG device interface
−1 x QSPI
−Infrared transmitter (IRTMR)
CRC calculation unit
96-bit unique ID (UID)
Debug mode
−SWD interface
Operating temperature: -40 to +105 °C
Packages
−LQFP64 10 x 10 mm
−LQFP64 7 x 7 mm
−LQFP48 7 x 7 mm
−QFN48 6 x 6 mm
−QFN32 4 x 4 mm
List of models
Internal Flash
Model
128 Kbytes
AT32F405RBT7 AT32F405RBT7-7
AT32F405CBT7 AT32F405CBU7
AT32F405KBU7-4
AT32F402RBT7 AT32F402RBT7-7
AT32F402CBT7 AT32F402CBU7
AT32F402KBU7-4
256 Kbytes
AT32F405RCT7 AT32F405RCT7-7
AT32F405CCT7 AT32F405CCU7
AT32F405KCU7-4
AT32F402RCT7 AT32F402RCT7-7
AT32F402CCT7 AT32F402CCU7
AT32F402KCU7-45RCT7-7
AT32F405RCT7

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Contents
1System architecture...................................................................... 33
1.1 System overview..........................................................................34
1.1.1 ARM Cortex®-M4F processor ....................................................... 34
1.1.2 Bit band...................................................................................... 34
1.1.3 Interrupt and exception vectors .................................................... 36
1.1.4 System Tick (SysTick) ................................................................. 40
1.1.5 Reset ......................................................................................... 40
1.2 List of abbreviations for registers ..................................................41
1.3 Device characteristics information.................................................42
1.3.1 Flash memory size register .......................................................... 42
1.3.2 Device electronic signature.......................................................... 42
2Memory resources ........................................................................ 43
2.1 Internal memory address map.......................................................43
2.2 Flash memory..............................................................................44
2.3 SRAM memory.............................................................................45
2.4 Peripheral address map................................................................45
3Power control (PWC)..................................................................... 48
3.1 Introduction .................................................................................48
3.2 Main features ..............................................................................48
3.3POR/LVR ....................................................................................49
3.4 Power voltage monitor (PVM)........................................................49
3.5 Power domain..............................................................................50
3.6 Power saving modes ....................................................................50
3.7 PWC registers .............................................................................52
3.7.1 Power control register (PWC_CTRL) ............................................ 52
3.7.2 Power control/status register (PWC_CTRLSTS) ............................ 53
3.7.3 LDO output voltage select register (PWC_LDOOV)........................ 55
4Clock and reset manage (CRM) ..................................................... 56
4.1 Clock ..........................................................................................56

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4.1.1 Clock sources ............................................................................. 57
4.1.2 System clock............................................................................... 58
4.1.3 Peripheral clock .......................................................................... 58
4.1.4 Clock fail detector ....................................................................... 58
4.1.5 Auto step-by-step system clock switch.......................................... 59
4.1.6 Internal clock output.................................................................... 59
4.1.7 Interrupts.................................................................................... 59
4.2 Reset..........................................................................................59
4.2.1 System reset............................................................................... 59
4.2.2 Battery powered domain reset...................................................... 60
4.3 CRM registers .............................................................................60
4.3.1 Clock control register (CRM_CTRL).............................................. 60
4.3.2 PLL clock configuration register (CRM_PLLCFG) .......................... 62
4.3.3 Clock configuration register (CRM_CFG) ...................................... 63
4.3.4 Clock interrupt register (CRM_CLKINT) ........................................ 64
4.3.5 AHB peripheral reset register 1 (CRM_AHBRST1)......................... 65
4.3.6 AHB peripheral reset register 2 (CRM_AHBRST2)......................... 67
4.3.7 AHB peripheral reset register 3 (CRM_AHBRST3)......................... 67
4.3.8 APB1 peripheral reset register (CRM_APB1RST) .......................... 67
4.3.9 APB2 peripheral reset register (CRM_APB2RST) .......................... 68
4.3.10 AHB peripheral clock enable register 1 (CRM_AHBEN1)................ 69
4.3.11 AHB peripheral clock enable register 2 (CRM_AHBEN2)................ 69
4.3.12 AHB peripheral clock enable register 3 (CRM_AHBEN3)................ 70
4.3.13 APB1 peripheral clock enable register (CRM_APB1EN) ................. 70
4.3.14 APB2 peripheral clock enable register (CRM_APB2EN) ................. 71
4.3.15 AHB peripheral clock enable in low-power mode register 1
(CRM_AHBLPEN1)................................................................................ 72
4.3.16 AHB peripheral clock enable in low-power mode register 2
(CRM_AHBLPEN2)................................................................................ 72
4.3.17 AHB peripheral clock enable in low-power mode register 3
(CRM_AHBLPEN3)................................................................................ 73
4.3.18 APB1 peripheral clock enable in low-power mode register
(CRM_APB1LPEN)................................................................................ 73
4.3.19 APB2 peripheral clock enable in low-power mode register
(CRM_APB2LPEN)................................................................................ 74

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4.3.20 Battery powered domain control register (CRM_BPDC).................. 75
4.3.21 Control/status register (CRM_CTRLSTS) ...................................... 75
4.3.22 OTGHS control register (CRM_OTGHS)........................................ 76
4.3.23 Additional register 1 (CRM_MISC1) .............................................. 76
4.3.24 Additional register 2 (CRM_MISC2) .............................................. 77
5Flash memory controller (FLASH)................................................. 79
5.1 FLASH introduction......................................................................79
5.2 Flash memory operation ...............................................................81
5.2.1 Unlock/lock ................................................................................. 81
5.2.2 Erase operation........................................................................... 81
5.2.3 Programming operation................................................................ 83
5.2.4 Read operation ........................................................................... 85
5.3 Main Flash memory extension area ...............................................85
5.4 User system data area operation...................................................85
5.4.1 Unlock/lock ................................................................................. 85
5.4.2 Erase operation........................................................................... 85
5.4.3 Programming operation................................................................ 86
5.4.4 Read operation ........................................................................... 87
5.5 Flash memory protection ..............................................................87
5.5.1 Access protection........................................................................ 87
5.5.2 Erase/program protection............................................................. 88
5.6 Read access................................................................................89
5.7 Special functions .........................................................................89
5.7.1 Security library settings ............................................................... 89
5.7.2 Boot memory used as Flash memory extension ............................. 90
5.7.3 CRC verify .................................................................................. 90
5.8 FLASH registers ..........................................................................90
5.8.1 Flash performance select register (FLASH_PSR) .......................... 91
5.8.2 Flash unlock register (FLASH_UNLOCK) ...................................... 91
5.8.3 Flash user system data unlock register (FLASH_USD_UNLOCK) ... 92
5.8.4 Flash status register (FLASH_STS) .............................................. 92
5.8.5 Flash control register (FLASH_CTRL)........................................... 92
5.8.6 Flash address register (FLASH_ADDR) ........................................ 93

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5.8.7 User system data register (FLASH_USD)...................................... 93
5.8.8 Erase/program protection status register (FLASH_EPPS) .............. 93
5.8.9 Flash security library status register 0 (SLIB_STS0)...................... 93
5.8.10 Flash security library status register 1 (SLIB_STS1)...................... 94
5.8.11 Security library password clear register (SLIB_PWD_CLR) ............ 94
5.8.12 Security library additional status register (SLIB_MISC_STS).......... 95
5.8.13 Flash CRC address register (FLASH_CRC_ADDR)........................ 95
5.8.14 Flash CRC check control register (FLASH_CRC_CTRL) ................ 95
5.8.15 Flash CRC check result register (FLASH_CRC_CHKR).................. 95
5.8.16 Security library password setting register (SLIB_SET_PWD).......... 96
5.8.17 Security library address setting register (SLIB_SET_RANGE) ........ 96
5.8.18 Flash extension memory security library setting register
(EM_SLIB_SET).................................................................................... 97
5.8.19 Boot memory mode setting register (BTM_MODE_SET)................. 97
5.8.20 Security library unlock register (SLIB_UNLOCK) ........................... 97
6GPIOs and IOMUX ......................................................................... 98
6.1 Introduction .................................................................................98
6.2 Function overview........................................................................98
6.2.1 GPIO structure............................................................................ 98
6.2.2 GPIO reset status........................................................................ 99
6.2.3 General-purpose input configuration............................................. 99
6.2.4 Analog input/output configuration ................................................. 99
6.2.5 General-purpose output configuration........................................... 99
6.2.6 I/O port protection ......................................................................100
6.2.7 IOMUX structure ........................................................................100
6.2.8 Multiplexed function pull-up/pull-down configuration.....................100
6.2.9 IOMUX input/output ....................................................................101
6.2.10 Peripheral MUX function configuration.........................................108
6.2.11 IOMUX mapping priority..............................................................108
6.2.12 External interrupt/wake-up lines ..................................................108
6.3 GPIO registers........................................................................... 109
6.3.1 GPIO configuration register (GPIOx_CFGR) (x=A..F)....................109
6.3.2 GPIO output mode register (GPIOx_OMODE) (x=A..F)..................109
6.3.3 GPIO drive capability register (GPIOx_ODRVR) (x=A..F) ..............110

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6.3.4 GPIO pull-up/pull-down register (GPIOx_PULL) (x=A..F) ..............110
6.3.5 GPIO input data register (GPIOx_IDT) (x=A..F)............................110
6.3.6 GPIO output data register (GPIOx_ODT) (x=A..F) ........................110
6.3.7 GPIO set/clear register (GPIOx_SCR) (x=A..F) ............................110
6.3.8 GPIO write protection register (GPIOx_WPR) (x=A..F)..................111
6.3.9 GPIO multiplexed function low register (GPIOx_MUXL) (x=A..F) ...111
6.3.10 GPIO multiplexed function high register (GPIOx_MUXH) (x=A..F)..112
6.3.11 GPIO port bit clear register (GPIOx_CLR) (x=A..F).......................112
6.3.12 GPIO port bit toggle register (GPIOx_TOGR) (x=A..F) ..................113
6.3.13 GPIO huge current control register (GPIOx_HDRV) (x=A..F) .........113
7System configuration controller (SYSCFG)................................. 114
7.1 Introduction ............................................................................... 114
7.2 SCFG registers.......................................................................... 114
7.2.1 SCFG configuration register 1 (SCFG_CFG1) ..............................114
7.2.2 SCFG configuration register 2 (SCFG_CFG2) ..............................114
7.2.3 SCFG external interrupt configuration register 1 (SCFG_EXINTC1)115
7.2.4 SCFG external interrupt configuration register 2 (SCFG_EXINTC2)116
7.2.5 SCFG external interrupt configuration register 3 (SCFG_EXINTC3)116
7.2.6 SCFG external interrupt configuration register 4 (SCFG_EXINTC4)117
7.2.7 SCFG ultra high sourcing/sinking strength register (SCFG_UHDRV)118
8External interrupt/event controller (EXINT) ................................. 119
8.1 EXINT introduction..................................................................... 119
8.2 Function overview and configuration procedure ............................ 119
8.3 EXINT registers ......................................................................... 120
8.3.1 Interrupt enable register (EXINT_INTEN).....................................120
8.3.2 Event enable register (EXINT_EVTEN) ........................................120
8.3.3 Polarity configuration register 1 (EXINT_POLCFG1).....................120
8.3.4 Polarity configuration register 2 (EXINT_POLCFG2).....................120
8.3.5 Software trigger register (EXINT_SWTRG)...................................121
8.3.6 Interrupt status register (EXINT_INTSTS) ....................................121
9DMA controller (DMA) ................................................................. 122
9.1 Introduction ............................................................................... 122

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9.2 Main features ............................................................................ 122
9.3 Function overview...................................................................... 123
9.3.1 DMA configuration......................................................................123
9.3.2 Handshake mechanism...............................................................123
9.3.3 Arbiter .......................................................................................123
9.3.4 Programmable data transfer width ...............................................124
9.3.5 Errors ........................................................................................125
9.3.6 Interrupts...................................................................................125
9.4 DMA multiplexer (DMAMUX) ....................................................... 125
9.4.1 DMAMUX function overview ........................................................125
9.4.2 DMAMUX overflow interrupts ......................................................127
9.5 DMA registers............................................................................ 128
9.5.1 DMA interrupt status register (DMA_STS)....................................130
9.5.2 DMA interrupt flag clear register (DMA_CLR)...............................132
9.5.3 DMA channel-x configuration register (DMA_CxCTRL) (x=1…7)....134
9.5.4 DMA channel-x number of data register (DMA_CxDTCNT) (x=1…7)135
9.5.5 DMA channel-x peripheral address register (DMA_CxPADDR)
(x=1…7) ..............................................................................................135
9.5.6 DMA channel-x memory address register (DMA_CxMADDR) (x=1…7)135
9.5.7 DMAMUX select register (DMA_MUXSEL) ...................................135
9.5.8 DMAMUX channel-x control register (DMA_MUXCxCTRL) (x=1…7)136
9.5.9 DMAMUX generator-x control register (DMA_MUXGxCTRL) (x=1…4)137
9.5.10 DMAMUX channel synchronization status register
(DMA_MUXSYNCSTS) .........................................................................137
9.5.11 DMAMUX channel interrupt flag clear register (DMA_MUXSYNCCLR)137
9.5.12 DMAMUX generator interrupt status register (DMA_MUXGSTS) ....138
9.5.13 DMAMUX generator interrupt flag clear register (DMA_MUXGCLR)138
10 CRC calculation unit (CRC)......................................................... 139
10.1 CRC introduction ....................................................................... 139
10.2 CRC function description ............................................................ 139
10.3 CRC registers............................................................................ 140
10.3.1 Data register (CRC_DT)..............................................................140
10.3.2 Common data register (CRC_CDT)..............................................140
10.3.3 Control register (CRC_CTRL)......................................................141

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10.3.4 Initialization register (CRC_IDT) .................................................141
10.3.5 Polynomial register (CRC_POLY) ................................................141
11 I2C interface ................................................................................ 142
11.1 I2C Introduction ......................................................................... 142
11.2 I2C main features....................................................................... 142
11.3 I2C function overview ................................................................. 142
11.4 I2C Interface.............................................................................. 143
11.4.1 I2C timing control .......................................................................145
11.4.2 Data transfer management..........................................................146
11.4.3 I2C master communication flow ...................................................147
11.4.4 I
2
C slave communication flow .....................................................152
11.4.5 SMBus.......................................................................................155
11.4.6 SMBus master communication flow..............................................157
11.4.7 SMBus slave communication flow................................................159
11.4.8 Data transfer using DMA.............................................................163
11.4.9 Error management......................................................................164
11.5 I2C interrupt requests ................................................................. 165
11.6 I2C debug mode......................................................................... 165
11.7 I2C registers .............................................................................. 165
11.7.1 Control register 1 (I2C_CTRL1)...................................................166
11.7.2 Control register 2 (I2C_CTRL2)...................................................167
11.7.3 Address register 1 (I2C_OADDR1) ..............................................167
11.7.4 Address register 2 (I2C_OADDR2) ..............................................167
11.7.5 Timing register (I2C_CLKCTRL) ..................................................168
11.7.6 Timeout register (I2C_TIMEOUT) ................................................168
11.7.7 Status register (I2C_STS) ...........................................................168
11.7.8 Status clear flag (I2C_CLR) ........................................................170
11.7.9 PEC register (I2C_PEC) .............................................................170
11.7.10 Receive data register (I2C_RXDT)............................................170
11.7.11 Transmit data register (I2C_TXDT) ...........................................170
12 Universal synchronous/asynchronous receiver/transmitter (USART)171
12.1 USART introduction ................................................................... 171

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12.2 Full-duplex/half-duplex selector .................................................. 173
12.3 Mode selector............................................................................ 173
12.3.1 Introduction................................................................................173
12.3.2 Configuration procedure .............................................................173
12.4 USART frame format and configuration........................................ 176
12.5 DMA transfer introduction ........................................................... 178
12.5.1 Transmission using DMA ............................................................178
12.5.2 Reception using DMA .................................................................179
12.6 Baud rate generation.................................................................. 179
12.6.1 Introduction................................................................................179
12.6.2 Configuration .............................................................................179
12.7 Transmitter................................................................................ 180
12.7.1 Introduction................................................................................180
12.7.2 Transmitter configuration ............................................................180
12.8 Receiver ................................................................................... 181
12.8.1 Introduction................................................................................181
12.8.2 Receiver configuration................................................................181
12.8.3 Start bit and noise detection .......................................................182
12.9 Tx/Rx swap ............................................................................... 183
12.10Interrupts .................................................................................. 184
12.11I/O pin control............................................................................ 184
12.12USART registers........................................................................ 184
12.12.1 Status register (USART_STS) ..................................................185
12.12.2 Data register (USART_DT).......................................................186
12.12.3 Baud rate register (USART_BAUDR) ........................................186
12.12.4 Control register 1 (USART_CTRL1) ..........................................187
12.12.5 Control register 2 (USART_CTRL2) ..........................................189
12.12.6 Control register 3 (USART_CTRL3) ..........................................190
12.12.7 Guard time and divider register (GDIV).....................................192
12.12.8 Receiver timeout detection register (RTOV) ..............................192
12.12.9 Interrupt flag clear register (IFC) ..............................................192
13 Serial peripheral interface (SPI).................................................. 193
13.1 SPI introduction......................................................................... 193

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13.2 Functional overview ................................................................... 193
13.2.1 SPI overview..............................................................................193
13.2.2 Full-duplex/half-duplex mode selector .........................................194
13.2.3 Chip select controller..................................................................196
13.2.4 SPI_SCK controller ....................................................................196
13.2.5 CRC overview ............................................................................197
13.2.6 DMA transfer..............................................................................198
13.2.7 TI mode overview .......................................................................198
13.2.8 Transmitter ................................................................................199
13.2.9 Receiver ....................................................................................199
13.2.10 Motorola mode ........................................................................200
13.2.11 TI mode communication timings ...............................................202
13.2.12 Interrupts ................................................................................203
13.2.13 IO pin control ..........................................................................203
13.3 I2S functional description............................................................ 204
13.3.1 I2S introduction ..........................................................................204
13.3.2 I2S full-duplex mode ...................................................................205
13.3.3 Operating mode selection ...........................................................205
13.3.4 Audio protocol selector ...............................................................207
13.3.5 I2S_CLK controller .....................................................................208
13.3.6 DMA transfer..............................................................................209
13.3.7 Transmitter/Receiver ..................................................................210
13.3.8 I2S communication timings .........................................................211
13.3.9 Interrupts...................................................................................211
13.3.10 IO pin control ..........................................................................211
13.4 SPI registers ............................................................................. 212
13.4.1 SPI control register1 (SPI_CTRL1) (Not used in I2S mode) ...........212
13.4.2 SPI control register2 (SPI_CTRL2) ..............................................213
13.4.3 SPI status register (SPI_STS) .....................................................214
13.4.4 SPI data register (SPI_DT) .........................................................215
13.4.5 SPICRC register (SPI_CPOLY) (Not used in I2S mode).................215
13.4.6 SPIRxCRC register (SPI_RCRC) (Not used in I2S mode) ..............215
13.4.7 SPITxCRC register (SPI_TCRC)..................................................215
13.4.8 SPI_I2S register (SPI_I2SCTRL) .................................................215
13.4.9 SPI_I2S prescaler register (SPI_I2SCLKP) ..................................216

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14 Full-duplexed I2S (I2SF).............................................................. 217
14.1 I2SF introduction ....................................................................... 217
14.2 I2SF functional overview ............................................................ 217
14.2.1 I2SF full duplex mode.................................................................217
14.2.2 I2SF master clock sources..........................................................218
14.2.3 PCM mode .................................................................................219
14.2.4 Interrupts...................................................................................220
14.2.5 IO pin control .............................................................................220
14.2.6 Special notes on I2SF ................................................................220
14.3 I2SF registers............................................................................ 221
14.3.1 I2SF control register 2 (I2SF_CTRL2)..........................................221
14.3.2 I2SF status register (I2SF_STS) ...............................................221
14.3.3 I2SF data register (I2SF_DT) ......................................................222
14.3.4 I2SF register (I2SF_I2SCTRL) ....................................................222
14.3.5 I2SF prescaler register (I2SF_I2SCLKP)......................................223
14.3.6 I2SF additional register (I2SF_MISC1) ........................................223
15 Timer .......................................................................................... 224
15.1 Basic timer (TMR6 and TMR7) .................................................... 225
15.1.1 TMR6 and TMR7 introduction......................................................225
15.1.2 TMR6 and TMR7 main features ...................................................225
15.1.3 TMR6 and TMR7 function overview .............................................225
15.1.3.1 Counting clock...................................................................... 225
15.1.3.2 Counting mode ..................................................................... 225
15.1.3.3 Debug mode ......................................................................... 227
15.1.4 TMR6 and TMR7 registers ..........................................................227
15.1.4.1 TMR6 and TMR7 control register1 (TMRx_CTRL1)................... 227
15.1.4.2 TMR6 and TMR7 control register2 (TMRx_CTRL2)................... 228
15.1.4.3 TMR6 and TMR7 DMA/interrupt enable register (TMRx_IDEN) .. 228
15.1.4.4 TMR6 and TMR7 interrupt status register (TMRx_ISTS) ........... 228
15.1.4.5 TMR6 and TMR7 software event register (TMRx_SWEVT) ........ 228
15.1.4.6 TMR6 and TMR7 counter value (TMRx_CVAL) ........................ 228
15.1.4.7 TMR6 and TMR7 division (TMRx_DIV) .................................... 228
15.1.4.8 TMR6 and TMR7 period register (TMRx_PR) ........................... 229
15.2 General-purpose timer (TMR2 to TMR4) ...................................... 229

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15.2.1 TMR2 to TMR4 introduction ........................................................229
15.2.2 TMR2 to TMR4 main features......................................................229
15.2.3 TMR2 to TMR4 functional overview .............................................229
15.2.3.1 Counting clock...................................................................... 229
15.2.3.2 Counting mode ..................................................................... 233
15.2.3.3 TMR input function................................................................ 236
15.2.3.4 TMR output function.............................................................. 238
15.2.3.5 TMR synchronization............................................................. 242
15.2.3.6 Debug mode ......................................................................... 244
15.2.4 TMR2 to TMR4 registers.............................................................244
15.2.4.1 Control register 1 (TMRx_CTRL1) .......................................... 245
15.2.4.2 Control register 2 (TMRx_CTRL2) .......................................... 246
15.2.4.3 Slave timer control register (TMRx_STCTRL) .......................... 246
15.2.4.4 DMA/interrupt enable register (TMRx_IDEN) ........................... 247
15.2.4.5 Interrupt status register (TMRx_ISTS) .................................... 248
15.2.4.6 Software event register (TMRx_SWEVT) ................................. 249
15.2.4.7 Channel mode register1 (TMRx_CM1) .................................... 249
15.2.4.8 Channel mode register2 (TMRx_CM2) .................................... 251
15.2.4.9 Channel control register (TMRx_CCTRL) ................................ 252
15.2.4.10 Counter value (TMRx_CVAL) ............................................. 253
15.2.4.11 Frequency division value (TMRx_DIV) ................................ 253
15.2.4.12 Period register (TMRx_PR) ................................................ 253
15.2.4.13 Channel 1 data register (TMRx_C1DT) ............................... 253
15.2.4.14 Channel 2 data register (TMRx_C2DT) ............................... 254
15.2.4.15 Channel 3 data register (TMRx_C3DT) ............................... 254
15.2.4.16 Channel 4 data register (TMRx_C4DT) ............................... 254
15.2.4.17 DMA control register (TMRx_DMACTRL) ............................. 254
15.2.4.18 DMA data register (TMRx_DMADT) .................................... 255
15.2.4.19 TMR2 channel input remap register (TMR2_RMP)................ 255
15.3 General-purpose timer (TMR9).................................................... 255
15.3.1 TMR9 introduction ......................................................................255
15.3.2 TMR9 main features ...................................................................255
15.3.3 TMR9 functional overview...........................................................256
15.3.3.1 Counting clock...................................................................... 256
15.3.3.2 Counting mode ..................................................................... 259
15.3.3.3 TMR input function................................................................ 263
15.3.3.4 TMR output function.............................................................. 266

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15.3.3.5 TMR break function............................................................... 269
15.3.3.6 TMR synchronization............................................................. 270
15.3.3.7 Debug mode ......................................................................... 271
15.3.4 TMR9 registers ..........................................................................271
15.3.4.1 TMR9 control register1 (TMRx_CTRL1) .................................. 272
15.3.4.2 TMR9 control register 2 (TMRx_CTRL2) ................................. 273
15.3.4.3 TMR9 slave timer control register (TMRx_STCTRL) ................. 273
15.3.4.4 TMR9 DMA/interrupt enable register (TMRx_IDEN).................. 274
15.3.4.5 TMR9 interrupt status register (TMRx_ISTS) ........................... 274
15.3.4.6 TMR9 software event register (TMRx_SWEVT)........................ 275
15.3.4.7 TMR9 channel mode register 1 (TMRx_CM1)........................... 276
15.3.4.8 TMR9 channel control register (TMRx_CCTRL) ....................... 278
15.3.4.9 TMR9 counter value (TMRx_CVAL) ........................................ 280
15.3.4.10 TMR9 division value (TMRx_DIV) ....................................... 280
15.3.4.11 TMR9 period register (TMRx_PR)....................................... 280
15.3.4.12 TMR9 repetition period register (TMRx_RPR) ...................... 280
15.3.4.13 TMR9 channel 1 data register (TMRx_C1DT)....................... 280
15.3.4.14 TMR9 channel 2 data register (TMRx_C2DT)....................... 280
15.3.4.15 TMR9 break register (TMRx_BRK)...................................... 280
15.3.4.16 TMR9 DMA control register (TMRx_DMACTRL) ................... 282
15.3.4.17 TMR9 DMA data register (TMRx_DMADT) ........................... 282
15.4 General-purpose timer (TMR10/11/13/14) .................................... 283
15.4.1 TMRx introduction ......................................................................283
15.4.2 TMRx main features ...................................................................283
15.4.3 TMRx functional overview ...........................................................283
15.4.3.1 Counting clock...................................................................... 283
15.4.3.2 Counting mode ..................................................................... 284
15.4.3.3 TMR input function................................................................ 287
15.4.3.4 TMR output function.............................................................. 288
15.4.3.5 TMR break function............................................................... 291
15.4.3.6 Debug mode ......................................................................... 292
15.4.4 TMRx registers...........................................................................293
15.4.4.1 TMRx control register1 (TMRx_CTRL1) (x=10/11/13/14)........... 293
15.4.4.2 TMRx control register 2 (TMRx_CTRL2) (x=10/11/13/14).......... 294
15.4.4.3 TMRx DMA/interrupt enable register (TMRx_IDEN) (x=10/11/13/14)294
15.4.4.4 TMRx interrupt status register (TMRx_ISTS) (x=10/11/13/14) ... 295
15.4.4.5 TMRx software event register (TMRx_SWEVT) (x=10/11/13/14) 295

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15.4.4.6 TMRx channel mode register1 (TMRx_CM1) (x=10/11/13/14).... 296
15.4.4.7 TMRx Channel control register (TMRx_CCTRL) (x=10/11/13/14) 297
15.4.4.8 TMRx counter value (TMRx_CVAL) (x=10/11/13/14)................. 300
15.4.4.9 TMRx division value (TMRx_DIV) (x=10/11/13/14) ................... 300
15.4.4.10 TMRx period register (TMRx_PR) (x=10/11/13/14) ............... 300
15.4.4.11 TMRx repetition period register (TMRx_RPR) (x=10/11/13/14)300
15.4.4.12 TMRx channel 1 data register (TMRx_C1DT) (x=10/11/13/14)300
15.4.4.13 TMRx break register (TMRx_BRK) (x=10/11/13/14) .............. 300
15.4.4.14 TMRX DMA control register (TMRX_DMACTRL) (X=10/11/13/14)302
15.4.4.15 TMRx DMA data register (TMRx_DMADT) (X=10/11/13/14)... 302
15.4.4.16 TMR14 channel input remap register (TMRx_RMP) .............. 302
15.5 Advanced-control timers (TMR1) ................................................. 303
15.5.1 TMR1 introduction ......................................................................303
15.5.2 TMR1 main features ...................................................................303
15.5.3 TMR1 functional overview...........................................................303
15.5.3.1 Counting clock...................................................................... 303
15.5.3.2 Counting mode ..................................................................... 306
15.5.3.3 TMR input function................................................................ 311
15.5.3.4 TMR output function.............................................................. 313
15.5.3.5 TMR break function............................................................... 317
15.5.3.6 TMR synchronization............................................................. 318
15.5.3.7 Debug mode ......................................................................... 320
15.5.4 TMR1 registers ..........................................................................320
15.5.4.1 TMR1 control register1 (TMR1_CTRL1) .................................. 320
15.5.4.2 TMR1 control register2 (TMR1_CTRL2) .................................. 321
15.5.4.3 TMR1 slave timer control register (TMR1_STCTRL) ................. 322
15.5.4.4 TMR1 DMA/interrupt enable register (TMR1_IDEN).................. 323
15.5.4.5 TMR1 interrupt status register (TMR1_ISTS) ........................... 324
15.5.4.6 TMR1 software event register (TMR1_SWEVT)........................ 325
15.5.4.7 TMR1 channel mode register1 (TMR1_CM1) ........................... 325
15.5.4.8 TMR1 channel mode register2 (TMR1_CM2) ........................... 327
15.5.4.9 TMR1 channel control register (TMR1_CCTRL) ....................... 328
15.5.4.10 TMR1 counter value (TMR1_CVAL) .................................... 330
15.5.4.11 TMR1 division value (TMR1_DIV) ....................................... 330
15.5.4.12 TMR1 period register (TMR1_PR)....................................... 330
15.5.4.13 TMR1 repetition period register (TMR1_RPR)...................... 330
15.5.4.14 TMR1 channel 1 data register (TMR1_C1DT) ...................... 330

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15.5.4.15 TMR1 channel 2 data register (TMR1_C2DT) ...................... 331
15.5.4.16 TMR1 channel 3 data register (TMR1_C3DT) ...................... 331
15.5.4.17 TMR1 channel 4 data register (TMRx_C4DT)....................... 331
15.5.4.18 TMR1 break register (TMR1_BRK)...................................... 331
15.5.4.19 TMR1 DMA control register (TMR1_DMACTRL) ................... 332
15.5.4.20 TMR1 DMA data register (TMR1_DMADT)........................... 333
15.5.4.21 TMR1 channel mode register3 (TMR1_ CM3) ...................... 333
15.5.4.22 TMR1 channel 5 data register (TMR1_C5DT) ...................... 333
16 Window watchdog timer (WWDT) ................................................ 334
16.1 WWDT introduction .................................................................... 334
16.2 WWDT main features ................................................................. 334
16.3 WWDT functional overview ......................................................... 334
16.4 Debug mode.............................................................................. 335
16.5 WWDT registers ........................................................................ 335
16.5.1 Control register (WWDT_CTRL) ..................................................335
16.5.2 Configuration register (WWDT_CFG)...........................................336
16.5.3 Status register (WWDT_STS)......................................................336
17 Watchdog timer (WDT) ................................................................ 337
17.1 WDT introduction ....................................................................... 337
17.2 WDT main features .................................................................... 337
17.3 WDT functional overview ............................................................ 337
17.4 Debug mode.............................................................................. 338
17.5 WDT registers ........................................................................... 338
17.5.1 Command register (WDT_CMD) ..................................................339
17.5.2 Divider register (WDT_DIV).........................................................339
17.5.3 Reload register (WDT_RLD)........................................................339
17.5.4 Status register (WDT_STS).........................................................339
17.5.5 Window register (WDT_WIN).......................................................340
18 Enhanced real-time clock (ERTC) ............................................... 341
18.1 ERTC introduction...................................................................... 341
18.2 ERTC main features................................................................... 341
18.3 ERTC function overview ............................................................. 342

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18.3.1 ERTC clock................................................................................342
18.3.2 ERTC initialization......................................................................342
18.3.3 Periodic automatic wakeup .........................................................344
18.3.4 ERTC calibration ........................................................................344
18.3.5 Reference clock detection...........................................................345
18.3.6 Time stamp function ...................................................................345
18.3.7 Tamper detection .......................................................................346
18.3.8 Multiplexed function output .........................................................346
18.3.9 ERTC wakeup ............................................................................347
18.4 ERTC registers.......................................................................... 348
18.4.1 ERTC time register (ERTC_TIME) ...............................................348
18.4.2 ERTC date register (ERTC_DATE) ..............................................349
18.4.3 ERTC control register (ERTC_CTRL)...........................................349
18.4.4 ERTC initialization and status register (ERTC_STS).....................350
18.4.5 ERTC divider register (ERTC_DIV)..............................................352
18.4.6 ERTC wakeup timer register (ERTC_WAT) ..................................352
18.4.7 ERTC alarm clock A register (ERTC_ALA) ...................................352
18.4.8 ERTC alarm clock B register (ERTC_ALB) ...................................352
18.4.9 ERTC write protection register (ERTC_WP) .................................353
18.4.10 ERTC subsecond register (ERTC_SBS) ....................................353
18.4.11 ERTC time adjustment register (ERTC_TADJ) ...........................353
18.4.12 ERTC time stamp time register (ERTC_TSTM) ..........................353
18.4.13 ERTC time stamp date register (ERTC_TSDT) ..........................354
18.4.14 ERTC time stamp subsecond register (ERTC_TSSBS)...............354
18.4.15 ERTC smooth calibration register (ERTC_SCAL) .......................354
18.4.16 ERTC tamper configuration register (ERTC_TAMP) ...................355
18.4.17 ERTC alarm clock A subsecond register (ERTC_ALASBS) .........356
18.4.18 ERTC alarm clock B subsecond register (ERTC_ALBSBS) .........356
18.4.19 ERTC battery powered domain data register (ERTC_BPRx) .......356
19 Analog-to-digital converter (ADC)............................................... 357
19.1 ADC introduction ....................................................................... 357
19.2 ADC main features..................................................................... 357
19.3 ADC structure............................................................................ 358
19.4 ADC functional overview............................................................. 359

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19.4.1 Channel management .................................................................359
19.4.1.1 Internal temperature sensor ................................................... 359
19.4.1.2 Internal reference voltage...................................................... 359
19.4.2 ADC operation process...............................................................359
19.4.2.1 Power-on and calibration ....................................................... 360
19.4.2.2 Trigger................................................................................. 361
19.4.2.3 Sampling and conversion sequence........................................ 361
19.4.3 Conversion sequence management .............................................362
19.4.3.1 Sequence mode .................................................................... 362
19.4.3.2 Preempted group automatic conversion mode ......................... 362
19.4.3.3 Repetition mode.................................................................... 363
19.4.3.4 Partition mode ...................................................................... 363
19.4.4 Oversampling.............................................................................364
19.4.4.1 Oversampling of ordinary group of channels............................ 364
19.4.4.2 Oversampling of preempted group of channels ........................ 365
19.4.5 Data management ......................................................................366
19.4.5.1 Data alignment ..................................................................... 366
19.4.5.2 Data read ............................................................................. 366
19.4.6 Voltage monitoring .....................................................................366
19.4.7 Status flag and interrupts............................................................367
19.5 ADC registers............................................................................ 367
19.5.1 ADC status register (ADC_STS) ..................................................368
19.5.2 ADC control register1 (ADC_CTRL1) ...........................................368
19.5.3 ADC control register2 (ADC_CTRL2) ...........................................370
19.5.4 ADC sampling time register 1 (ADC_SPT1)..................................371
19.5.5 ADC sampling time register 2 (ADC_SPT2)..................................372
19.5.6 ADC preempted channel data offset register x
(ADC_ PCDTOx) (x=1..4)......................................................................375
19.5.7 ADC voltage monitoring high threshold register (ADC_VWHB) ......375
19.5.8 ADC voltage monitor low threshold register (ADC_ VWLB)............375
19.5.9 ADC ordinary sequence register 1 (ADC_ OSQ1) .........................375
19.5.10 ADC ordinary sequence register 2 (ADC_ OSQ2) ......................375
19.5.11 ADC ordinary sequence register 3 (ADC_ OSQ3) ......................376
19.5.12 ADC preempted sequence register (ADC_PSQ).........................376
19.5.13 ADC preempted data register x (ADC_ PDTx) (x=1..4) ...............376
19.5.14 ADC ordinary data register (ADC_ ODT) ...................................376

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19.5.15 ADC oversampling register (ADC_OVSP)..................................377
19.5.16 ADC common control register (ADC_CCTRL) ............................377
20 Controller area network (CAN) .................................................... 378
20.1 CAN introduction ....................................................................... 378
20.2 CAN main features..................................................................... 378
20.3 Baud rate .................................................................................. 378
20.4 Interrupt management ................................................................ 381
20.5 Design tips ................................................................................ 382
20.6 Functional overview ................................................................... 382
20.6.1 General description ....................................................................382
20.6.2 Operating modes........................................................................383
20.6.3 Test modes................................................................................384
20.6.4 Message filtering........................................................................384
20.6.5 Message transmission ................................................................387
20.6.6 Message reception .....................................................................388
20.6.7 Error management......................................................................389
20.7 CAN registers............................................................................ 389
20.7.1 CAN control and status registers.................................................391
20.7.1.1 CAN master control register (CAN_MCTRL) ............................ 391
20.7.1.2 CAN master status register (CAN_MSTS)................................ 392
20.7.1.3 CAN transmit status register (CAN_TSTS) .............................. 393
20.7.1.4 CAN receive FIFO 0 register (CAN_RF0) ................................ 396
20.7.1.5 CAN receive FIFO 1 register (CAN_RF1) ................................ 396
20.7.1.6 CAN interrupt enable register (CAN_INTEN) ........................... 397
20.7.1.7 CAN error status register (CAN_ESTS) ................................... 399
20.7.1.8 CAN bit timing register (CAN_BTMG) ..................................... 399
20.7.2 CAN mailbox registers ................................................................400
20.7.2.1 Transmit mailbox identifier register (CAN_TMIx) (x=0..2) ......... 400
20.7.2.2 Transmit mailbox data length and time stamp register
(CAN_TMCx) (x=0..2)......................................................................... 401
20.7.2.3 Transmit mailbox data low register (CAN_TMDTLx) (x=0..2) ..... 401
20.7.2.4 Transmit mailbox data high register (CAN_TMDTHx) (x=0..2) ... 401
20.7.2.5 Receive FIFO mailbox identifier register (CAN_RFIx) (x=0..1) .. 401
20.7.2.6 Receive FIFO mailbox data length and time stamp register
(CAN_RFCx) (x=0..1) ......................................................................... 402

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20.7.2.7 Receive FIFO mailbox data low register (CAN_RFDTLx) (x=0..1)402
20.7.2.8 Receive FIFO mailbox data high register (CAN_RFDTHx) (x=0..1)402
20.7.3 CAN filter registers.....................................................................402
20.7.3.1 CAN filter control register (CAN_FCTRL) ................................ 402
20.7.3.2 CAN filter mode configuration register (CAN_FMCFG) ............. 402
20.7.3.3 CAN filter bit width configuration register (CAN_ FBWCFG)...... 403
20.7.3.4 CAN filter FIFO association register (CAN_ FRF) .................... 403
20.7.3.5 CAN filter activation control register (CAN_ FACFG)................ 403
20.7.3.6 CAN filter bank i filter bit register (CAN_ FiFBx) (i=0..13; x=1..2)403
21 USB full-speed/high-speed device interface (OTGFS/HS) ........... 404
21.1 OTGFS/OTGHS structure ........................................................... 404
21.2 OTGFS/HS functional description................................................ 405
21.3 OTGFS/HS clock and pin configuration........................................ 406
21.3.1 OTGFS clock configuration .........................................................406
21.3.2 OTGHS clock configuration.........................................................406
21.3.3 OTGFS/HS pin configuration.......................................................406
21.4 OTGFS/HS interrupts ................................................................. 407
21.5 OTGFS/HS functional description................................................ 408
21.5.1 OTGFS/HS initialization..............................................................408
21.5.2 OTGFS/HS FIFO configuration ....................................................408
21.5.2.1 Device mode ........................................................................ 408
21.5.2.2 Host mode............................................................................ 409
21.5.2.3 Refresh controller transmit FIFO ............................................ 410
21.5.3 OTGFS /HS host mode ...............................................................410
21.5.3.1 Host initialization .................................................................. 411
21.5.3.2 OTGFS channel initialization.................................................. 411
21.5.3.3 Halting a channel.................................................................. 411
21.5.3.4 Queue depth......................................................................... 412
21.5.3.5 Special cases ....................................................................... 413
21.5.3.6 Host HFIR feature ................................................................. 414
21.5.3.7 Initialize bulk and control IN transfers..................................... 415
21.5.3.8 Initialize bulk and control OUT/SETUP transfers...................... 417
21.5.3.9 Initialize interrupt IN transfers................................................ 419
21.5.3.10 Initialize interrupt OUT transfers ........................................ 421
21.5.3.11 Initialize synchronous IN transfers...................................... 423
21.5.3.12 Initialize synchronous OUT transfers .................................. 425

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21.5.4 OTGFS/HS device mode .............................................................426
21.5.4.1 Device initialization............................................................... 426
21.5.4.2Endpoint initialization on USB reset........................................ 426
21.5.4.3 Endpoint initialization on enumeration completion.................... 427
21.5.4.4 Endpoint initialization on SetAddress command....................... 427
21.5.4.5 Endpoint initialization on SetConfiguration/SetInterface command427
21.5.4.6 Endpoint activation ............................................................... 428
21.5.4.7 USB endpoint deactivation..................................................... 428
21.5.4.8 Control write transfers (SETUP/Data OUT/Status IN) ............... 428
21.5.4.9 Control read transfers (SETUP/Data IN/Status OUT)................ 429
21.5.4.10 Control transfers (SETUP/Status IN)................................... 429
21.5.4.11 Read FIFO packets ........................................................... 429
21.5.4.12 OUT data transfers ........................................................... 431
21.5.4.13 IN data transfers............................................................... 432
21.5.4.14 Non-periodic (bulk and control) IN data transfers................. 433
21.5.4.15 Non-synchronous OUT data transfers ................................. 434
21.5.4.16 Synchronous OUT data transfers........................................ 436
21.5.4.17 Enable synchronous endpoints........................................... 438
21.5.4.18 Incomplete synchronous OUT data transfers ....................... 439
21.5.4.19 Incomplete synchronous IN data transfers........................... 440
21.5.4.20 Periodic IN (interrupt and synchronous) data transfers ......... 440
21.6 OTGFS control and status registers............................................. 442
21.6.1 CSR register map.......................................................................442
21.6.2 OTGFS/HS register address map ................................................443
21.6.3 OTGFS/HS global registers.........................................................448
21.6.3.1 OTGFS/HS status and control register (OTGFS/HS_GOTGCTL) 449
21.6.3.2 OTGFS/HS interrupt status control register (OTGFS/HS_GOTGINT)449
21.6.3.3 OTGFS/HS AHB configuration register (OTGFS/HS_GAHBCFG) 449
21.6.3.4 OTGFS/HS USB configuration register (OTGFS/HS_GUSBCFG) 450
21.6.3.5 OTGFS/HS reset register (OTGFS/HS_GRSTCTL) ................... 451
21.6.3.6 OTGFS/HS interrupt register (OTGFS/HS_GINTSTS) ............... 453
21.6.3.7 OTGFS/HS interrupt mask register (OTGFS/HS_GINTMSK)...... 456
21.6.3.8 OTGFS/HS receive status debug read/OTG status read and POP
registers (OTGFS/HS_GRXSTSR / OTGFS/HS_GRXSTSP) ................... 457
21.6.3.9 OTGFS/HS receive FIFO size register (OTGFS/HS_GRXFSIZ) . 458
21.6.3.10 OTGFS/HS non-periodic Tx FIFO size
(OTGFS/HS_GNPTXFSIZ)/Endpoint 0 Tx FIFO size registers
(OTGFS/HS_DIEPTXF0)..................................................................... 458