ARTERY AT32F413 Series User manual

AT32F413 Series Reference Manual
2022.06.27 Page 1 Rev 2.00
ARM®-based 32-bit Cortex®-M4F MCU+FPU with 64 to 25 KB Flash, sLib,
USB, 2 CANs, 12 timers, 3 ADCs, 13 communication interfaces
Feature
Core: ARM®32-bit Cortex®-M4F CPU with FPU
−200 MHz maximum frequency, with a Memory
Protection Unit (MPU), single-cycle multiplication
and hardware division
−Floating Point Unit (FPU)
−DSP instructions
Memories
−64 to 256 KBytes of Flash memory
−sLib: configurable part of main Flash set as a library
area with code excutable but secured, non-readable
−SPIM interface: extra interfacing up to 16 Mbytes of
external SPI Flash (as instruction/data memory)
−Up to 64 KBytes of SRAM
Clock, Reset, and Power management
−2.6 V ~ 3.6 V application suppy and I/Os
−Power on reset (POR)/ low voltage reset (LVR), and
power voltage monitor (PVM)
−4 to 25 MHz crystal (HEXT)
−Internal 48 MHz factory-trimmed RC (accuracy 1%
at TA=25 °C, 2.5 % at TA=-40 to +105 °C), with
automatic clock calibration (ACC)
−Internal 40 kHz RC oscillator (LICK)
−32.768 kHz crystal oscillator (LEXT)
Low power consumption
−Sleep, Deepsleep, and Standby modes
−VBAT supply for RTC and 42 x 16-bit battery powered
registers (BPR)
2 x 12-bit 0.5 μs A/D converters, up to 16 channels
−Conversion range: 0 V to 3.6 V
−Dual sample and hold capability
−Temparature sensor
DMA: 12-channel DMA controller
−Peripherals supported: timers, ADCs, SDIOs,
I2Ss, SPIs, I2Cs, and USARTs
Debug mode
−Serial wire debug (SWD) and JTAG interface
Up to 55 fast I/O Interfaces
−27/39/55 multifunctional and bidirectional I/Os, all
mappable to 16 external interrupt vectors and almost 5
V-tolerant
−All fast I/Os, control registers accessable with fAHB speed
Up to 12 Timers
−Up to5 x 16-bit timers +2 x 32-bit timers; each with 4
IC/OC/PWMor pulse counter andquadrature
(incremental) encoder input.
−Up to2 x 16-bit motor control PWMadvanced timers
with dead-time generator and emergency brake
−2 x Watchdog timers
−SysTick timer: 24-bitdowncounter
Up to 13 Communication Interfaces
−Up to2 x I2C interfaces (SMBus/PMBus)
−Up to5 x USARTs (ISO7816 interface, LIN, IrDA
capability, and modemcontrol)
−Up to2 x SPIs (can be used as I2S)
−Up to2 x CAN interfaces (2.0B Active)
−USB2.0 full-speed interface supporting Crystal-less
−SDIO
CRC Calculation Unit
96-bit unique ID (UID)
Packages
−LQFP64 10x10 mm
−LQFP64 7x7 mm
−QFN48 6 x 6 mm
−QFN32 4x4 mm
List of Models
Internal Flash
Model
256 KBytes
AT32F413RCT7, AT32F413CCT7,
AT32F413CCU7, AT32F413KCU7
128 KBytes
AT32F413RBT7, AT32F413CBT7,
AT32F413CBU7, AT32F413KBU7
64 KBytes
AT32F413C8T7

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Contents
1System architecture...................................................................... 26
1.1 System overview..........................................................................27
1.1.1 ARM CortexTM-M4F processor...................................................... 27
1.1.2 Bit band...................................................................................... 28
1.1.3 Interrupt and exception vectors .................................................... 30
1.1.4 System Tick (SysTick) ................................................................. 33
1.1.5 Reset ......................................................................................... 33
1.2 List of abbreviations for registers ..................................................35
1.3 Device characteristics information.................................................35
1.3.1 Flash memory size register .......................................................... 35
1.3.2 Device electronic signature.......................................................... 35
2Memory resources ........................................................................ 36
2.1 Internal memory address map .......................................................36
2.2 Flash memory..............................................................................37
2.3 SRAM memory.............................................................................38
2.4 Peripheral address map................................................................38
3Power control (PWC)..................................................................... 40
3.1 Introduction .................................................................................40
3.2 Main Features .............................................................................40
3.3 POR/LVR ....................................................................................41
3.4 Power voltage monitor (PVM)........................................................41
3.5 Power domain..............................................................................42
3.6 Power saving modes ....................................................................42
3.7 PWC registers .............................................................................44
3.7.1 Power control register (PWC_CTRL) ............................................ 44
3.7.2 Power control/status register (PWC_CTRLSTS) ............................ 45
4Clock and reset management (CRM) ............................................. 46
4.1 Clock ..........................................................................................46

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4.1.1 Clock sources ............................................................................. 46
4.1.2 System clock............................................................................... 47
4.1.3 Peripheral clock .......................................................................... 47
4.1.4 Clock fail detector ....................................................................... 48
4.1.5 Auto step-by-step system clock switch.......................................... 48
4.1.6 Internal clock output.................................................................... 48
4.1.7 Interrupts.................................................................................... 48
4.2 Reset..........................................................................................48
4.2.1 System reset............................................................................... 48
4.2.2 Battery powered domain reset...................................................... 49
4.3 CRM registers .............................................................................49
4.3.1 Clock control register (CRM_CTRL).............................................. 50
4.3.2 Clock configuration register (CRM_CFG) ...................................... 51
4.3.3 Clock interrupt register (CRM_CLKINT) ........................................ 53
4.3.4 APB2 peripheral reset register (CRM_APB2RST) .......................... 54
4.3.5 APB1 peripheral reset register (CRM_APB1RST) .......................... 55
4.3.6 APB peripheral clock enable register (CRM_AHBEN)..................... 56
4.3.7 APB2 peripheral clock enable register (CRM_AHB2EN) ................. 57
4.3.8 APB1 peripheral clock enable register (CRM_AHB1EN) ................. 58
4.3.9 Battery powered domain control register (CRM_BPDC).................. 59
4.3.10 Control/status register (CRM_CTRLSTS) ...................................... 60
4.3.11 Additional register1 (CRM_MISC1) ............................................... 61
4.3.12 Additional register2 (CRM_MISC2) ............................................... 61
4.3.13 Additional register3 (CRM_MISC3) ............................................... 62
4.3.14 Interrupt map register (CRM_INTMAP) ......................................... 62
5Flash memory controller (FLASH)................................................. 63
5.1 Flash memory introduction............................................................63
5.2 Flash memory operation ...............................................................67
5.2.1 Unlock/lock ................................................................................. 67
5.2.2 Erase operation........................................................................... 67
5.2.3 Programming operation................................................................ 70
5.2.4 Read operation ........................................................................... 71
5.3 External memory operation ...........................................................71
5.4 User system data area operation...................................................71

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5.4.1 Unlock/lock ................................................................................. 71
5.4.2 Erase operation........................................................................... 71
5.4.3 Programming operation................................................................ 72
5.4.4 Read operation ........................................................................... 73
5.5 Flash memory protection ..............................................................73
5.5.1 Access protection........................................................................ 74
5.5.2 Erase/program protection............................................................. 74
5.6 Special functions .........................................................................75
5.6.1 Security library settings ............................................................... 75
5.7 Flash memory registers ................................................................76
5.7.1 Flash performance select register (FLASH_PSR) .......................... 76
5.7.2 Flash unlock register (FLASH_UNLOCK) ...................................... 77
5.7.3 Flash user system data unlock register (FLASH_USD_UNLOCK) ... 77
5.7.4 Flash status register (FLASH_STS) .............................................. 77
5.7.5 Flash control register (FLASH_CTRL)........................................... 77
5.7.6 Flash address register (FLASH_ADDR) ........................................ 78
5.7.7 User system data register (FLASH_USD)...................................... 78
5.7.8 Erase/program protection status register (FLASH_EPPS) .............. 78
5.7.9 Flash unlock register3 (FLASH_UNLOCK3)................................... 79
5.7.10 Flash select register (FLASH_SELECT)........................................ 79
5.7.11 Flash status register3 (FLASH_STS3) .......................................... 79
5.7.12 Flash control register3 (FLASH_CTRL3) ....................................... 79
5.7.13 Flash address register3 (FLASH_ADDR3)..................................... 80
5.7.14 Flash decrption address register (FLASH_DA) .............................. 80
5.7.15 Flash security library status register 0 (SLIB_STS0)...................... 80
5.7.16 Flash security library status register 1 (SLIB_STS1)...................... 81
5.7.17 Flash security library password clear register (SLIB_PWD_CLR).... 81
5.7.18 Security library additional status register (SLIB_MISC_STS).......... 81
5.7.19 Security library password setting register (SLIB_SET_PWD).......... 82
5.7.20 Security library address setting register (SLIB_SET_RANGE) ........ 82
5.7.21 Security library unlock register (SLIB_UNLOCK) ........................... 82
5.7.22 Flash CRC check control register (FLASH_CRC_CTRL) ................ 83
5.7.23 Flash CRC check result register (FLASH_CRC_CHKR).................. 83
6General-purpose I/Os (GPIOs)....................................................... 84

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6.1 Introduction .................................................................................84
6.2 Function overview........................................................................84
6.2.1 GPIO structure ............................................................................ 84
6.2.2 GPIO reset status........................................................................ 85
6.2.3 General-purpose input configuration............................................. 85
6.2.4 Analog input/output configuration ................................................. 85
6.2.5 General-purpose output configuration........................................... 85
6.2.6 I/O port protection ....................................................................... 85
6.3 GPIO registers.............................................................................86
6.3.1 GPIO configuration register low (GPIOx_CFGLR) (x=A..F)............. 86
6.3.2 GPIO configuration register high (GPIOx_CFGHR) (A..F)............... 87
6.3.3 GPIO input data register (GPIOx_IDT) (x=A..F)............................. 87
6.3.4 GPIO output data register (GPIOx_ODT) (x=A..F) ......................... 87
6.3.5 GPIO set/clear register (GPIOx_SCR) (x=A..F) ............................. 88
6.3.6 GPIO clear register (GPIOx_CLR) (x=A..F) ................................... 88
6.3.7 GPIO write protection register (GPIOx_WPR) (x=A..F)................... 88
7Multiplexed function I/Os (IOMUX) ................................................ 89
7.1 Introduction .................................................................................89
7.2 Function overview........................................................................89
7.2.1 IOMUX structure ......................................................................... 89
7.2.2 Multiplexed input configuration..................................................... 90
7.2.3 Multiplexed output or bidirectional multiplexed configuration.......... 90
7.2.4 Peripheral multiplexed function configuration ................................ 90
7.2.5 IOMUX map priority ..................................................................... 90
7.2.5.1 Hardware preemption .............................................................. 91
7.2.5.2 Debug port priority .................................................................. 91
7.2.5.3 Other peripheral output priority ................................................ 91
7.2.6 External interrupt/wake-up lines ................................................... 91
7.3 IOMUX registers ..........................................................................92
7.3.1 Event output control register (IOMUX_EVTOUT) ........................... 92
7.3.2 IOMUX remap register (IOMUX_REMAP) ...................................... 93
7.3.3 IOMUX external interrupt configuration register1 (IOMUX_EXINTC1)95
7.3.4 IOMUX external interrupt configuration register2 (IOMUX_EXINTC2)96
7.3.5 IOMUX external interrupt configuration register3 (IOMUX_EXINTC3)96

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7.3.6 IOMUX external interrupt configuration register4 (IOMUX_EXINTC4)97
7.3.7 IOMUX remap register2 (IOMUX_REMAP2) .................................. 98
7.3.8 IOMUX remap register3 (IOMUX_REMAP3) .................................. 98
7.3.9 IOMUX remap register4 (IOMUX_REMAP4) .................................. 98
7.3.10 IOMUX remap register5 (IOMUX_REMAP5) .................................. 99
7.3.11 IOMUX remap register6 (IOMUX_REMAP6) .................................. 99
7.3.12 IOMUX remap register7 (IOMUX_REMAP7) .................................100
8External interrupt/Event controller (EXINT) ................................ 102
8.1 EXINT introduction..................................................................... 102
8.2 Function overview and configuration procedure ............................ 102
8.3 EXINT registers ......................................................................... 103
8.3.1 Interrupt enable register (EXINT_INTEN).....................................103
8.3.2 Event enable register (EXINT_EVTEN) ........................................103
8.3.3 Polarity configuration register1 (EXINT_ POLCFG1).....................103
8.3.4 Polarity configuration register2 (EXINT_ POLCFG2).....................103
8.3.5 Software trigger register (EXINT_ SWTRG)..................................104
8.3.6 Interrupt status register (EXINT_ INTSTS) ...................................104
9DMA controller (DMA) ................................................................. 105
9.1 Introduction ............................................................................... 105
9.2 Main features ............................................................................ 105
9.3 Function overview...................................................................... 106
9.3.1 DMA configuration......................................................................106
9.3.2 Handshake mechanism...............................................................106
9.3.3 Arbiter .......................................................................................106
9.3.4 Programmable data transfer width ...............................................107
9.3.5 Errors ........................................................................................108
9.3.6 Interrupts...................................................................................108
9.3.7 Fixed DMA request mapping .......................................................108
9.3.8 Flexible DMA request mapping....................................................109
9.4 DMA registers............................................................................ 110
9.4.1 DMA interrupt status register (DMA_STS) ....................................111
9.4.2 DMA interrupt flag clear register (DMA_CLR) ...............................113
9.4.3 DMA channelx configuration register (DMA_CxCTRL) (x = 1…7) ...115

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9.4.4 DMA channelx number of data register (DMA_CxDTCNT) (x = 1…7)116
9.4.5 DMA channelx peripheral address register (DMA_CxPADDR)
(x = 1…7) ............................................................................................116
9.4.6 DMA channelx memory address register (DMA_CxMADDR)
(x = 1…7) ............................................................................................116
9.4.7 Channel source register (DMA_SRC_SEL0) .................................116
9.4.8 Channel source register1 (DMA_SRC_SEL1) ...............................117
10 CRC calculation unit (CRC)......................................................... 118
10.1 CRC introduction ....................................................................... 118
10.2 CRC registers............................................................................ 118
10.2.1 Data register (CRC_DT)..............................................................118
10.2.2 Common data register (CRC_CDT)..............................................118
10.2.3 Control register (CRC_CTRL)......................................................119
10.2.4 Initialization register (CRC_IDT) .................................................119
11 I2C interface ................................................................................ 120
11.1 I2C introduction.......................................................................... 120
11.2 I2C main features....................................................................... 120
11.3 I2C function overview ................................................................. 120
11.4 I2C interface .............................................................................. 121
11.4.1 I2C slave communication flow......................................................123
11.4.2 I2C master communication flow ...................................................125
11.4.3 Utilize DMA for data transfer.......................................................131
11.4.4 SMBus.......................................................................................132
11.4.5 I2C interrupt requests .................................................................133
11.4.6 I2C debug mode .........................................................................134
11.5 I2C registers .............................................................................. 134
11.5.1 Control register1 (I2C_CTRL1)....................................................134
11.5.2 Control register2 (I2C_CTRL2)....................................................136
11.5.3 Own address register1 (I2C_OADDR1) ........................................136
11.5.4 Own address register2 (I2C_OADDR2) ........................................137
11.5.5 Data register (I2C_DT) ...............................................................137
11.5.6 Status register1 (I2C_STS1) .......................................................137
11.5.7 Status register2 (I2C_STS2) .......................................................139

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11.5.8 Clock control register (I2C_ CLKCTRL) .......................................140
12 Universal synchronous/asynchronous receiver/transmitter (USART)142
12.1 USART introduction ................................................................... 142
12.2 Full-duplex/half-duplex selector .................................................. 144
12.3 Mode selector............................................................................ 144
12.3.1 Introduction................................................................................144
12.3.2 Configuration procedure .............................................................144
12.4 USART frame format and configuration........................................ 145
12.5 DMA transfer introduction ........................................................... 147
12.5.1 Transmission using DMA ............................................................147
12.5.2 Reception using DMA .................................................................147
12.6 Baud rate generation.................................................................. 148
12.6.1 Introduction................................................................................148
12.6.2 Configuration .............................................................................148
12.7 Transmitter................................................................................ 148
12.7.1 Transmitter introduction..............................................................148
12.7.2 Transmitter configuration ............................................................149
12.8 Receiver ................................................................................... 149
12.8.1 Receiver introduction..................................................................149
12.8.2 Receiver configuration................................................................150
12.8.3 Start bit and noise detection .......................................................151
12.9 Interrupt requests ...................................................................... 152
12.10I/O pin control............................................................................ 152
12.11USART registers........................................................................ 153
12.11.1 Status register (USART_STS) ..................................................153
12.11.2 Data register (USART_DT).......................................................154
12.11.3 Baud rate register (USART_BAUDR) ........................................154
12.11.4 Control register1 (USART_CTRL1) ...........................................154
12.11.5 Control register2 (USART_CTRL2) ...........................................156
12.11.6 Control register3 (USART_CTRL3) ...........................................157
12.11.7 Guard time and divider register (GDIV) .....................................158
13 Serial peripheral interface (SPI).................................................. 159
13.1 SPI introduction......................................................................... 159

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13.2 Function overview...................................................................... 159
13.2.1 SPI description...........................................................................159
13.2.2 Full-duplex/half-duplex selector ..................................................160
13.2.3 Chip select controller..................................................................162
13.2.4 SPI_SCK controller ....................................................................162
13.2.5 CRC ..........................................................................................162
13.2.6 DMA transfer..............................................................................163
13.2.7 Transmitter ................................................................................164
13.2.8 Receiver ....................................................................................164
13.2.9 Motorola mode ...........................................................................165
13.2.10 Interrrupts...............................................................................167
13.2.11 IO pin control ..........................................................................167
13.2.12 Precautions.............................................................................168
13.3 I2S functional description............................................................ 168
13.3.1 I2S introduction ..........................................................................168
13.3.2 Operation mode selector.............................................................169
13.3.3 Audio protocol selector ...............................................................170
13.3.4 I2S_CLK controller .....................................................................171
13.3.5 DMA transfer..............................................................................174
13.3.6 Transmitter/Receiver ..................................................................174
13.3.7 I2S communication timings .........................................................175
13.3.8 Interrupts...................................................................................176
13.3.9 IO pin control .............................................................................176
13.4 SPI registers ............................................................................. 177
13.4.1 SPI control register1 (SPI_CTRL1) (Not used in I2S mode) ...........177
13.4.2 SPI control register2 (SPI_CTRL2)..............................................178
13.4.3 SPI status register (SPI_STS) .....................................................179
13.4.4 SPI data register (SPI_DT) .........................................................180
13.4.5 SPICRC register (SPI_CPOLY) (Not used in I2S mode).................180
13.4.6 SPIRxCRC register (SPI_RCRC) (Not used in I2S mode)..............180
13.4.7 SPITxCRC register (SPI_TCRC)..................................................180
13.4.8 SPI_I2S register (SPI_I2SCTRL) .................................................180
13.4.9 SPI_I2S prescaler register (SPI_I2SCLKP) ..................................181
14 Timer .......................................................................................... 182

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14.1 General-purpose timer (TMR2 to TMR5) ...................................... 182
14.1.1 TMRx introduction ......................................................................182
14.1.2 TMRx main features ...................................................................183
14.1.3 TMRx functional overview ...........................................................183
14.1.3.1 Count clock .......................................................................... 183
14.1.3.2 Counting mode ..................................................................... 185
14.1.3.3 TMR input function................................................................ 187
14.1.3.4 TMR output function.............................................................. 188
14.1.3.5 TMR synchronization............................................................. 191
14.1.3.6 Debug mode ......................................................................... 194
14.1.4 TMRx registers...........................................................................194
14.1.4.1 Control register1 (TMRx_CTRL1) ........................................... 195
14.1.4.2 Control register2 (TMRx_CTRL2) ........................................... 196
14.1.4.3 Slave timer control register (TMRx_STCTRL) .......................... 196
14.1.4.4 DMA/interrupt enable register (TMRx_IDEN) ........................... 197
14.1.4.5 Interrupt status register (TMRx_ISTS) .................................... 198
14.1.4.6 Software event register (TMRx_SWEVT) ................................. 199
14.1.4.7 Channel mode register1 (TMRx_CM1) .................................... 200
14.1.4.8 Channel mode register2 (TMRx_CM2) .................................... 202
14.1.4.9 Channel control register (TMRx_CCTRL) ................................ 203
14.1.4.10 Counter value (TMRx_CVAL) ............................................. 204
14.1.4.11 Division value (TMRx_DIV) ................................................ 204
14.1.4.12 Period register (TMRx_PR) ................................................ 204
14.1.4.13 Channel 1 data register (TMRx_C1DT) ............................... 204
14.1.4.14 Channel 2 data register (TMRx_C2DT) ............................... 204
14.1.4.15 Channel 3 data register (TMRx_C3DT) ............................... 205
14.1.4.16 Channel 4 data register (TMRx_C4DT) ............................... 205
14.1.4.17 DMA control register (TMRx_DMACTRL) ............................. 205
14.1.4.18 DMA data register (TMRx_DMADT) .................................... 206
14.2 General-purpose timer (TMR9 to TMR11) .................................... 206
14.2.1 TMRx introduction ......................................................................206
14.2.2 TMRx main features ...................................................................206
14.2.2.1 TMR9 main features .............................................................. 206
14.2.2.2 TMR10 and TMR11 main features .......................................... 206
14.2.3 TMRx functional overview ...........................................................207
14.2.3.1 Count clock .......................................................................... 207
14.2.3.2 Counting mode ..................................................................... 208