ARTERY AT32F413 Series User manual

AT32F413 Series Reference Manual
2022.06.27 Page 1 Rev 2.00
ARM®-based 32-bit Cortex®-M4F MCU+FPU with 64 to 25 KB Flash, sLib,
USB, 2 CANs, 12 timers, 3 ADCs, 13 communication interfaces
Feature
Core: ARM®32-bit Cortex®-M4F CPU with FPU
−200 MHz maximum frequency, with a Memory
Protection Unit (MPU), single-cycle multiplication
and hardware division
−Floating Point Unit (FPU)
−DSP instructions
Memories
−64 to 256 KBytes of Flash memory
−sLib: configurable part of main Flash set as a library
area with code excutable but secured, non-readable
−SPIM interface: extra interfacing up to 16 Mbytes of
external SPI Flash (as instruction/data memory)
−Up to 64 KBytes of SRAM
Clock, Reset, and Power management
−2.6 V ~ 3.6 V application suppy and I/Os
−Power on reset (POR)/ low voltage reset (LVR), and
power voltage monitor (PVM)
−4 to 25 MHz crystal (HEXT)
−Internal 48 MHz factory-trimmed RC (accuracy 1%
at TA=25 °C, 2.5 % at TA=-40 to +105 °C), with
automatic clock calibration (ACC)
−Internal 40 kHz RC oscillator (LICK)
−32.768 kHz crystal oscillator (LEXT)
Low power consumption
−Sleep, Deepsleep, and Standby modes
−VBAT supply for RTC and 42 x 16-bit battery powered
registers (BPR)
2 x 12-bit 0.5 μs A/D converters, up to 16 channels
−Conversion range: 0 V to 3.6 V
−Dual sample and hold capability
−Temparature sensor
DMA: 12-channel DMA controller
−Peripherals supported: timers, ADCs, SDIOs,
I2Ss, SPIs, I2Cs, and USARTs
Debug mode
−Serial wire debug (SWD) and JTAG interface
Up to 55 fast I/O Interfaces
−27/39/55 multifunctional and bidirectional I/Os, all
mappable to 16 external interrupt vectors and almost 5
V-tolerant
−All fast I/Os, control registers accessable with fAHB speed
Up to 12 Timers
−Up to5 x 16-bit timers +2 x 32-bit timers; each with 4
IC/OC/PWMor pulse counter andquadrature
(incremental) encoder input.
−Up to2 x 16-bit motor control PWMadvanced timers
with dead-time generator and emergency brake
−2 x Watchdog timers
−SysTick timer: 24-bitdowncounter
Up to 13 Communication Interfaces
−Up to2 x I2C interfaces (SMBus/PMBus)
−Up to5 x USARTs (ISO7816 interface, LIN, IrDA
capability, and modemcontrol)
−Up to2 x SPIs (can be used as I2S)
−Up to2 x CAN interfaces (2.0B Active)
−USB2.0 full-speed interface supporting Crystal-less
−SDIO
CRC Calculation Unit
96-bit unique ID (UID)
Packages
−LQFP64 10x10 mm
−LQFP64 7x7 mm
−QFN48 6 x 6 mm
−QFN32 4x4 mm
List of Models
Internal Flash
Model
256 KBytes
AT32F413RCT7, AT32F413CCT7,
AT32F413CCU7, AT32F413KCU7
128 KBytes
AT32F413RBT7, AT32F413CBT7,
AT32F413CBU7, AT32F413KBU7
64 KBytes
AT32F413C8T7

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Contents
1System architecture...................................................................... 26
1.1 System overview..........................................................................27
1.1.1 ARM CortexTM-M4F processor...................................................... 27
1.1.2 Bit band...................................................................................... 28
1.1.3 Interrupt and exception vectors .................................................... 30
1.1.4 System Tick (SysTick) ................................................................. 33
1.1.5 Reset ......................................................................................... 33
1.2 List of abbreviations for registers ..................................................35
1.3 Device characteristics information.................................................35
1.3.1 Flash memory size register .......................................................... 35
1.3.2 Device electronic signature.......................................................... 35
2Memory resources ........................................................................ 36
2.1 Internal memory address map .......................................................36
2.2 Flash memory..............................................................................37
2.3 SRAM memory.............................................................................38
2.4 Peripheral address map................................................................38
3Power control (PWC)..................................................................... 40
3.1 Introduction .................................................................................40
3.2 Main Features .............................................................................40
3.3 POR/LVR ....................................................................................41
3.4 Power voltage monitor (PVM)........................................................41
3.5 Power domain..............................................................................42
3.6 Power saving modes ....................................................................42
3.7 PWC registers .............................................................................44
3.7.1 Power control register (PWC_CTRL) ............................................ 44
3.7.2 Power control/status register (PWC_CTRLSTS) ............................ 45
4Clock and reset management (CRM) ............................................. 46
4.1 Clock ..........................................................................................46

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4.1.1 Clock sources ............................................................................. 46
4.1.2 System clock............................................................................... 47
4.1.3 Peripheral clock .......................................................................... 47
4.1.4 Clock fail detector ....................................................................... 48
4.1.5 Auto step-by-step system clock switch.......................................... 48
4.1.6 Internal clock output.................................................................... 48
4.1.7 Interrupts.................................................................................... 48
4.2 Reset..........................................................................................48
4.2.1 System reset............................................................................... 48
4.2.2 Battery powered domain reset...................................................... 49
4.3 CRM registers .............................................................................49
4.3.1 Clock control register (CRM_CTRL).............................................. 50
4.3.2 Clock configuration register (CRM_CFG) ...................................... 51
4.3.3 Clock interrupt register (CRM_CLKINT) ........................................ 53
4.3.4 APB2 peripheral reset register (CRM_APB2RST) .......................... 54
4.3.5 APB1 peripheral reset register (CRM_APB1RST) .......................... 55
4.3.6 APB peripheral clock enable register (CRM_AHBEN)..................... 56
4.3.7 APB2 peripheral clock enable register (CRM_AHB2EN) ................. 57
4.3.8 APB1 peripheral clock enable register (CRM_AHB1EN) ................. 58
4.3.9 Battery powered domain control register (CRM_BPDC).................. 59
4.3.10 Control/status register (CRM_CTRLSTS) ...................................... 60
4.3.11 Additional register1 (CRM_MISC1) ............................................... 61
4.3.12 Additional register2 (CRM_MISC2) ............................................... 61
4.3.13 Additional register3 (CRM_MISC3) ............................................... 62
4.3.14 Interrupt map register (CRM_INTMAP) ......................................... 62
5Flash memory controller (FLASH)................................................. 63
5.1 Flash memory introduction............................................................63
5.2 Flash memory operation ...............................................................67
5.2.1 Unlock/lock ................................................................................. 67
5.2.2 Erase operation........................................................................... 67
5.2.3 Programming operation................................................................ 70
5.2.4 Read operation ........................................................................... 71
5.3 External memory operation ...........................................................71
5.4 User system data area operation...................................................71

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5.4.1 Unlock/lock ................................................................................. 71
5.4.2 Erase operation........................................................................... 71
5.4.3 Programming operation................................................................ 72
5.4.4 Read operation ........................................................................... 73
5.5 Flash memory protection ..............................................................73
5.5.1 Access protection........................................................................ 74
5.5.2 Erase/program protection............................................................. 74
5.6 Special functions .........................................................................75
5.6.1 Security library settings ............................................................... 75
5.7 Flash memory registers ................................................................76
5.7.1 Flash performance select register (FLASH_PSR) .......................... 76
5.7.2 Flash unlock register (FLASH_UNLOCK) ...................................... 77
5.7.3 Flash user system data unlock register (FLASH_USD_UNLOCK) ... 77
5.7.4 Flash status register (FLASH_STS) .............................................. 77
5.7.5 Flash control register (FLASH_CTRL)........................................... 77
5.7.6 Flash address register (FLASH_ADDR) ........................................ 78
5.7.7 User system data register (FLASH_USD)...................................... 78
5.7.8 Erase/program protection status register (FLASH_EPPS) .............. 78
5.7.9 Flash unlock register3 (FLASH_UNLOCK3)................................... 79
5.7.10 Flash select register (FLASH_SELECT)........................................ 79
5.7.11 Flash status register3 (FLASH_STS3) .......................................... 79
5.7.12 Flash control register3 (FLASH_CTRL3) ....................................... 79
5.7.13 Flash address register3 (FLASH_ADDR3)..................................... 80
5.7.14 Flash decrption address register (FLASH_DA) .............................. 80
5.7.15 Flash security library status register 0 (SLIB_STS0)...................... 80
5.7.16 Flash security library status register 1 (SLIB_STS1)...................... 81
5.7.17 Flash security library password clear register (SLIB_PWD_CLR).... 81
5.7.18 Security library additional status register (SLIB_MISC_STS).......... 81
5.7.19 Security library password setting register (SLIB_SET_PWD).......... 82
5.7.20 Security library address setting register (SLIB_SET_RANGE) ........ 82
5.7.21 Security library unlock register (SLIB_UNLOCK) ........................... 82
5.7.22 Flash CRC check control register (FLASH_CRC_CTRL) ................ 83
5.7.23 Flash CRC check result register (FLASH_CRC_CHKR).................. 83
6General-purpose I/Os (GPIOs)....................................................... 84

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6.1 Introduction .................................................................................84
6.2 Function overview........................................................................84
6.2.1 GPIO structure ............................................................................ 84
6.2.2 GPIO reset status........................................................................ 85
6.2.3 General-purpose input configuration............................................. 85
6.2.4 Analog input/output configuration ................................................. 85
6.2.5 General-purpose output configuration........................................... 85
6.2.6 I/O port protection ....................................................................... 85
6.3 GPIO registers.............................................................................86
6.3.1 GPIO configuration register low (GPIOx_CFGLR) (x=A..F)............. 86
6.3.2 GPIO configuration register high (GPIOx_CFGHR) (A..F)............... 87
6.3.3 GPIO input data register (GPIOx_IDT) (x=A..F)............................. 87
6.3.4 GPIO output data register (GPIOx_ODT) (x=A..F) ......................... 87
6.3.5 GPIO set/clear register (GPIOx_SCR) (x=A..F) ............................. 88
6.3.6 GPIO clear register (GPIOx_CLR) (x=A..F) ................................... 88
6.3.7 GPIO write protection register (GPIOx_WPR) (x=A..F)................... 88
7Multiplexed function I/Os (IOMUX) ................................................ 89
7.1 Introduction .................................................................................89
7.2 Function overview........................................................................89
7.2.1 IOMUX structure ......................................................................... 89
7.2.2 Multiplexed input configuration..................................................... 90
7.2.3 Multiplexed output or bidirectional multiplexed configuration.......... 90
7.2.4 Peripheral multiplexed function configuration ................................ 90
7.2.5 IOMUX map priority ..................................................................... 90
7.2.5.1 Hardware preemption .............................................................. 91
7.2.5.2 Debug port priority .................................................................. 91
7.2.5.3 Other peripheral output priority ................................................ 91
7.2.6 External interrupt/wake-up lines ................................................... 91
7.3 IOMUX registers ..........................................................................92
7.3.1 Event output control register (IOMUX_EVTOUT) ........................... 92
7.3.2 IOMUX remap register (IOMUX_REMAP) ...................................... 93
7.3.3 IOMUX external interrupt configuration register1 (IOMUX_EXINTC1)95
7.3.4 IOMUX external interrupt configuration register2 (IOMUX_EXINTC2)96
7.3.5 IOMUX external interrupt configuration register3 (IOMUX_EXINTC3)96

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7.3.6 IOMUX external interrupt configuration register4 (IOMUX_EXINTC4)97
7.3.7 IOMUX remap register2 (IOMUX_REMAP2) .................................. 98
7.3.8 IOMUX remap register3 (IOMUX_REMAP3) .................................. 98
7.3.9 IOMUX remap register4 (IOMUX_REMAP4) .................................. 98
7.3.10 IOMUX remap register5 (IOMUX_REMAP5) .................................. 99
7.3.11 IOMUX remap register6 (IOMUX_REMAP6) .................................. 99
7.3.12 IOMUX remap register7 (IOMUX_REMAP7) .................................100
8External interrupt/Event controller (EXINT) ................................ 102
8.1 EXINT introduction..................................................................... 102
8.2 Function overview and configuration procedure ............................ 102
8.3 EXINT registers ......................................................................... 103
8.3.1 Interrupt enable register (EXINT_INTEN).....................................103
8.3.2 Event enable register (EXINT_EVTEN) ........................................103
8.3.3 Polarity configuration register1 (EXINT_ POLCFG1).....................103
8.3.4 Polarity configuration register2 (EXINT_ POLCFG2).....................103
8.3.5 Software trigger register (EXINT_ SWTRG)..................................104
8.3.6 Interrupt status register (EXINT_ INTSTS) ...................................104
9DMA controller (DMA) ................................................................. 105
9.1 Introduction ............................................................................... 105
9.2 Main features ............................................................................ 105
9.3 Function overview...................................................................... 106
9.3.1 DMA configuration......................................................................106
9.3.2 Handshake mechanism...............................................................106
9.3.3 Arbiter .......................................................................................106
9.3.4 Programmable data transfer width ...............................................107
9.3.5 Errors ........................................................................................108
9.3.6 Interrupts...................................................................................108
9.3.7 Fixed DMA request mapping .......................................................108
9.3.8 Flexible DMA request mapping....................................................109
9.4 DMA registers............................................................................ 110
9.4.1 DMA interrupt status register (DMA_STS) ....................................111
9.4.2 DMA interrupt flag clear register (DMA_CLR) ...............................113
9.4.3 DMA channelx configuration register (DMA_CxCTRL) (x = 1…7) ...115

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9.4.4 DMA channelx number of data register (DMA_CxDTCNT) (x = 1…7)116
9.4.5 DMA channelx peripheral address register (DMA_CxPADDR)
(x = 1…7) ............................................................................................116
9.4.6 DMA channelx memory address register (DMA_CxMADDR)
(x = 1…7) ............................................................................................116
9.4.7 Channel source register (DMA_SRC_SEL0) .................................116
9.4.8 Channel source register1 (DMA_SRC_SEL1) ...............................117
10 CRC calculation unit (CRC)......................................................... 118
10.1 CRC introduction ....................................................................... 118
10.2 CRC registers............................................................................ 118
10.2.1 Data register (CRC_DT)..............................................................118
10.2.2 Common data register (CRC_CDT)..............................................118
10.2.3 Control register (CRC_CTRL)......................................................119
10.2.4 Initialization register (CRC_IDT) .................................................119
11 I2C interface ................................................................................ 120
11.1 I2C introduction.......................................................................... 120
11.2 I2C main features....................................................................... 120
11.3 I2C function overview ................................................................. 120
11.4 I2C interface .............................................................................. 121
11.4.1 I2C slave communication flow......................................................123
11.4.2 I2C master communication flow ...................................................125
11.4.3 Utilize DMA for data transfer.......................................................131
11.4.4 SMBus.......................................................................................132
11.4.5 I2C interrupt requests .................................................................133
11.4.6 I2C debug mode .........................................................................134
11.5 I2C registers .............................................................................. 134
11.5.1 Control register1 (I2C_CTRL1)....................................................134
11.5.2 Control register2 (I2C_CTRL2)....................................................136
11.5.3 Own address register1 (I2C_OADDR1) ........................................136
11.5.4 Own address register2 (I2C_OADDR2) ........................................137
11.5.5 Data register (I2C_DT) ...............................................................137
11.5.6 Status register1 (I2C_STS1) .......................................................137
11.5.7 Status register2 (I2C_STS2) .......................................................139

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11.5.8 Clock control register (I2C_ CLKCTRL) .......................................140
12 Universal synchronous/asynchronous receiver/transmitter (USART)142
12.1 USART introduction ................................................................... 142
12.2 Full-duplex/half-duplex selector .................................................. 144
12.3 Mode selector............................................................................ 144
12.3.1 Introduction................................................................................144
12.3.2 Configuration procedure .............................................................144
12.4 USART frame format and configuration........................................ 145
12.5 DMA transfer introduction ........................................................... 147
12.5.1 Transmission using DMA ............................................................147
12.5.2 Reception using DMA .................................................................147
12.6 Baud rate generation.................................................................. 148
12.6.1 Introduction................................................................................148
12.6.2 Configuration .............................................................................148
12.7 Transmitter................................................................................ 148
12.7.1 Transmitter introduction..............................................................148
12.7.2 Transmitter configuration ............................................................149
12.8 Receiver ................................................................................... 149
12.8.1 Receiver introduction..................................................................149
12.8.2 Receiver configuration................................................................150
12.8.3 Start bit and noise detection .......................................................151
12.9 Interrupt requests ...................................................................... 152
12.10I/O pin control............................................................................ 152
12.11USART registers........................................................................ 153
12.11.1 Status register (USART_STS) ..................................................153
12.11.2 Data register (USART_DT).......................................................154
12.11.3 Baud rate register (USART_BAUDR) ........................................154
12.11.4 Control register1 (USART_CTRL1) ...........................................154
12.11.5 Control register2 (USART_CTRL2) ...........................................156
12.11.6 Control register3 (USART_CTRL3) ...........................................157
12.11.7 Guard time and divider register (GDIV) .....................................158
13 Serial peripheral interface (SPI).................................................. 159
13.1 SPI introduction......................................................................... 159

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13.2 Function overview...................................................................... 159
13.2.1 SPI description...........................................................................159
13.2.2 Full-duplex/half-duplex selector ..................................................160
13.2.3 Chip select controller..................................................................162
13.2.4 SPI_SCK controller ....................................................................162
13.2.5 CRC ..........................................................................................162
13.2.6 DMA transfer..............................................................................163
13.2.7 Transmitter ................................................................................164
13.2.8 Receiver ....................................................................................164
13.2.9 Motorola mode ...........................................................................165
13.2.10 Interrrupts...............................................................................167
13.2.11 IO pin control ..........................................................................167
13.2.12 Precautions.............................................................................168
13.3 I2S functional description............................................................ 168
13.3.1 I2S introduction ..........................................................................168
13.3.2 Operation mode selector.............................................................169
13.3.3 Audio protocol selector ...............................................................170
13.3.4 I2S_CLK controller .....................................................................171
13.3.5 DMA transfer..............................................................................174
13.3.6 Transmitter/Receiver ..................................................................174
13.3.7 I2S communication timings .........................................................175
13.3.8 Interrupts...................................................................................176
13.3.9 IO pin control .............................................................................176
13.4 SPI registers ............................................................................. 177
13.4.1 SPI control register1 (SPI_CTRL1) (Not used in I2S mode) ...........177
13.4.2 SPI control register2 (SPI_CTRL2)..............................................178
13.4.3 SPI status register (SPI_STS) .....................................................179
13.4.4 SPI data register (SPI_DT) .........................................................180
13.4.5 SPICRC register (SPI_CPOLY) (Not used in I2S mode).................180
13.4.6 SPIRxCRC register (SPI_RCRC) (Not used in I2S mode)..............180
13.4.7 SPITxCRC register (SPI_TCRC)..................................................180
13.4.8 SPI_I2S register (SPI_I2SCTRL) .................................................180
13.4.9 SPI_I2S prescaler register (SPI_I2SCLKP) ..................................181
14 Timer .......................................................................................... 182

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14.1 General-purpose timer (TMR2 to TMR5) ...................................... 182
14.1.1 TMRx introduction ......................................................................182
14.1.2 TMRx main features ...................................................................183
14.1.3 TMRx functional overview ...........................................................183
14.1.3.1 Count clock .......................................................................... 183
14.1.3.2 Counting mode ..................................................................... 185
14.1.3.3 TMR input function................................................................ 187
14.1.3.4 TMR output function.............................................................. 188
14.1.3.5 TMR synchronization............................................................. 191
14.1.3.6 Debug mode ......................................................................... 194
14.1.4 TMRx registers...........................................................................194
14.1.4.1 Control register1 (TMRx_CTRL1) ........................................... 195
14.1.4.2 Control register2 (TMRx_CTRL2) ........................................... 196
14.1.4.3 Slave timer control register (TMRx_STCTRL) .......................... 196
14.1.4.4 DMA/interrupt enable register (TMRx_IDEN) ........................... 197
14.1.4.5 Interrupt status register (TMRx_ISTS) .................................... 198
14.1.4.6 Software event register (TMRx_SWEVT) ................................. 199
14.1.4.7 Channel mode register1 (TMRx_CM1) .................................... 200
14.1.4.8 Channel mode register2 (TMRx_CM2) .................................... 202
14.1.4.9 Channel control register (TMRx_CCTRL) ................................ 203
14.1.4.10 Counter value (TMRx_CVAL) ............................................. 204
14.1.4.11 Division value (TMRx_DIV) ................................................ 204
14.1.4.12 Period register (TMRx_PR) ................................................ 204
14.1.4.13 Channel 1 data register (TMRx_C1DT) ............................... 204
14.1.4.14 Channel 2 data register (TMRx_C2DT) ............................... 204
14.1.4.15 Channel 3 data register (TMRx_C3DT) ............................... 205
14.1.4.16 Channel 4 data register (TMRx_C4DT) ............................... 205
14.1.4.17 DMA control register (TMRx_DMACTRL) ............................. 205
14.1.4.18 DMA data register (TMRx_DMADT) .................................... 206
14.2 General-purpose timer (TMR9 to TMR11) .................................... 206
14.2.1 TMRx introduction ......................................................................206
14.2.2 TMRx main features ...................................................................206
14.2.2.1 TMR9 main features .............................................................. 206
14.2.2.2 TMR10 and TMR11 main features .......................................... 206
14.2.3 TMRx functional overview ...........................................................207
14.2.3.1 Count clock .......................................................................... 207
14.2.3.2 Counting mode ..................................................................... 208

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14.2.3.3 TMR input function................................................................ 209
14.2.3.4 TMR output function.............................................................. 210
14.2.3.5 TMR synchronization............................................................. 212
14.2.3.6 Debug mode ......................................................................... 213
14.2.4 TMR9 registers ..........................................................................213
14.2.4.1 Control register1 (TMR9_CTRL1) ........................................... 213
14.2.4.2 Slave timer control register (TMR9_STCTRL) .......................... 214
14.2.4.3 DMA/interrupt enable register (TMR9_IDEN) ........................... 214
14.2.4.4 Interrupt status register (TMR9_ISTS) .................................... 215
14.2.4.5 Software event register (TMR9_SWEVT)................................. 215
14.2.4.6 Channel mode register1 (TMR9_CM1) .................................... 216
14.2.4.7 Channel control register (TMR9_CCTRL) ................................ 218
14.2.4.8 Counter value (TMR9_CVAL) ................................................. 219
14.2.4.9 Division value (TMR9_DIV) .................................................... 219
14.2.4.10 Period register (TMR9_PR)................................................ 219
14.2.4.11 Channel 1 data register (TMR9_C1DT) ............................... 219
14.2.4.12 Channel 2 data register (TMR9_C2DT) ............................... 219
14.2.5 TMR10 and TMR11 registers.......................................................220
14.2.5.1 Control register1 (TMRx_CTRL1) ........................................... 220
14.2.5.2 DMA/interrupt enable register (TMRx_IDEN) ........................... 221
14.2.5.3 Interrupt status register (TMRx_ISTS) .................................... 221
14.2.5.4 Software event register (TMRx_SWEVT) ................................. 221
14.2.5.5 Channel mode register1 (TMRx_CM1) .................................... 222
14.2.5.6 Channel control register (TMRx_CCTRL) ................................ 224
14.2.5.7 Counter value (TMRx_CVAL) ................................................. 224
14.2.5.8 Division value (TMRx_DIV) .................................................... 224
14.2.5.9 Period register (TMRx_PR) .................................................... 224
14.2.5.10 Channel 1 data register (TMRx_C1DT) ............................... 224
14.3 Advanced-control timers (TMR1 and TMR8) ................................. 225
14.3.1 TMR1 and TMR8 introduction......................................................225
14.3.2 TMR1 and TMR8 main features ...................................................225
14.3.3 TMR1 and TMR8 functional overview...........................................225
14.3.3.1 Count clock .......................................................................... 225
14.3.3.2 Counting mode ..................................................................... 227
14.3.3.3 TMR input function................................................................ 229
14.3.3.4 TMR output function.............................................................. 231
14.3.3.5 TMR break function............................................................... 234
14.3.3.6 TMR synchronization............................................................. 235

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14.3.3.7 Debug mode ......................................................................... 236
14.3.4 TMR1 and TMR8 registers ..........................................................236
14.3.4.1 TMR1 and TMR8 control register1 (TMRx_CTRL1)................... 237
14.3.4.2 TMR1 and TMR8 control register2 (TMRx_CTRL2)................... 238
14.3.4.3 TMR1 and TMR8 slave timer control register (TMRx_STCTRL) . 239
14.3.4.4 TMR1 and TMR8 DMA/interrupt enable register (TMRx_IDEN) .. 240
14.3.4.5 TMR1 and TMR8 interrupt status register (TMRx_ISTS) ........... 241
14.3.4.6 Software event register (TMRx_SWEVT)................................. 242
14.3.4.7 TMR1 and TMR8 channel mode register1 (TMRx_CM1)............ 243
14.3.4.8 Channel mode register2 (TMRx_CM2) .................................... 245
14.3.4.9 Channel control register (TMRx_CCTRL) ................................ 246
14.3.4.10 TMR1 and TMR8 counter value (TMRx_CVAL) ....................... 248
14.3.4.11 TMR1 and TMR8 division value (TMRx_DIV) ......................... 248
14.3.4.12 TMR1 and TMR8 period register (TMRx_PR) ......................... 248
14.3.4.13 TMR1 and TMR8 repetition period register (TMRx_RPR) ........ 248
14.3.4.14 TMR1 and TMR8 channel 1 data register (TMRx_C1DT) ......... 248
14.3.4.15 TMR1 and TMR8 channel 2 data register (TMRx_C2DT) ......... 249
14.3.4.16 TMR1 and TMR8 channel 3 data register (TMRx_C3DT) ......... 249
14.3.4.17 TMR1 and TMR8 channel 4 data register (TMRx_C4DT) ......... 249
14.3.4.18 TMR1 and TMR8 break register (TMRx_BRK) ........................ 249
14.3.4.19 TMR1 and TMR8 DMA control register (TMRx_ DMACTRL) .... 251
14.3.4.20 TMR1 and TMR8 DMA data register (TMRx_ DMADT) ............ 251
15 Window watchdog timer (WWDT) ................................................ 252
15.1 WWDT introduction .................................................................... 252
15.2 WWDT main features ................................................................. 252
15.3 WWDT functional overview ......................................................... 252
15.4 Debug mode.............................................................................. 253
15.5 WWDT registers ........................................................................ 253
15.5.1 Control register (WWDT_CTRL) ..................................................253
15.5.2 Configuration register (WWDT_CFG) ...........................................254
15.5.3 Status register (WWDT_STS)......................................................254
16 Watchdog timer (WDT) ................................................................ 255
16.1 WDT introduction ....................................................................... 255
16.2 WDT main features .................................................................... 255
16.3 WDT functional overview ............................................................ 255

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16.4 Debug mode.............................................................................. 256
16.5 WDT registers ........................................................................... 256
16.5.1 Command register (WDT_CMD) ..................................................257
16.5.2 Divider register (WDT_DIV).........................................................257
16.5.3 Reload register (WDT_RLD)........................................................257
16.5.4 Status register (WDT_STS).........................................................257
17 Real-time clock (RTC) ................................................................. 258
17.1 RTC introduction........................................................................ 258
17.2 RTC main features..................................................................... 258
17.3 RTC structure............................................................................ 258
17.4 RTC functional overview............................................................. 259
17.4.1 Configuring RTC registers...........................................................259
17.4.2 Reading RTC registers ...............................................................260
17.4.3 RTC interrupts ...........................................................................260
17.5 RTC registers ............................................................................ 261
17.5.1 RTC control register high (RTC_CTRLH) .....................................261
17.5.2 RTC control register low (RTC_CTRLL) .......................................262
17.5.3 RTC divider register (RTC_ DIVH/RTC_DIVL) ..............................262
17.5.4 RTC divider counter register (RTC_ DIVCNTH/RTC_DIVCNTL).....263
17.5.5 RTC counter value register (RTC_CNTH/RTC_CNTL) ...................263
17.5.6 RTC alarm register (RTC_TAH/RTC_TAL) ...................................263
18 Battery powered registers (BPR) ................................................ 264
18.1 BPR introduction........................................................................ 264
18.2 BPR main features..................................................................... 264
18.3 BPR functional overview............................................................. 264
18.4 BPR registers ............................................................................ 264
18.4.1 Battery powered data register x (BPR_DTx) (x = 1 … 42) .............265
18.4.2 RTC calibration register (BPR_ RTCCAL) ....................................266
18.4.3 BPR control register (BPR_ CTRL) ..............................................266
18.4.4 BPR control/status register (BPR_ CTRLSTS)..............................267
19 Analog-to-digital converter (ADC)............................................... 268
19.1 ADC introduction ....................................................................... 268

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19.2 ADC main features..................................................................... 268
19.3 ADC structure............................................................................ 268
19.4 ADC functional overview............................................................. 270
19.4.1 Channel management .................................................................270
19.4.1.1 Internal temperature sensor ................................................... 270
19.4.1.2 Internal reference voltage...................................................... 270
19.4.2 ADC operation process...............................................................271
19.4.2.1 Power-on and calibration ....................................................... 271
19.4.2.2 Trigger................................................................................. 272
19.4.2.3 Sampling and conversion sequence........................................ 273
19.4.3 Conversion sequence management .............................................273
19.4.3.1 Sequence mode .................................................................... 273
19.4.3.2 Automatic preempted group conversion mode ......................... 274
19.4.3.3 Repetition mode.................................................................... 274
19.4.3.4 Partition mode ...................................................................... 275
19.4.4 Data management ......................................................................276
19.4.4.1 Data alignment ..................................................................... 276
19.4.4.2 Data read ............................................................................. 276
19.4.5 Voltage monitor..........................................................................276
19.4.6 Status flag and interrupts............................................................276
19.5 Master/Slave mode .................................................................... 277
19.5.1 Data management ......................................................................277
19.5.2 Regular simultaneous mode ........................................................277
19.5.3 Interleaved trigger mode of preempted group ...............................278
19.5.4 Shift mode of regular group.........................................................279
19.6 ADC registers............................................................................ 280
19.6.1 ADC status register (ADC_STS)..................................................281
19.6.2 ADC control register1 (ADC_CTRL1) ...........................................281
19.6.3 ADC control register2 (ADC_CTRL2) ...........................................283
19.6.4 ADC sampling time register 1 (ADC_SPT1)..................................285
19.6.5 ADC sampling time register 2 (ADC_SPT2)..................................286
19.6.6 ADC preempted channel data offset register x
(ADC_PCDTOx) (x=1..4).......................................................................288
19.6.7 ADC voltage monitor high threshold register (ADC_VWHB)...........288
19.6.8 ADC voltage monitor low threshold register (ADC_VWLB).............288
19.6.9 ADC ordinary sequence register 1 (ADC_OSQ1) ..........................288

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19.6.10 ADC ordinary sequence register 2 (ADC_OSQ2) .......................289
19.6.11 ADC ordinary sequence register 3 (ADC_OSQ3) .......................289
19.6.12 ADC preempted sequence register (ADC_PSQ).........................289
19.6.13 ADC preempted data register x (ADC_PDTx) (x=1..4) ................290
19.6.14 ADC ordinary data register (ADC_ODT) ....................................290
20 CAN ............................................................................................ 291
20.1 CAN introduction ....................................................................... 291
20.2 CAN main features..................................................................... 291
20.3 Baud rate configuration .............................................................. 291
20.4 Interrupt management ................................................................ 294
20.5 Design tips ................................................................................ 295
20.6 Function overview...................................................................... 295
20.6.1 General functional description.....................................................295
20.6.2 Operating modes........................................................................296
20.6.3 Test modes................................................................................296
20.6.4 Message filtering........................................................................297
20.6.5 Message transmission ................................................................299
20.6.6 Message reception .....................................................................301
20.6.7 Error management......................................................................302
20.7 CAN registers............................................................................ 302
20.7.1 CAN control and status registers .................................................303
20.7.1.1 CAN master control register (CAN_MCTRL) ............................ 303
20.7.1.2 CAN master status register (CAN_MSTS)................................ 305
20.7.1.3 CAN transmit status register (CAN_TSTS) .............................. 306
20.7.1.4 CAN receive FIFO 0 register (CAN_RF0) ................................ 310
20.7.1.5 CAN receive FIFO 1 register (CAN_RF1) ................................ 310
20.7.1.6 CAN interrupt enable register (CAN_INTEN) ........................... 311
20.7.1.7 CAN error status register (CAN_ESTS) ................................... 313
20.7.1.8 CAN bit timing register (CAN_BTMG) ..................................... 314
20.7.2 CAN mailbox registers ................................................................314
20.7.2.1 Transmit mailbox identifier register (CAN_TMIx) (x=0..2) ......... 315
20.7.2.2 Transmit mailbox data length and time stamp register
(CAN_TMCx) (x=0..2)......................................................................... 315
20.7.2.3 Transmit mailbox data low register (CAN_TMDTLx) (x=0..2) ..... 316
20.7.2.4 Transmit mailbox data high register (CAN_TMDTHx) (x=0..2) ... 316

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20.7.2.5 Receive FIFO mailbox identifier register (CAN_RFIx) (x=0..1) .. 316
20.7.2.6 Receive FIFO mailbox data length and time stamp register
(CAN_RFCx) (x=0..1) ......................................................................... 316
20.7.2.7 Receive FIFO mailbox data low register (CAN_RFDTLx) (x=0..1)317
20.7.2.8 Receive FIFO mailbox data high register (CAN_RFDTHx) (x=0..1)317
20.7.3 CAN filter registers.....................................................................317
20.7.3.1 CAN filter control register (CAN_FCTRL) ................................ 317
20.7.3.2 CAN filter mode configuration register (CAN_FMCFG) ............. 317
20.7.3.3 CAN filter bit width configuration register (CAN_ FBWCFG)...... 317
20.7.3.4 CAN filter FIFO association register (CAN_ FRF) .................... 318
20.7.3.5 CAN filter activation control register (CAN_ FACFG) ................ 318
20.7.3.6 CAN filter bank i filter bit register (CAN_ FiFBx)
(i=0..13; x=1..2)................................................................................. 318
21 Universal serial bus full-seed device interface (USBFS) ............. 319
21.1 USBFS introduction.................................................................... 319
21.2 USBFS clock and pin configuration.............................................. 319
21.2.1 USB clock configuration..............................................................319
21.2.2 USB pin configuration.................................................................319
21.3 USBFS functional description...................................................... 319
21.3.1 USB initialization........................................................................319
21.3.2 Endpoint configuration................................................................320
21.3.3 USB buffer.................................................................................320
21.3.4 Double-buffered endpoints..........................................................321
21.3.5 SOF output ................................................................................322
21.3.6 Suspend/Resume .......................................................................322
21.4 USB interrupts........................................................................... 322
21.5 USBFS registers ........................................................................ 322
21.5.1 USBFS endpoint n register (USBFS_EPTn), n=[0..7] ....................323
21.5.2 USBFS control register (USBFS_CTRL).......................................324
21.5.3 USBFS interrupt status register (USBFS_INTSTS) .......................325
21.5.4 USBFS SOF frame number register (USBFS_SOFRNUM) .............326
21.5.5 USBFS device address register (USBFS_DEVADDR) ...................326
21.5.6 USBFS buffer table address register (USBFS_BUFTBL) ...............326
21.5.7 USBFS CFG control register (USBFS_CFG).................................326
21.5.8 USBFS transmission buffer first address register (USBFS_TnADDR)327

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21.5.9 USBFS transmission data length register (USBFS_TnLEN) ...........327
21.5.10 USBFS reception buffer first address register (USBFS_RnADDR)327
21.5.11 USBFS reception data length register (USBFS_RnLEN).............327
22 HICK auto clock calibration (ACC) .............................................. 328
22.1 ACC introduction ....................................................................... 328
22.2 Main features ............................................................................ 328
22.3 Interrupt requests ...................................................................... 328
22.4 Functional description ................................................................ 329
22.5 Principle.................................................................................... 330
22.6 Register description ................................................................... 331
22.6.1 Status register (ACC_STS) .........................................................331
22.6.2 Control register 1 (ACC_CTRL1) .................................................332
22.6.3 Control register 2 (ACC_CTRL2) .................................................333
22.6.4 Compare value 1 (ACC_C1) ........................................................333
22.6.5 Compare value 2 (ACC_C2) ........................................................333
22.6.6 Compare value 3 (ACC_C3) ........................................................333
23 SDIO interface............................................................................. 334
23.1 SDIO introduction ...................................................................... 334
23.2 SDIO main features.................................................................... 334
23.3 SDIO main features.................................................................... 336
23.3.1 Card functional description .........................................................336
23.3.1.1 Card identification mode........................................................ 336
23.3.1.2 Data transfer mode ............................................................... 337
23.3.1.3 Erase................................................................................... 338
23.3.1.4 Protection management ......................................................... 338
23.3.2 Commands and responses ..........................................................341
23.3.2.1 Commands ........................................................................... 341
23.3.2.2 Response formats ................................................................. 345
23.3.3 SDIO functional description ........................................................347
23.3.3.1 SDIO adapter ....................................................................... 348
23.3.3.2 Data BUF ............................................................................. 352
23.3.3.3 SDIO AHB interface .............................................................. 352
23.3.3.4 Hardware flow control............................................................ 353
23.3.4 SDIO I/O card-specific operations ...............................................353

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23.4 SDIO registers........................................................................... 354
23.4.1 SDIO power control register (SDIO_ PWRCTRL) ..........................354
23.4.2 SDIO clock control register (SDIO_ CLKCTRL) ............................355
23.4.3 SDIO argument register (SDIO_ARG) ..........................................356
23.4.4 SDIO command register (SDIO_CMD) .........................................356
23.4.5 SDIO command response register (SDIO_RSPCMD) ....................357
23.4.6 SDIO response 1..4 register (SDIO_RSPx) ..................................357
23.4.7 SDIO data timer register (SDIO_DTTMR).....................................357
23.4.8 SDIO data length register (SDIO_DTLEN)....................................357
23.4.9 SDIO data control register (SDIO_DTCTRL).................................358
23.4.10 SDIO data counter register (SDIO_DTCNTR) ............................359
23.4.11 SDIO status register (SDIO_STS).............................................359
23.4.12 SDIO clear interrupt register (SDIO_INTCLR)............................360
23.4.13 SDIO interrupt mask register (SDIO_INTEN) .............................361
23.4.14 SDIOBUF counter register (SDIO_BUFCNTR) ...........................363
23.4.15 SDIO data BUF register (SDIO_BUF)........................................363
24 Debug (DEBUG) .......................................................................... 364
24.1 Debug introduction..................................................................... 364
24.2 Debug and Trace ....................................................................... 364
24.3 I/O pin control............................................................................ 364
24.4 DEBUG registers ....................................................................... 365
24.4.1 DEBUG device ID (DEBUG_IDCODE)..........................................365
24.4.2 DEBUG control register (DEBUG_CTRL) .....................................366
25 Revision history.......................................................................... 368

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List of figures
Figure 1-1 AT32F413A Series microcontrollers system architecture .............................................................. 26
Figure 1-2 Internal block diagram of Cortex®-M4F...................................................................................... 27
Figure 1-3 Comparison between bit-band region and its alias region: image A ......................................... 28
Figure 1-4 Comparison between bit-band region and its alias region: image B......................................... 28
Figure 1-5 Reset process ............................................................................................................................ 33
Figure 1-6 Example of MSP and PC initialization........................................................................................ 34
Figure 2-1 AT32F413 address mapping ...................................................................................................... 36
Figure 3-1 Block diagram of each power supply ......................................................................................... 40
Figure 3-2 Power-on reset/Low voltage reset waveform............................................................................. 41
Figure 3-3 PVM threshold and output ......................................................................................................... 41
Figure 4-1 AT32F413 clock tree .................................................................................................................. 46
Figure 4-2 System reset circuit.................................................................................................................... 49
Figure 5-1 External memory ciphertext protection ...................................................................................... 64
Figure 5-2 Reference circuit for external memory....................................................................................... 65
Figure 5-3 Flash memory page erase process ........................................................................................... 68
Figure 5-4 Flash memory mass erase process........................................................................................... 69
Figure 5-5 Flash memory programming process ........................................................................................ 70
Figure 5-6 System data area erase process ............................................................................................... 72
Figure 5-7 System data area programming process................................................................................... 73
Figure 6-1 GPIO basic structure.................................................................................................................. 84
Figure 7-1 Basic structure of IOMUX basic structure.................................................................................. 89
Figure 8-1 External interrupt/Event controller block diagram.................................................................... 102
Figure 9-1 DMA block diagram.................................................................................................................. 105
Figure 9-2 Re-arbitrae after request/acknowledge.................................................................................... 107
Figure 9-3 PWIDTH: byte, MWIDTH: half-word ........................................................................................ 107
Figure 9-4 PWIDTH: half-word, MWIDTH: word ....................................................................................... 107
Figure 9-5 PWIDTH: word, MWIDTH: byte ............................................................................................... 108
Figure 11-1 I2C bus protocol ..................................................................................................................... 120
Figure 11-2 I2C function block diagram..................................................................................................... 121
Figure 11-3 Transfer sequence of slave transmitter.................................................................................. 123
Figure 11-4 Transfer sequence of slave receiver ...................................................................................... 124
Figure 11-5 Transfer sequence of master transmitter ............................................................................... 125
Figure 11-6 Transfer sequence of master receiver.................................................................................... 127
Figure 11-7 Transfer sequence of master receiver when N>2.................................................................. 128
Figure 11-8 Transfer sequence of master receiver when N=2.................................................................. 129
Figure 11-9 Transfer sequence of master receiver when N=1.................................................................. 130
Figure 12-1 USART block diagram............................................................................................................ 142
Figure 12-2 IrDA DATA(3/16) – normal mode ........................................................................................... 145
Figure 12-3 Word length............................................................................................................................ 146
Figure 12-4 Stop bit configuration ............................................................................................................. 146
Figure 12-5 TDC/TDBE behavior when transmitting................................................................................. 149
Figure 12-6 Data sampling for noise detection.......................................................................................... 152
Figure 12-7 USART interrupt map diagram............................................................................................... 152

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Figure 13-1 SPI block diagram.................................................................................................................. 159
Figure 13-2 SPI two-wire unidirectional full-duplex connection ................................................................ 160
Figure 13-3 Single-wire unidirectional receive only in SPI master mode.................................................. 160
Figure 13-4 Single-wire unidirectional receive only in SPI slave mode .................................................... 161
Figure 13-5 Single-wire bidirectional half-duplex mode ............................................................................ 161
Figure 13-6 Master full-duplex communications ....................................................................................... 165
Figure 13-7 Slave full-duplex communications.......................................................................................... 166
Figure 13-8 Slave full-duplex communications.......................................................................................... 166
Figure 13-9 Slave half-duplex receive....................................................................................................... 166
Figure 13-10 Slave half-duplex transmit.................................................................................................... 167
Figure 13-11 Master half-duplex receive ................................................................................................... 167
Figure 13-12 SPI interrupts ....................................................................................................................... 167
Figure 13-13 I2S block diagram ................................................................................................................. 168
Figure 13-14 I2S slave device transmission .............................................................................................. 169
Figure 13-15 I2S slave device reception.................................................................................................... 169
Figure 13-16 I2S master device transmission............................................................................................ 170
Figure 13-17 I2S master device reception................................................................................................. 170
Figure 13-18 CK & MCK source in master mode...................................................................................... 172
Figure 13-19 Audio standard timings......................................................................................................... 175
Figure 13-20 I2S interrupts......................................................................................................................... 176
Figure 14-1 General-purpose timer block diagram ................................................................................... 183
Figure 14-2 Control circuit with CK_INT divided by 1 ............................................................................... 183
Figure 14-3 Block diagram of external clock mode A................................................................................ 184
Figure 14-4 Counting in external clock mode A......................................................................................... 184
Figure 14-5 Block diagram of external clock mode B................................................................................ 184
Figure 14-6 Counting in external clock mode B ........................................................................................ 184
Figure 14-7 Counter timing with prescaler value changing from 1 to 4 .................................................... 185
Figure 14-8 Overflow event when PRBEN=0............................................................................................ 186
Figure 14-9 Overflow event when PRBEN=1............................................................................................ 186
Figure 14-10 Counter timing diagram with internal clock divided by 4 ..................................................... 186
Figure 14-11 Counter timing diagram with internal clock divided by 1 and TMRx_PR=0x32................... 186
Figure 14-12 Example of counter behavior in encoder interface mode (encoder mode C)...................... 187
Figure 14-13 Input/output channel 1 main circuit ...................................................................................... 187
Figure 14-14 Channel 1 input stage.......................................................................................................... 188
Figure 14-15 Capture/compare channel output stage (channel 1 to 4) .................................................... 188
Figure 14-16 C1ORAW toggles when counter value matches the C1DT value ....................................... 189
Figure 14-17 Upcounting mode and PWM mode A................................................................................... 190
Figure 14-18 Up/down counting mode and PWM mode A........................................................................ 190
Figure 14-19 One-pulse mode................................................................................................................... 190
Figure 14-20 Clearing CxORAW(PWM mode A) by EXT input.................................................................191
Figure 14-21 Example of reset mode........................................................................................................ 191
Figure 14-22 Example of suspend mode .................................................................................................. 192
Figure 14-23 Example of trigger mode...................................................................................................... 192
Figure 14-24 Master/slave timer connection ............................................................................................. 192
Figure 14-25 Using master timer to start slave timer ................................................................................ 193