ARTERY AT32F403A Series User manual

AT32F403A/407 Series Reference Manual
2021.12.01 Page 1 Ver 2.02
ARM®-based 32-bit Cortex®-M4F MCU+FPU with 256 to 1024 KB Flash, sLib,
USB, Ethernet, 2 CANs, 17 timers, 3 ADCs, 21 communication interfaces
Feature
Core: ARM®32-bit Cortex®-M4F CPU with FPU
−240 MHz maximum frequency, with a Memory
Protection Unit (MPU), single-cycle multiplication
and hardware division
−Floating Point Unit (FPU)
−DSP instructions
Memories
−256 to 1024 KBytes of Flash memory
−sLib: configurable part of main Flash set as a library
area with code excutable but secured, non-readable
−SPIM interface: extra interfacing up to 16 Mbytes of
external SPI Flash (as instruction/data memory)
−Up to 96 + 128 KBytes of SRAM
−External memory controller (XMC) with 2 Chip
Select, supports multiplexed SRAM/NOR/PSRAM
and NAND memories
−LCD parallel interface, 8080/6800 modes
Clock, Reset, and Power management
−2.6 V ~ 3.6 V application suppy and I/Os
−Power on reset (POR)/ low voltage reset (LVR), and
power voltage monitor (PVM)
−4 to 25 MHz crystal (HEXT)
−Internal 48 MHz factory-trimmed RC (accuracy 1%
at TA=25 °C, 2.5 % at TA=-40 to +105 °C), with
automatic clock calibration (ACC)
−Internal 40 kHz RC oscillator (LICK)
−32.768 kHz crystal oscillator (LEXT)
Low power consumption
−Sleep, Deepsleep, and Standby modes
−VBAT supply for RTC and 42 x 16-bit battery powered
registers (BPR)
3 x 12-bit 0.5 μs A/D converters, up to 16 channels
−Conversion range: 0 V to 3.6 V
−Triple sample and hold capability
−Temparature sensor
2 x 12-bit D/A converters
DMA: 14-channel DMA controller
−Peripherals supported: timers, ADCs, SDIOs,
I2Ss, SPIs, I2Cs, and USARTs
Debug Mode
−Serial wire debug (SWD) and JTAG interface
−Cortex®-M4F Embedded Trace Macrocell (ETMTM)
Up to 80 Fast I/O Interfaces
−37/51/80multifunctional and bidirectional I/Os, all
mappable to 16 external interrupt vectors and almost 5
V-tolerant
−All fast I/Os, control registers accessable with fAHB speed
Up to 17 Timers
−Up to8 x 16-bittimers + 2 x 32-bit timers; each with 4
IC/OC/PWMor pulse counter andquadrature
(incremental) encoder input.
−Up to2 x 16-bit motor control PWM advanced timers
with dead-time generator andemergency brake
−2 x Watchdogtimers
−SysTick timer: 24-bitdowncounter
−2 x 16-bit basic timers to drive the DAC
Up to 21 Communication Interfaces
−Up to3 x I2Cinterfaces (SMBus/PMBus)
−Up to8 x USARTs (ISO7816 interface,LIN, IrDA
capability, and modem control)
−Up to4 x SPIs (50 Mbit/s), all with I2Sinterface
multiplexed,.I2S2/ I2S3 support full-duplex
−Up to2 x CAN interfaces (2.0B Active)
−USB2.0 full-speed interface supporting Crystal-less
−Up to2 x SDIO interfaces
−10/100M Ethernet MAC with dedicated DMA and
SRAM(4 KBytes): IEEE1588 hardware support, MII/RMII
available
CRC Calculation Unit
96-bit unique ID (UID)
Packages
−LQFP100 14x14mm
−LQFP64 10x10 mm
−LQFP48 7x7 mm
−QFN48 6 x 6mm
List of Models
Internal Flash
Model
1024 KBytes
AT32F403ACGU7, AT32F403ACGT7,
AT32F403ARGT7, AT32F403AVGT7,
AT32F407RGT7, AT32F407VGT7, AT32F407AVGT7
512 KBytes
AT32F403ACEU7, AT32F403ACET7,
AT32F403ARET7, AT32F403AVET7,
AT32F407RET7, AT32F407VET7
256 KBytes
AT32F403ACCU7, AT32F403ACCT7,
AT32F403ARCT7, AT32F403AVCT7,
AT32F407RCT7, AT32F407VCT7, AT32F407AVCT7

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Contents
1System architecture...................................................................... 35
1.1 System overview..........................................................................37
1.1.1 ARM CortexTM-M4F processor...................................................... 37
1.1.2 Bit band...................................................................................... 38
1.1.3 Interrupt and exception vectors .................................................... 40
1.1.4 System Tick (SysTick) ................................................................. 43
1.1.5 Reset ......................................................................................... 43
1.2 List of abbreviations for registers ..................................................45
1.3 Device characteristics information.................................................45
1.3.1 Flash memory size register .......................................................... 45
1.3.2 Device electronic signature.......................................................... 45
2Memory resources ........................................................................ 47
2.1 Internal memory address map.......................................................47
2.2 Flash memory..............................................................................47
2.3 SRAM memory.............................................................................49
2.4 Peripheral address map................................................................49
3Power control (PWC)..................................................................... 52
3.1 Introduction .................................................................................52
3.2 Main Features .............................................................................52
3.3 POR/LVR ....................................................................................52
3.4 Power voltage monitor (PVM)........................................................53
3.5Power domain..............................................................................53
3.6 Power saving modes ....................................................................54
3.7 PWC registers .............................................................................55
3.7.1 Power control register (PWC_CTRL) ............................................ 56
3.7.2 Power control/status register (PWC_CTRLSTS) ............................ 57
4Clock and reset manage (CRM) ..................................................... 58
4.1Clock ..........................................................................................58

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4.1.1 Clock sources ............................................................................. 58
4.1.2 System clock............................................................................... 59
4.1.3 Peripheral clock .......................................................................... 59
4.1.4 Clock fail detector ....................................................................... 60
4.1.5 Auto step-by-step system clock switch.......................................... 60
4.1.6 Internal clock output.................................................................... 60
4.1.7 Interrupts.................................................................................... 60
4.2 Reset..........................................................................................60
4.2.1 System reset............................................................................... 60
4.2.2 Battery powered domain reset...................................................... 61
4.3 CRM registers .............................................................................61
4.3.1 Clock control register (CRM_CTRL).............................................. 62
4.3.2 Clock configuration register (CRM_CFG) ...................................... 63
4.3.3 Clock interrupt register (CRM_CLKINT) ........................................ 65
4.3.4 APB2 peripheral reset register (CRM_APB2RST) .......................... 66
4.3.5 APB1 peripheral reset register (CRM_APB1RST) .......................... 68
4.3.6 APB peripheral clock enable register (CRM_AHBEN)..................... 69
4.3.7 APB2 peripheral clock enable register (CRM_AHB2EN) ................. 70
4.3.8 APB1 peripheral clock enable register (CRM_AHB1EN)................. 72
4.3.9 Battery powered domain control register (CRM_BPDC).................. 73
4.3.10 Control/status register (CRM_CTRLSTS) ...................................... 74
4.3.11 AHB peripheral reset register (CRM_AHBRST) ............................. 75
4.3.12 Additional register1 (CRM_MISC1) ............................................... 75
4.3.13 Additional register2 (CRM_MISC2) ............................................... 76
4.3.14 Additional register3 (CRM_MISC3) ............................................... 76
4.3.15 Interrupt map register (CRM_INTMAP) ......................................... 77
5Flash memory controller (FLASH) ................................................. 78
5.1 Flash memory introduction............................................................78
5.2 Flash memory operation ...............................................................82
5.2.1 Unlock/lock ................................................................................. 82
5.2.2 Erase operation........................................................................... 83
5.2.3 Programming operation................................................................ 85
5.2.4 Read operation ........................................................................... 86
5.3 External memory operation ...........................................................86

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5.4 User system data area operation...................................................86
5.4.1 Unlock/lock ................................................................................. 86
5.4.2 Erase operation........................................................................... 86
5.4.3 Programming operation................................................................ 87
5.4.4 Read operation ........................................................................... 88
5.5 Flash memory protection ..............................................................88
5.5.1 Access protection........................................................................ 89
5.5.2 Erase/program protection............................................................. 89
5.6 Special functions .........................................................................89
5.6.1 Security library settings ............................................................... 89
5.7 Flash memory registers ................................................................91
5.7.1 Flash performance select register (FLASH_PSR) .......................... 91
5.7.2 Flash unlock register (FLASH_UNLOCK) ...................................... 91
5.7.3 Flash user system data unlock register (FLASH_USD_UNLOCK) ... 92
5.7.4 Flash status register (FLASH_STS) .............................................. 92
5.7.5 Flash control register (FLASH_CTRL)........................................... 92
5.7.6 Flash address register (FLASH_ADDR) ........................................ 93
5.7.7 User system data register (FLASH_USD)...................................... 93
5.7.8 Erase/program protection status register (FLASH_EPPS) .............. 93
5.7.9 Flash unlock register2 (FLASH_UNLOCK2)................................... 93
5.7.10 Flash status register2 (FLASH_STS2) .......................................... 94
5.7.11 Flash control register2 (FLASH_CTRL2) ....................................... 94
5.7.12 Flash address register2 (FLASH_ADDR2)..................................... 95
5.7.13 Flash unlock register3 (FLASH_UNLOCK3)................................... 95
5.7.14 Flash select register (FLASH_SELECT)........................................ 95
5.7.15 Flash status register3 (FLASH_STS3) .......................................... 95
5.7.16 Flash control register3 (FLASH_CTRL3) ....................................... 95
5.7.17 Flash address register3 (FLASH_ADDR3)..................................... 96
5.7.18 Flash decrption address register (FLASH_DA) .............................. 96
5.7.19 Flash security library status register (SLIB_STS0)......................... 96
5.7.20 Flash security library status register1 (SLIB_STS1)....................... 96
5.7.21 Flash security library password clear register (SLIB_PWD_CLR).... 97
5.7.22 Security library additional status register (SLIB_MISC_STS).......... 97
5.7.23 Security library password setting register (SLIB_SET_PWD).......... 98
5.7.24 Security library address setting register (SLIB_SET_RANGE) ........ 98

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5.7.25 Security library unlock register (SLIB_UNLOCK) ........................... 98
5.7.26 Flash CRC check control register (FLASH_CRC_CTRL) ................ 99
5.7.27 Flash CRC check result register (FLASH_CRC_CHKR).................. 99
6General-purpose I/Os (GPIOs)..................................................... 100
6.1 Introduction ............................................................................... 100
6.2 Function overview...................................................................... 100
6.2.1 GPIO structure...........................................................................100
6.2.2 GPIO reset status.......................................................................101
6.2.3 General-purpose input configuration............................................101
6.2.4 Analog input/output configuration ................................................101
6.2.5 General-purpose output configuration..........................................101
6.2.6 I/O port protection ......................................................................101
6.3 GPIO registers........................................................................... 102
6.3.1 GPIO configuration register low (GPIOx_CFGLR) (x=A..E)............102
6.3.2 GPIO configuration register high (GPIOx_CFGHR) (A..E) .............103
6.3.3 GPIO input data register (GPIOx_IDT) (x=A..E)............................103
6.3.4 GPIO output data register (GPIOx_ODT) (x=A..E) ........................103
6.3.5 GPIO set/clear register (GPIOx_SCR) (x=A..E) ............................104
6.3.6 GPIO clear register (GPIOx_CLR) (x=A..E) ..................................104
6.3.7 GPIO write protection register (GPIOx_WPR) (x=A..E) .................104
6.3.8 GPIO huge current control register (GPIOx_HDRV) (x=A..E).........104
7Multiplex function I/Os (IOMUX).................................................. 105
7.1 Introduction ............................................................................... 105
7.2 Function overview...................................................................... 105
7.2.1 IOMUX structure ........................................................................105
7.2.2 MUX Input configuration .............................................................106
7.2.3 MUX output or bidirectional MUX configuration ............................106
7.2.4 Peripheral MUX function configuration.........................................106
7.2.5 IOMUX map priority ....................................................................106
7.2.5.1 Hardware preemption ............................................................ 107
7.2.5.2 Debug port priority ................................................................ 107
7.2.5.3 Other peripheral output priority .............................................. 107
7.2.6 External interrupt/wake-up lines ..................................................107

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7.3 IOMUX registers ........................................................................ 108
7.3.1 Event output control register (IOMUX_EVTOUT) ..........................108
7.3.2 IOMUX remap register (IOMUX_REMAP) .....................................109
7.3.3 IOMUX external interrupt configuration register1
(IOMUX_EXINTC1) ..............................................................................111
7.3.4 IOMUX external interrupt configuration register2
(IOMUX_EXINTC2) ..............................................................................112
7.3.5 IOMUX external interrupt configuration register3
(IOMUX_EXINTC3) ..............................................................................113
7.3.6 IOMUX external interrupt configuration register4
(IOMUX_EXINTC4) ..............................................................................113
7.3.7 IOMUX remap register2 (IOMUX_REMAP2) .................................114
7.3.8 IOMUX remap register3 (IOMUX_REMAP3) .................................115
7.3.9 IOMUX remap register4 (IOMUX_REMAP4) .................................115
7.3.10 IOMUX remap register5 (IOMUX_REMAP5) .................................116
7.3.11 IOMUX remap register6 (IOMUX_REMAP6) .................................117
7.3.12 IOMUX remap register7 (IOMUX_REMAP7) .................................118
7.3.13 IOMUX remap register8 (IOMUX_REMAP8) .................................119
8External interrupt/Event controller (EXINT) ................................ 121
8.1 EXINT introduction..................................................................... 121
8.2 Function overview and configuration procedure ............................ 121
8.3 EXINT registers ......................................................................... 122
8.3.1 Interrupt enable register (EXINT_INTEN).....................................122
8.3.2 Event enable register (EXINT_EVTEN) ........................................122
8.3.3 Polarity configuration register1 (EXINT_ POLCFG1).....................122
8.3.4 Polarity configuration register2 (EXINT_ POLCFG2).....................122
8.3.5 Software trigger register (EXINT_ SWTRG)..................................123
8.3.6 Interrupt status register (EXINT_ INTSTS) ...................................123
9DMA controller (DMA) ................................................................. 124
9.1 Introduction ............................................................................... 124
9.2 Main features ............................................................................ 124
9.3 Function overview...................................................................... 124
9.3.1 DMA configuration......................................................................124

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9.3.2 Handshake mechanism...............................................................125
9.3.3 Arbiter .......................................................................................125
9.3.4 Programmable data transfer width ...............................................126
9.3.5 Errors ........................................................................................127
9.3.6 Interrupts...................................................................................127
9.3.7 Fixed DMA request mapping .......................................................127
9.3.8 Flexible DMA request mapping....................................................128
9.4 DMA registers............................................................................ 129
9.4.1 DMA interrupt status register (DMA_STS) ....................................130
9.4.2 DMA interrupt flag clear register (DMA_CLR) ...............................132
9.4.3 DMA channelx configuration register (DMA_CxCTRL) (x = 1…7) ...133
9.4.4 DMA channelx number of data register (DMA_CxDTCNT)
(x = 1…7) ............................................................................................134
9.4.5 DMA channelx peripheral address register (DMA_CxPADDR)
(x = 1…7) ............................................................................................135
9.4.6 DMA channelx memory address register (DMA_CxMADDR)
(x = 1…7) ............................................................................................135
9.4.7 Channel source register (DMA_SRC_SEL0) .................................135
9.4.8 Channel source register1 (DMA_SRC_SEL1) ...............................135
10 CRC calculation unit (CRC)......................................................... 137
10.1 CRC introduction ....................................................................... 137
10.2 CRC registers............................................................................ 137
10.2.1 Data register (CRC_DT)..............................................................137
10.2.2 Common data register (CRC_CDT)..............................................137
10.2.3 Control register (CRC_CTRL)......................................................138
10.2.4 Initialization register (CRC_IDT) .................................................138
11 I2C interface ................................................................................ 139
11.1 I2C introduction.......................................................................... 139
11.2 I2C main features....................................................................... 139
11.3 I2C function overview ................................................................. 139
11.4 I2C interface .............................................................................. 140
11.4.1 I2C slave communication flow......................................................142
11.4.2 I2C master communication flow ...................................................144

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11.4.3 Utilize DMA for data transfer.......................................................151
11.4.4 SMBus.......................................................................................151
11.4.5 I2C interrupt requests .................................................................153
11.4.6 I2C debug mode .........................................................................153
11.5 I2C registers .............................................................................. 154
11.5.1 Control register1 (I2C_CTRL1)....................................................154
11.5.2 Control register2 (I2C_CTRL2)....................................................155
11.5.3 Own address register1 (I2C_OADDR1) ........................................156
11.5.4 Own address register2 (I2C_OADDR2) ........................................156
11.5.5 Data register (I2C_DT) ...............................................................156
11.5.6 Status register1 (I2C_STS1) .......................................................157
11.5.7 Status register2 (I2C_STS2) .......................................................159
11.5.8 Clock control register (I2C_ CLKCTRL) .......................................160
12 Universal synchronous/asynchronous receiver/transmitter
(USART) ................................................................................................ 161
12.1 USART introduction ................................................................... 161
12.2 Full-duplex/half-duplex selector .................................................. 163
12.3 Mode selector............................................................................ 163
12.3.1 Introduction................................................................................163
12.3.2 Configuration procedure .............................................................163
12.4 USART frame format and configuration........................................ 164
12.5 DMA transfer introduction........................................................... 164
12.5.1 Transmission using DMA ............................................................164
12.5.2 Reception using DMA .................................................................164
12.6 Baud rate generation.................................................................. 165
12.6.1 Introduction................................................................................165
12.6.2 Configuration .............................................................................165
12.7 Transmitter................................................................................ 166
12.7.1 Transmitter introduction..............................................................166
12.7.2 Transmitter configuration ............................................................166
12.8 Receiver ................................................................................... 166
12.8.1 Receiver introduction..................................................................166
12.8.2 Receiver configuration................................................................167
12.8.3 Start bit and noise detection .......................................................168

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12.9 Interrupt requests ...................................................................... 168
12.10I/O pin control............................................................................ 169
12.11USART registers........................................................................ 169
12.11.1 Status register (USART_STS) ..................................................169
12.11.2 Data register (USART_DT).......................................................171
12.11.3 Baud rate register (USART_BAUDR) ........................................171
12.11.4 Control register1 (USART_CTRL1) ...........................................171
12.11.5 Control register2 (USART_CTRL2) ...........................................172
12.11.6 Control register3 (USART_CTRL3) ...........................................173
12.11.7 Guard time and divider register (GDIV) .....................................174
13 Serial peripheral interface (SPI).................................................. 175
13.1 SPI introduction......................................................................... 175
13.2 Function overview...................................................................... 175
13.2.1 SPI description...........................................................................175
13.2.2 Full-duplex/half-duplex selector ..................................................176
13.2.3 Chip select controller..................................................................178
13.2.4 SPI_SCK controller ....................................................................178
13.2.5 CRC ..........................................................................................178
13.2.6 DMA transfer..............................................................................179
13.2.7 Transmitter ................................................................................180
13.2.8 Receiver ....................................................................................180
13.2.9 Interrupt ....................................................................................181
13.2.10 IO pin control ..........................................................................181
13.2.11 Precautions.............................................................................182
13.3 I2S functional description............................................................ 182
13.3.1 I2S introduction ..........................................................................182
13.3.2 I2S full-duplex ............................................................................183
13.3.3 Operation mode selector.............................................................183
13.3.4 Audio protocol selector ...............................................................184
13.3.5 I2S_CLK controller .....................................................................185
13.3.6 DMA transfer..............................................................................188
13.3.7 Transmitter/Receiver ..................................................................188
13.3.8 Interrupts...................................................................................189
13.3.9 IO pin control .............................................................................189

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13.4 SPI registers ............................................................................. 190
13.4.1 SPI control register1 (SPI_CTRL1) (Not used in I2S mode) ...........190
13.4.2 SPI control register2 (SPI_CTRL2)..............................................191
13.4.3 SPI status register (SPI_STS) .....................................................192
13.4.4 SPI data register (SPI_DT) .........................................................193
13.4.5 SPICRC register (SPI_CPOLY) (Not used in I2S mode).................193
13.4.6 SPIRxCRC register (SPI_RCRC) (Not used in I2S mode)..............193
13.4.7 SPITxCRC register (SPI_TCRC)..................................................193
13.4.8 SPI_I2S register (SPI_I2SCTRL) .................................................193
13.4.9 SPI_I2S prescaler register (SPI_I2SCLKP) ..................................194
14 Timer .......................................................................................... 195
14.1 Basic timer (TMR6 and TMR7) .................................................... 196
14.1.1 TMR6 and TMR7 introduction......................................................196
14.1.2 TMR6 and TMR7 main features ...................................................196
14.1.3 TMR6 and TMR7 function overview .............................................196
14.1.3.1 Count clock .......................................................................... 196
14.1.3.2 Counting mode ..................................................................... 196
14.1.3.3 Debug mode ......................................................................... 197
14.1.4 TMR6 and TMR7 registers ..........................................................197
14.1.4.1 TMR6 and TMR7 control register1 (TMRx_CTRL1)................... 198
14.1.4.2 TMR6 and TMR7 control register2 (TMRx_CTRL2)................... 198
14.1.4.3 TMR6 and TMR7 DMA/interrupt enable register (TMRx_IDEN) .. 198
14.1.4.4 TMR6 and TMR7 interrupt status register (TMRx_ISTS) ........... 199
14.1.4.5 TMR6 and TMR7 software event register (TMRx_SWEVT) ........ 199
14.1.4.6 TMR6 and TMR7 counter value (TMRx_CVAL) ........................ 199
14.1.4.7 TMR6 and TMR7 division (TMRx_DIV) .................................... 199
14.1.4.8 TMR6 and TMR7 period register (TMRx_PR) ........................... 199
14.2 General-purpose timer (TMR2 to TMR5) ...................................... 199
14.2.1 TMRx introduction ......................................................................199
14.2.2 TMRx main features ...................................................................200
14.2.3 TMRx functional overview ...........................................................200
14.2.3.1 Count clock .......................................................................... 200
14.2.3.2 Counting mode ..................................................................... 202
14.2.3.3 TMR input function................................................................ 204
14.2.3.4 TMR output function.............................................................. 205

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14.2.3.5 TMR synchronization............................................................. 208
14.2.3.6 Debug mode ......................................................................... 211
14.2.4 TMRx registers...........................................................................211
14.2.4.1 Control register1 (TMRx_CTRL1) ........................................... 212
14.2.4.2 Control register2 (TMRx_CTRL2) ........................................... 213
14.2.4.3 Slave timer control register (TMRx_STCTRL) .......................... 213
14.2.4.4 DMA/interrupt enable register (TMRx_IDEN) ........................... 214
14.2.4.5 Interrupt status register (TMRx_ISTS) .................................... 215
14.2.4.6 Software event register (TMRx_SWEVT) ................................. 216
14.2.4.7 Channel mode register1 (TMRx_CM1) .................................... 216
14.2.4.8 Channel mode register2 (TMRx_CM2) .................................... 219
14.2.4.9 Channel control register (TMRx_CCTRL) ................................ 220
14.2.4.10 Counter value (TMRx_CVAL) ............................................... 220
14.2.4.11 Division value (TMRx_DIV)................................................... 221
14.2.4.12 Period register (TMRx_PR) .................................................. 221
14.2.4.13 Channel 1 data register (TMRx_C1DT) .................................. 221
14.2.4.14 Channel 2 data register (TMRx_C2DT) .................................. 221
14.2.4.15 Channel 3 data register (TMRx_C3DT) .................................. 221
14.2.4.16 Channel 4 data register (TMRx_C4DT) .................................. 222
14.2.4.17 DMA control register (TMRx_DMACTRL) ............................... 222
14.2.4.18 DMA data register (TMRx_DMADT) ....................................... 222
14.3 General-purpose timer (TMR9 to TMR14) .................................... 222
14.3.1 TMRx introduction ......................................................................222
14.3.2 TMRx main features ...................................................................223
14.3.2.1 TMR9 and TMR12 main features ............................................ 223
14.3.2.2 TMR10, TMR11, TMR13 and TMR14 main features .................. 223
14.3.3 TMRx functional overview ...........................................................224
14.3.3.1 Count clock .......................................................................... 224
14.3.3.2 Counting mode ..................................................................... 225
14.3.3.3 TMR input function................................................................ 226
14.3.3.4 TMR output function.............................................................. 226
14.3.3.5 TMR synchronization............................................................. 228
14.3.3.6 Debug mode ......................................................................... 229
14.3.4 TMR9 and TMR12 registers ........................................................230
14.3.4.1 Control register1 (TMRx_CTRL1) ........................................... 230
14.3.4.2 Slave timer control register (TMRx_STCTRL) .......................... 231
14.3.4.3 DMA/interrupt enable register (TMRx_IDEN) ........................... 231
14.3.4.4 Interrupt status register (TMRx_ISTS) .................................... 231

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14.3.4.5 Software event register (TMRx_SWEVT) ................................. 232
14.3.4.6 Channel mode register1 (TMRx_CM1) .................................... 233
14.3.4.7 Channel control register (TMRx_CCTRL) ................................ 235
14.3.4.8 Counter value (TMRx_CVAL) ................................................. 235
14.3.4.9 Division value (TMRx_DIV) .................................................... 235
14.3.4.10 Period register (TMRx_PR) .................................................. 236
14.3.4.11 Channel 1 data register (TMRx_C1DT) .................................. 236
14.3.4.12 Channel 2 data register (TMRx_C2DT) .................................. 236
14.3.5 TMR10,TMR11, TMR13 and TMR14 registers...............................236
14.3.5.1 Control register1 (TMRx_CTRL1) ........................................... 237
14.3.5.2 DMA/interrupt enable register (TMRx_IDEN) ........................... 237
14.3.5.3 Interrupt status register (TMRx_ISTS) .................................... 237
14.3.5.4 Software event register (TMRx_SWEVT) ................................. 238
14.3.5.5 Channel mode register1 (TMRx_CM1) .................................... 238
14.3.5.6 Channel control register (TMRx_CCTRL) ................................ 240
14.3.5.7 Counter value (TMRx_CVAL) ................................................. 240
14.3.5.8 Division value (TMRx_DIV) .................................................... 240
14.3.5.9 Period register (TMRx_PR) .................................................... 240
14.3.5.10 Channel 1 data register (TMRx_C1DT) .................................. 241
14.4 Advanced-control timers (TMR1 and TMR8) ................................. 241
14.4.1 TMR1 and TMR8 introduction......................................................241
14.4.2 TMR1 and TMR8 main features ...................................................241
14.4.3 TMR1 and TMR8 functional overview...........................................242
14.4.3.1 Count clock .......................................................................... 242
14.4.3.2 Counting mode ..................................................................... 244
14.4.3.3 TMR input function................................................................ 246
14.4.3.4 TMR output function.............................................................. 247
14.4.3.5 TMR break function............................................................... 251
14.4.3.6 TMR synchronization............................................................. 252
14.4.3.7 Debug mode ......................................................................... 253
14.4.4 TMR1 and TMR8 registers ..........................................................253
14.4.4.1 TMR1 and TMR8 control register1 (TMRx_CTRL1)................... 254
14.4.4.2 TMR1 and TMR8 control register2 (TMRx_CTRL2)................... 255
14.4.4.3 TMR1 and TMR8 slave timer control register (TMRx_STCTRL) . 256
14.4.4.4 TMR1 and TMR8 DMA/interrupt enable register (TMRx_IDEN).. 257
14.4.4.5 TMR1 and TMR8 interrupt status register (TMRx_ISTS) ........... 258
14.4.4.6 Software event register (TMRx_SWEVT) ................................. 259
14.4.4.7 TMR1 and TMR8 channel mode register1 (TMRx_CM1)............ 260

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14.4.4.8 Channel mode register2 (TMRx_CM2) .................................... 262
14.4.4.9 Channel control register (TMRx_CCTRL) ................................ 263
14.4.4.10 TMR1 and TMR8 counter value (TMRx_CVAL) ....................... 265
14.4.4.11 TMR1 and TMR8 division value (TMRx_DIV).......................... 265
14.4.4.12 TMR1 and TMR8 period register (TMRx_PR) ......................... 265
14.4.4.13 TMR1 and TMR8 repetition period register (TMRx_RPR) ........ 265
14.4.4.14 TMR1 and TMR8 channel 1 data register (TMRx_C1DT) ......... 265
14.4.4.15 TMR1 and TMR8 channel 2 data register (TMRx_C2DT) ......... 265
14.4.4.16 TMR1 and TMR8 channel 3 data register (TMRx_C3DT) ......... 266
14.4.4.17 TMR1 and TMR8 channel 4 data register (TMRx_C4DT) ......... 266
14.4.4.18 TMR1 and TMR8 break register (TMRx_BRK) ........................ 266
14.4.4.19 TMR1 and TMR8 DMA control register (TMRx_ DMACTRL)..... 267
14.4.4.20 TMR1 and TMR8 DMA data register (TMRx_ DMADT) ............ 268
15 Window watchdog timer (WWDT) ................................................ 269
15.1 WWDT introduction .................................................................... 269
15.2 WWDT main features ................................................................. 269
15.3 WWDT functional overview ......................................................... 269
15.4 Debug mode.............................................................................. 270
15.5 WWDT registers ........................................................................ 270
15.5.1 Control register (WWDT_CTRL) ..................................................270
15.5.2 Configuration register (WWDT_CFG)...........................................270
15.5.3 Status register (WWDT_STS)......................................................271
16 Watchdog timer (WDT) ................................................................ 272
16.1 WDT introduction ....................................................................... 272
16.2 WDT main features .................................................................... 272
16.3 WDT functional overview ............................................................ 272
16.4 Debug mode.............................................................................. 273
16.5 WDT registers ........................................................................... 273
16.5.1 Command register (WDT_CMD) ..................................................274
16.5.2 Divider register (WDT_DIV).........................................................274
16.5.3 Reload register (WDT_RLD)........................................................274
16.5.4 Status register (WDT_STS).........................................................274
17 Real-time clock (RTC) ................................................................. 275

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17.1 RTC introduction........................................................................ 275
17.2 RTC main features..................................................................... 275
17.3 RTC structure............................................................................ 275
17.4 RTC functional overview............................................................. 276
17.4.1 Configuring RTC registers...........................................................276
17.4.2 Reading RTC registers ...............................................................277
17.4.3 RTC interrupts ...........................................................................277
17.5 RTC registers ............................................................................ 278
17.5.1 RTC control register high (RTC_CTRLH) .....................................278
17.5.2 RTC control register low (RTC_CTRLL) .......................................279
17.5.3 RTC divider register (RTC_ DIVH/RTC_DIVL) ..............................279
17.5.4 RTC divider counter register (RTC_ DIVCNTH/RTC_DIVCNTL).....280
17.5.5 RTC counter value register (RTC_CNTH/RTC_CNTL) ...................280
17.5.6 RTC alarm register (RTC_TAH/RTC_TAL) ...................................280
18 Battery powered registers (BPR) ................................................ 281
18.1 BPR introduction........................................................................ 281
18.2 BPR main features..................................................................... 281
18.3 BPR functional overview............................................................. 281
18.4 BPR registers ............................................................................ 281
18.4.1 Battery powered data register x (BPR_DTx) (x = 1 … 42) .............282
18.4.2 RTC calibration register (BPR_ RTCCAL) ....................................282
18.4.3 BPR control register (BPR_ CTRL) ..............................................283
18.4.4 BPR control/status register (BPR_ CTRLSTS)..............................284
19 Analog-to-digital converter (ADC)............................................... 285
19.1 ADC introduction ....................................................................... 285
19.2 ADC main features..................................................................... 285
19.3 ADC structure............................................................................ 285
19.4 ADC functional overview............................................................. 286
19.4.1 Channel management.................................................................286
19.4.1.1 Internal temperature sensor ................................................... 287
19.4.1.2 Internal reference voltage...................................................... 287
19.4.2 ADC operation process...............................................................287
19.4.2.1 Power-on and calibration ....................................................... 288

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19.4.2.2 Trigger................................................................................. 288
19.4.2.3 Sampling and conversion sequence........................................ 289
19.4.3 Conversion sequence management .............................................290
19.4.3.1 Sequence mode .................................................................... 290
19.4.3.2 Automatic preempted group conversion mode ......................... 290
19.4.3.3 Repetition mode.................................................................... 291
19.4.3.4 Partition mode ...................................................................... 291
19.4.4 Data management ......................................................................292
19.4.4.1 Data alignment ..................................................................... 292
19.4.4.2 Data read ............................................................................. 292
19.4.5 Voltage monitor..........................................................................292
19.4.6 Status flag and interrupts............................................................292
19.5 Master/Slave mode .................................................................... 293
19.5.1 Data management ......................................................................293
19.5.2 Regular simultaneous mode ........................................................293
19.5.3 Alternate preempted trigger mode ...............................................294
19.5.4 Regular switch mode ..................................................................295
19.6 ADC registers............................................................................ 296
19.6.1 ADC status register (ADC_STS)..................................................297
19.6.2 ADC control register1 (ADC_CTRL1) ...........................................297
19.6.3 ADC control register2 (ADC_CTRL2) ...........................................299
19.6.4 ADC sampling time register 1 (ADC_SPT1)..................................302
19.6.5 ADC sampling time register 2 (ADC_SPT2)..................................304
19.6.6 ADC preempted channel data offset register x (ADC_ PCDTOx)
(x=1..4) ..............................................................................................306
19.6.7 ADC voltage monitor high threshold register (ADC_ VWHB)..........306
19.6.8 ADC voltage monitor low threshold register (ADC_ VWLB)............306
19.6.9 ADC ordinary sequence register 1 (ADC_ OSQ1) .........................306
19.6.10 ADC ordinary sequence register 2 (ADC_ OSQ2) ......................306
19.6.11 ADC ordinary sequence register 3 (ADC_ OSQ3) ......................307
19.6.12 ADC preempted sequence register (ADC_ PSQ)........................307
19.6.13 ADC preempted data register x (ADC_ PDTx) (x=1..4) ...............307
19.6.14 ADC ordinary data register (ADC_ ODT) ...................................307
20 Digital-to-analog converter (DAC)............................................... 308
20.1 DAC introduction ....................................................................... 308

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20.2 DAC main features..................................................................... 308
20.3 Design tips................................................................................ 308
20.4 Function overview...................................................................... 309
20.4.1 Trigger events............................................................................309
20.4.2 Noise/Triangular-wave generation ...............................................309
20.4.3 DAC data alignment ...................................................................311
20.5 DAC registers............................................................................ 311
20.5.1 DAC control register (DAC_CTRL)...............................................311
20.5.2 DAC software trigger register (DAC_SWTRG) ..............................314
20.5.3 DAC1 12-bit right-aligned data holding register
(DAC_ D1DTH12R) ..............................................................................314
20.5.4 DAC1 12-bit left-aligned data holding register
(DAC_ D1DTH12L)...............................................................................314
20.5.5 DAC1 8-bit right-aligned data holding register (DAC_ D1DTH8R) ..314
20.5.6 DAC2 12-bit right-aligned data holding register
(DAC_ D2DTH12R) ..............................................................................314
20.5.7 DAC2 12-bit left-aligned data holding register
(DAC_ D2DTH12L)...............................................................................315
20.5.8 DAC2 8-bit right-aligned data holding register (DAC_ D2DTH8R) ..315
20.5.9 Dual DAC 12-bit right-aligned data holding register
(DAC_ DDTH12R) ................................................................................315
20.5.10 Dual DAC 12-bit left-aligned data holding register
(DAC_ DDTH12L).................................................................................315
20.5.11 Dual DAC 8-bit right-aligned data holding register
(DAC_ DDTH8R)..................................................................................315
20.5.12 DAC1 data output register (DAC_ D1ODT)................................315
20.5.13 DAC2 data output register (DAC_ D2ODT) ................................315
21 CAN ............................................................................................ 316
21.1 CAN introduction ....................................................................... 316
21.2 CAN main features..................................................................... 316
21.3 Baud rate .................................................................................. 316
21.4 Interrupt management ................................................................ 319
21.5 Interrupt management ................................................................ 320
21.6 Function overview...................................................................... 320

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21.6.1 General description ....................................................................320
21.6.2 Operating modes........................................................................321
21.6.3 Test modes ................................................................................321
21.6.4 Message filtering........................................................................322
21.6.5 Message transmission ................................................................324
21.6.6 Message reception .....................................................................326
21.6.7 Error management......................................................................326
21.7 CAN registers............................................................................ 327
21.7.1 CAN control and status registers.................................................328
21.7.1.1 CAN master control register (CAN_MCTRL) ............................ 328
21.7.1.2 CAN master status register (CAN_MSTS)................................ 329
21.7.1.3 CAN transmit status register (CAN_TSTS) .............................. 331
21.7.1.4 CAN receive FIFO 0 register (CAN_RF0) ................................ 333
21.7.1.5 CAN receive FIFO 1 register (CAN_RF1) ................................ 334
21.7.1.6 CAN interrupt enable register (CAN_INTEN) ........................... 335
21.7.1.7 CAN error status register (CAN_ESTS) ................................... 336
21.7.1.8 CAN bit timing register (CAN_BTMG) ..................................... 337
21.7.2 CAN mailbox registers ................................................................338
21.7.2.1 Transmit mailbox identifier register (CAN_TMIx) (x=0..2) ......... 338
21.7.2.2 Transmit mailbox data length and time stamp register
(CAN_TMCx) (x=0..2)......................................................................... 338
21.7.2.3 Transmit mailbox data low register (CAN_TMDTLx) (x=0..2) ..... 339
21.7.2.4 Transmit mailbox data high register (CAN_TMDTHx) (x=0..2) ... 339
21.7.2.5 Receive FIFO mailbox identifier register (CAN_RFIx) (x=0..1) .. 339
21.7.2.6 Receive FIFO mailbox data length and time stamp register
(CAN_RFCx) (x=0..1) ......................................................................... 340
21.7.2.7 Receive FIFO mailbox data low register (CAN_RFDTLx)
(x=0..1) ........................................................................................... 340
21.7.2.8 Receive FIFO mailbox data high register (CAN_RFDTHx)
(x=0..1) ........................................................................................... 340
21.7.3 CAN filter registers.....................................................................340
21.7.3.1 CAN filter control register (CAN_FCTRL) ................................ 340
21.7.3.2 CAN filter mode configuration register (CAN_FMCFG) ............. 341
21.7.3.3 CAN filter bit width configuration register (CAN_ FBWCFG)...... 341
21.7.3.4 CAN filter FIFO association register (CAN_ FRF) .................... 341
21.7.3.5 CAN filter activation control register (CAN_ FACFG)................ 341
21.7.3.6 CAN filter bank i filter bit register (CAN_ FiFBx)
(i=0..13; x=1..2)................................................................................. 341

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22 External memory controller ........................................................ 342
22.1 XMC introduction ....................................................................... 342
22.2 XMC main features .................................................................... 342
22.3 XMC architecture ....................................................................... 343
22.3.1 Block diagram ............................................................................343
22.3.2 Address mapping .......................................................................344
22.4 NOR/PSRAM ............................................................................. 345
22.4.1 Operation mode .........................................................................345
22.4.2 Access mode .............................................................................346
22.4.2.1 Read/write operation with the same timings ............................ 346
22.4.2.2 Read/write operation with different timings.............................. 351
22.4.2.3 Multiplexed mode.................................................................. 359
22.4.2.4 Synchronous mode................................................................ 361
22.5 NAND ....................................................................................... 363
22.5.1 Operation mode .........................................................................363
22.5.2 Access timings...........................................................................364
22.5.3 ECC computation .......................................................................366
22.6 XMC registers............................................................................ 366
22.6.1 NOR Flash and PSRAM control registers .....................................367
22.6.1.1 SRAM/NOR Flash chip select control register 1
(XMC_BK1CTRL1) ............................................................................. 367
22.6.1.2 SRAM/NOR Flash chip select control register 4
(XMC_BK1CTRL4) ............................................................................. 368
22.6.1.3 SRAM/NOR Flash chip select timing register 1, 4
(XMC_BK1CTRL1, 4) ......................................................................... 370
22.6.1.4 SRAM/NOR Flash write timing register 1, 4
(XMC_BK1 TMGWR1, 4)..................................................................... 371
22.6.1.5 SRAM/NOR Flash extra timing register 1, 4 (XMC_EXT1, 4) ..... 371
22.6.2 NAND Flash control registers......................................................372
22.6.2.1 NAND Flash control register 2 (XMC_BK2CTRL) ..................... 372
22.6.2.2 Interrupt enable and FIFO status register 2 (XMC_BK2IS) ........ 373
22.6.2.3 Regular memory timing register 2 (XMC_ BK2TMGRG) ............ 373
22.6.2.4 Special memory timing register 2 (XMC_ BK2TMGSP) ............. 374
22.6.2.5 ECC value register 2 (XMC_ BK2ECC) ................................... 374
23 SDIO interface............................................................................. 375

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23.1 SDIO introduction ...................................................................... 375
23.2 SDIO main features.................................................................... 375
23.3 SDIO main features.................................................................... 377
23.3.1 Card functional description .........................................................377
23.3.1.1 Card identification mode........................................................ 377
23.3.1.2 Data transfer mode ............................................................... 378
23.3.1.3 Erase................................................................................... 379
23.3.1.4 Protection management......................................................... 379
23.3.2 Commands and responses ..........................................................382
23.3.2.1 Commands ........................................................................... 382
23.3.2.2 Response formats ................................................................. 385
23.3.3 SDIO functional description ........................................................387
23.3.3.1 SDIO adapter ....................................................................... 388
23.3.3.2 Data BUF ............................................................................. 392
23.3.3.3 SDIO AHB interface .............................................................. 392
23.3.3.4 Hardware flow control............................................................ 393
23.3.4 SDIO I/O card-specific operations ...............................................393
23.4 SDIO registers........................................................................... 394
23.4.1 SDIO power control register (SDIO_ PWRCTRL)..........................394
23.4.2 SDIO clock control register (SDIO_ CLKCTRL) ............................395
23.4.3 SDIO argument register (SDIO_ARG) ..........................................396
23.4.4 SDIO command register (SDIO_CMD) .........................................396
23.4.5 SDIO command response register (SDIO_RSPCMD) ....................397
23.4.6 SDIO response 1..4 register (SDIO_RSPx) ..................................397
23.4.7 SDIO data timer register (SDIO_DTTMR).....................................397
23.4.8 SDIO data length register (SDIO_DTLEN)....................................397
23.4.9 SDIO data control register (SDIO_DTCTRL).................................398
23.4.10 SDIO data counter register (SDIO_DTCNTR) ............................399
23.4.11 SDIO status register (SDIO_STS).............................................399
23.4.12 SDIO clear interrupt register (SDIO_INTCLR)............................400
23.4.13 SDIO interrupt mask register (SDIO_INTEN) .............................401
23.4.14 SDIOBUF counter register (SDIO_BUFCNTR) ...........................403
23.4.15 SDIO data BUF register (SDIO_BUF)........................................403
24 Universal serial bus full-seed device interface (USBFS) ............. 404
24.1 USBFS introduction.................................................................... 404

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24.2 USBFS clock and pin configuration.............................................. 404
24.2.1 USB clock configuration..............................................................404
24.2.2 USB pin configuration.................................................................404
24.3 USBFS functional description...................................................... 404
24.3.1 USB initialization........................................................................404
24.3.2 Endpoint configuration................................................................405
24.3.3 USB buffer.................................................................................405
24.3.4 Double-buffered endpoints..........................................................406
24.3.5 SOF output ................................................................................407
24.3.6 Suspend/Resume .......................................................................407
24.4 USBFS interrupts....................................................................... 407
24.5 USBFS registers ........................................................................ 407
24.5.1 USBFS endpoint n register (USBFS_EPTn), n=[0..7] ....................408
24.5.2 USBFS control register (USBFS_CTRL).......................................409
24.5.3 USBFS interrupt status register (USBFS_INTSTS) .......................410
24.5.4 USBFS SOF frame number register (USBFS_SOFRNUM) .............411
24.5.5 USBFS device address register (USBFS_DEVADDR) ...................411
24.5.6 USBFS buffer table address register (USBFS_BUFTBL) ...............411
24.5.7 USBFS CFG control register (USBFS_CFG).................................411
24.5.8 USBFS transmission buffer first address register
(USBFS_TnADDR) ...............................................................................412
24.5.9 USBFS transmission data length register (USBFS_TnLEN) ...........412
24.5.10 USBFS reception buffer first address register
(USBFS_RnADDR)...............................................................................412
24.5.11 USBFS reception data length register (USBFS_RnLEN).............412
25 HICK auto clock calibration (ACC) .............................................. 413
25.1 ACC introduction ....................................................................... 413
25.2 Main features ............................................................................ 413
25.3 Interrupt requests ...................................................................... 413
25.4 Functional description ................................................................ 414
25.5 Principle.................................................................................... 415
25.6 Register description ................................................................... 416
25.6.1 Status register (ACC_STS) .........................................................416
25.6.2 Control register 1 (ACC_CTRL1) .................................................417