ARTERY AT32F421 Series User manual

Getting Started with AT32F421
2022.10.21 1 Ver 2.0.4
AN0024
Application Note
Getting Started with AT32F421
Introduction
This application note is written to help users with rapid project development using AT32F421xx.
Note: The corresponding code in this application note is developed on the basis of V2.x.x BSP provided by
Artery. For other versions of BSP, please pay attention to the differences in usage.
Applicable products:
Part number
AT32F421xx

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Contents
Preliminary environment requirements............................................................... 5
Build AT32 development environment ......................................................................5
Debug tools and evaluation board...............................................................................5
Programming tools and software.................................................................................5
AT32 development environment ..................................................................................6
How to replace SXX...................................................................................................11
AT32F421 chip enhanced functions .......................................................................12
Prefetch buffer............................................................................................................12
PLL clock settings ......................................................................................................13
Encryption mode ........................................................................................................15
Set boot memory as main Flash memory extension area.........................................18
Recognize AT32 MCU in program .............................................................................21
FAQs in downloading/compiling........................................................................ 23
Hard Fault Handler................................................................................................. 23
J-Link cannot find IC............................................................................................... 23
Errors in program downloading............................................................................... 23
Flash Download failed–“Cortex-M4”..........................................................................23
No Debug Unit Device found......................................................................................24
RDDI-DAP Error.........................................................................................................24
ISP serial port gets stuck in downloading..................................................................24
Resume download......................................................................................................24
Security Library (sLib)......................................................................................... 25
Introduction.............................................................................................................25
Principles of application..........................................................................................25
Security library application...................................................................................... 25
Revision history................................................................................................... 26

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List of Tables
Table 1. Document revision history....................................................................................................26

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List of Figures
Figure 1. AT-START-F421 evaluation board with AT-Link-EZ............................................................5
Figure 2.AT-START-F421 evaluation board package.........................................................................5
Figure 3. ICP/ISP/AT-Link-Family........................................................................................................6
Figure 4. BSP package........................................................................................................................6
Figure 5. Keil_v5 templates.................................................................................................................7
Figure 6. Pack download.....................................................................................................................8
Figure 7. Set upArteryTek.AT32F421 _DFP.......................................................................................8
Figure 8. Set up Keil4_AT32MCU_AddOn..........................................................................................8
Figure 9. Pack Installer icon in Keil .....................................................................................................9
Figure 10. Set up IAR_AT32MCU_AddOn..........................................................................................9
Figure 11. Keil Debug option .............................................................................................................10
Figure 12. Keil Debug Settings..........................................................................................................10
Figure 13. Keil Utilities.......................................................................................................................10
Figure 14. IAR Debug option............................................................................................................. 11
Figure 15. IAR CMSIS-DAP option....................................................................................................11
Figure 16. Wait states of Flash performance select register (FLASH_PSR)....................................12
Figure 17. System clock configuration function “system_clock_config”............................................12
Figure 18.AT32F421 118 MHz PLL clock configuration ...................................................................13
Figure 19. SXX PLL auto step-by-step switch configurations...........................................................14
Figure 20. AT32 PLL auto step-by-step switch configurations..........................................................14
Figure 21. Enable/disable access protection in ICP Programmer ....................................................15
Figure 22. Enable access protection in ISP Programmer.................................................................16
Figure 23. Disable access protection in ISP Programmer ................................................................16
Figure 24. Enable erase and program protection in ICP Programmer..............................................17
Figure 25. Disable erase and program protection in ICP Programmer.............................................18
Figure 26. Set AP mode in ICP Programmer.....................................................................................19
Figure 27.AP mode enabling in ICP Programmer............................................................................19
Figure 28. Offline config settings in ICP Programmer.......................................................................20
Figure 29.AT-Link project file settings...............................................................................................21
Figure 30.AT-Link offline download status........................................................................................21
Figure 31. Read Cortex ID.................................................................................................................22
Figure 32. Read PID and UID............................................................................................................22
Figure 33. Flash Download failed–“Cortex- M4” pops up in downloading ........................................23

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Preliminary environment requirements
Download development environment
ARTERY's official website
Build AT32 development environment
Debug tools and evaluation board
The AT32F421 supports AT-Link/J-Link, and the evaluation board has an AT-Link-EZ debug tool
(as shown in the red box in Figure 1 below), which can be disassembled and used with other circuit
boards, supporting IDE online debugging, online programming and USB-to-serial port.
Figure 1. AT-START-F421 evaluation board with AT-Link-EZ
Note: For details about resources for AT-START evaluation board, please refer to
UM_AT_START_F421_Vx.x. Path: ARTERY’s official website→PRODUCTS→Value line→AT32F4xx;
download and unzip Evaluation Board package, and get the “\AT_START_F421_Vx.x\03_Documents”.
Figure 2. AT-START-F421 evaluation board package
Programming tools and software
AT programming tools and software: AT-Link / AT-Link+ /AT-Link-Pro / AT-Link-ISO /AT-Link-
7-12 V external power socket
Boot mode select (BOOT jumper cap)
20-pinARM
Standard
JTAG port
User LED*3
AT-Link port
I/O extend port
USART1 port
RESET button
USER button
Arduino Uno extend port

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EZ, ICP/ISP.
3rd party programming tools: J-Link, Armfly, Alientek, XWOPEN, ICWORKSHOP, ZLG,
MaxWiz, Amomcu, Acroview, Forcreat, Galecomm, Prosystems, Rx-prog, Sinaen, XELTEK,
Zhifeng, etc.
Note: For more information, please visit ARTERY’s official website→SUPPORT→Hardware Development
Tool and 3RD Party Writer.
For ICP usage instructions, please refer to UM_ICP_Programmer. Path: ARTERY’s official
website→PRODUCTS→Value line→AT32F4xx; download and unzip ICP tool, and get the
“Artery_ICP_Programmer_Vx.x.xx\Document\UM_ICP_Programmer”.
For ISP usage instructions, please refer to UM_ISP_Programmer. Path: ARTERY’s official
website→PRODUCTS→Value line→AT32F4xx; download and unzip ISP tool, and get the
“Artery_ISP_Programmer_Vx.x.xx\Document\UM_ISP_Programmer”.
For AT-Link usage instructions, please refer to UM0004_AT-Link_User_Manual.
Path: ARTERY’s official website→PRODUCTS→Value line→AT32F4xx; download and unzip
AT-Link-Family, and then get the “AT_Link_CH_ Vx.x.x\05_Documents\UM0004_AT-
Link_User_Manual_EN_Vx.x.x”.
Figure 3. ICP/ISP/AT-Link-Family
AT32 development environment
Template projects
The commonly used IDE template projects are available from BSP provided by ArteryTek. BSP
path: ARTERY’s official website→PRODUCTS→Value line→AT32F4xx.
Figure 4. BSP package

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Template projects based on Keil_v5/Keil_v4/IAR_6.10/IAR_7.4/IAR_8.2/eclipse_gcc/at32_ide are
contained in BSP. Path:AT32F421_Firmware_Library_V2.x.x\project\at_start_f4xx\templates.
Open the project folder and click on the project file to open the corresponding IDE project. The
example of Keil_v5 template project is shown below.
Figure 5. Keil_v5 templates
Contents in the project:
①at32f421_clock.c: clock configuration file, contains default clock frequencyand clock path;
②at32f421_int.c: interrupt file, part of core interrupt function code flow is written by default;
③main.c: main code file of the template project;
④at32f421_board.c: board-level configuration file, contains settings of AT-START on-board
buttons and LEDs;
⑤at32f421_xx.c under firmware file: driver file of on-chip peripherals;
⑥system_at32f421.c: system initialization file;
⑦startup_at32f421.s: startup file;
⑧readme.txt: project documentation, contains application functions, setting methods and
associated application notes (ApNote) of the template project.
Except for templates, BSP also includes code examples (Keil_v5 project files) in terms of
peripherals for reference.
Path: AT32F421_Firmware_Library_V2.x.x\project\at_start_f4xx\examples.
Note: For more details about BSP, please refer to “Section 4 BSP application” of AT32F421 Firmware
BSP&Pack User Guide. Path: ARTERY’s official website→PRODUCTS→Value line→AT32F4xx; download
and unzip, and get the “\AT32F421_Firmware_Library_Vx.x.x\document”.
Pack installation
Install Pack and add the AT32 MCU part number to Keil/IAR. You can download Pack from
ARTERY’s official website→PRODUCTS→Value line→AT32F4xx.

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Figure 6. Pack download
For Keil compiling system, keil 4.74 /5.23 or above is recommended. If Keil_v5 is used, please
unzip Keil5_AT32MCU_AddOn and install the corresponding ArteryTek.AT32F421_DFP. If Keil_v4
is used, please install Keil4_AT32MCU_AddOn. By default, the Keil installation path can be
recognized automatically during installation. If the path is not recognized or incorrect, you need to
manually select the Keil installation path.
Figure 7. Set up ArteryTek.AT32F421 _DFP
Figure 8. Set up Keil4_AT32MCU_AddOn
You can also open keil and click on “Pack Installer” icon; then click on the top left “file” and select
“import” to import the corresponding pack downloaded from ARTERY's official website.

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Figure 9. Pack Installer icon in Keil
For IAR compiling system, IAR7.0 or IAR6.1 above is recommended. It is necessary to install
IAR_AT32MCU_AddOn. By default, the IAR installation path can be recognized automatically during
installation. If the path is not recognized or incorrect, you need to manually select the IAR installation
path.
Figure 10. Set up IAR_AT32MCU_AddOn
Note: For more details about Pack setup, please refer to “Section 2 Pack setup” of AT32F421 Firmware
BSP&Pack User Guide. Path: ARTERY’s official website→PRODUCTS→Value line→AT32F4xx; download
and unzip BSP, and get the “\AT32F421_Firmware_Library_Vx.x.x\document”.
Use AT-Link for debug and download
If you want to use AT-Link in IAR, select CMSIS-DAP in Debugger option.

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Figure 11. Keil Debug option
Go to Debug and click on Settings to enter the Cortex-M Target Driver Setup interface.
1. Select AT-Link(WinUSB)-CMSIS-DAP/AT-Link-CMSIS-DAP.
Note: For details about WinUSB, please refer to FAQ0136_How to use AT-LINK WinUSB to improve download
speed (ARTERY’s official website→SUPPORT→FAQ→FAQ0136).
2. Find Port, select SW and then tick SWJ;
3. Confirm that the ARM SW-DP debug module is recognized.
Figure 12. Keil Debug Settings
Click on Utilities and untick option box 1; then select CMSIS-DAP Debugger in option box 2, and
finally tick option box 1 (it should be unticked first and then ticked).
Figure 13. Keil Utilities

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If you want to use AT-Link in IAR, please click on Project and select Options; then select CMSIS-
DAP in Debugger option, and select SWD in CMSIS DAP option.
Figure 14. IAR Debug option
Figure 15. IAR CMSIS-DAP option
Note: For details about Flash algorithm file, MCU switch and solutions for “J-Link cannot find MCU”, please
refer to AT32F421 Firmware BSP&Pack User Guide. Path: ARTERY’s official website→PRODUCTS→Value
line→AT32F4xx; download and unzip BSP, and get the “\AT32F421_Firmware_Library_Vx.x.x\document”.
How to replace SXX
Please refer to MG0016_ Migrating from SXX32F030 to AT32F421. Path: ARTERY’s official

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website→PRODUCTS→Value line→AT32F4xx.
If the program still cannot run properly after completing the above steps, please refer to other
sections of this application note or contact the agent and ARTERY technicians for help.
Note: Compared with SXX32F0xx, AT32F421 is more flexible to achieve better performance. Please refer to
AN0004_Performance_Optimization (ARTERY’s official website→ SUPPORT→AP Note→AN0004) to learn
how to promote performance of AT32F421.
AT32F421 chip enhanced functions
Prefetch buffer
When the prefetch buffer is set, the CPU can execute operations faster. For example, while the
CPU is reading one byte, the next byte is waiting in the prefetch buffer. The Prefetch controller
decides whether to access the Flash according to the available space in the prefetch buffer. When
there is at least one available block in the prefetch buffer, the prefetch controller starts a read
operation.
The user needs to set wait states according to different system clock frequencies by setting bit 2:0
of the FLASH_PSR register (corresponds to the FLASH_ACR register of SXX32).
Figure 16. Wait states of Flash performance select register (FLASH_PSR)
AT library has corresponding settings in the system clock configuration function
“system_clock_config()”. For other BSP versions, please find out the correct position and complete
the corresponding settings.
Figure 17. System clock configuration function “system_clock_config”

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PLL clock settings
PLL setting methods
The embedded PLL clock of AT32F421 has a maximum output frequency of 120 MHz, and it can be
configured by using the CRM_CFG register (corresponds to RCC_CFGR register of SXX32) or the
additional CRM_PLL register. Users can use the CRM_PLL register to configure more PLL clock
frequencies, and the formula is shown below:
PLL output clock = PLL ref. input clock × PLL multiplication factor (PLL_NS)
PLL pre − division factor (PLL_MS) × PLL post − division factor (PLL_FR)
When the SXX32F0xx BSP is used, the PLL setting example (HSE=8 MHz, PLL=48 MHz)
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
If the user wants to use SXX32F0xx program to output a clock greater than 48 MHz on AT32F421, it
is necessary to configure the CRM_CFG register (corresponds to the RCC_CFGR register of SXX32).
When PLL=144 MHz, the corresponding setting is as follows:
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL15 );
When the AT BSP is used, the PLL setting example (HEXT=8 MHz, PLL=48 MHz):
crm_pll_config(CRM_PLL_SOURCE_HEXT, CRM_PLL_MULT_6);
When the AT BSP is used, the PLL setting example (HEXT=8 MHz, PLL=120 MHz):
crm_pll_config(CRM_PLL_SOURCE_HEXT, CRM_PLL_MULT_15);
The user also can use the additional CRM_PLL register of AT32 MCU to configure more clock
frequencies. For example, if the AT32F421 BSP is used, the PLL setting example (HEXT=8 MHz,
PLL=118 MHz):
Figure 18. AT32F421 118 MHz PLL clock configuration
#define CRM_PLL_NS ((uint16_t)0x3C) /* PLL_NS=59 */
#define CRM_PLL_MS ((uint16_t)0x01) /* PLL_MS=1 */
/* config pll clock resource PLL_FR =4*/
crm_pll_config2(CRM_PLL_SOURCE_HEXT, CRM_PLL_NS, CRM_PLL_MS, CRM_PLL_FR_4);
Where, the parameter CRM_PLL_SOURCE_HEXT represents that the HEXT is used as external
clock source; PLL_NS=59, PLL_MS=1, CRM_PLL_FR_4 (0x02, divided by four) represents the
PLL_FR value.
Please refer to AN0116_AT32F421_CRM_Start_Guide (ARTERY's official website→SUPPORT
→AP Note→AN0116) for more details about AT32F421 clock source settings and modification and
learn how to use New Clock Configuration (ARTERY's official website→PRODUCTS→Value
line→AT32F4xx) to generate the desired clock code and apply it to the project.

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Auto step-by-step switch
When the internal PLL of AT32F421 is set to 108 MHz and above, it is necessary to perform auto
step-by-step switch.
When the SXX32F0xx BSP is used, the user needs to open system_sxx32f0xx.c and find out the
current system clock configuration function (go through Section 1.2.2.1 PLL settings), and add the
following codes in Italic black to the static void SetSysClockToxxM(void) function:
Figure 19. SXX PLL auto step-by-step switch configurations
/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
*((unsigned int *)0x40021054) |= (0x30); // Enable auto step-by-step clock switch function
/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
{
}
*((unsigned int *)0x40021054) &=~ (0x30); // Disable auto step-by-step clock switch function
When the AT32F421 BSP is used, the example of PLL auto step-by-step switch is shown below:
Figure 20. AT32 PLL auto step-by-step switch configurations
/* enable auto step mode */
crm_auto_step_mode_enable(TRUE);
/* select pll as system clock source */
crm_sysclk_switch(CRM_SCLK_PLL);
/* wait till pll is used as system clock source */
while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL)
{
}
/* disable auto step mode */
crm_auto_step_mode_enable(FALSE);
/* update system_core_clock global variable */
system_core_clock_update();
Note: If the auto step-by-step system clock switch is enabled, it must be disabled after clock switch.

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Encryption mode
Note: The BOOT1 of AT32F421 is located in the user system data area (0x1FFF F800). When using ISP
programmer, please confirm that nBOOT1=1 (default value) to allow the program to boot from boot memory
(rather than SRAM).
Access protection
The access protection is commonly known as “encryption”, which is applied to the entire Flash
storage area. Once the Flash access protection is enabled, the embedded Flash storage area can
only be read through normal execution of the program, not through JTAG or SWD. When ICP/ISP
tool is used to disable the access protection, the chip will perform erase operation on the Flash.
Note: Once enabled, the high-level access protection cannot be disabled, and the user is not allowed to
re-erase or program the system data area in any way.
The ICP/ISP tool can be used to enable and disable IC access protection, as shown below:
Artery ICP Programmer (BOOT0=0)
Enable access protection: Open Artery ICP Programmer—Access protection—Enable
access/high-level access protection.
Disable access protection: Open Artery ICP Programmer—Access protection—Disable.
Figure 21. Enable/disable access protection in ICP Programmer
Artery ISP Programmer (BOOT0=1)
Enable access protection: Click on “Next” until enter the final interface, then select
“Protection/Enable/High-level access protection” —Next—Yes, encrypted.
Disable access protection: Protection/Disable/Access protection—Next—Yes, Flash decrypted.
Artery ISP Multi-Port Programmer (BOOT0=1)
Enable access protection: Protection/Enable/High-level access protection—Start, encrypted;
Disable access protection: Protection/Disable/Access protection—Start, Flash decrypted.

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Figure 22. Enable access protection in ISP Programmer
Figure 23.Disable access protection in ISP Programmer
Note: Once enabled, the access protection cannot be disabled through erase operation.

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Erase and program protection
The program protection is applied to the entire Flash storage area or certain pages in the Flash
storage area. Once the Flash program protection is enabled, the internal Flash storage area cannot
be programmed in any way.
The user can use ICP/ISP tool to enable/disable erase and program protection, as shown below:
Artery ICP Programmer (BOOT0=0)
Enable erase and program protection: Open Artery ICP Programmer—User system data—Tick
the sectors that require erase and program protection—Apply to device.
Disable erase and program protection: Open Artery ICP Programmer—User system data—
Untick the sectors that do not require erase and program protection—Apply to device.
Artery ISP Programmer (BOOT0=1)
Enable erase and program protection: Protection/Enable/Erase and program protection—
Next—Yes, erase and program protection enabled.
Disable erase and program protection: Protection/Disable/Erase and program protection—
Next—Yes, erase and program protection disabled.
Artery ISP Multi-Port Programmer (BOOT0=1)
Enable erase and program protection: Protection/Enable/Erase and program protection—
Start—Yes, enabled.
Disable erase and program protection: Protection/Disable/Erase and program protection—
Start—Yes, disabled.
Figure 24. Enable erase and program protection in ICP Programmer

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Figure 25. Disable erase and program protection in ICP Programmer
Note: Once enabled, the erase and program protection cannot be disabled through erase operation.
Set boot memory as main Flash memory extension area
By default, boot memory stores the original boot codes in BOOT mode. For AT32F421 series MCUs,
the boot memory also can be used as the main Flash memory extension area (AP mode) to store
user-defined codes.
Note: The boot memory AP mode can only be set once, and the BOOT mode function of the original
boot memory cannot be restored after setting.
The user can use Artery ICP Programmer to set the boot memory as the main Flash memory
extension area as follows:
Connect AT-Link/J-Link emulator to AT-START-F421 board and power on;
Open Artery ICP programmer and select AT-Link/J-Link to connect;
Target—Boot memory AP mode—OK.

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Figure 26. Set AP mode in ICP Programmer
To prevent misoperations, the user needs to manually enter the enable key 0xA35F6D24, and
then the “Flash info” interface will display a success or failure message.
Figure 27. AP mode enabling in ICP Programmer
The user can use Artery ICP Programmer to set the boot memory as the main Flash memory
extension area (in mass production) as follows:
Connect AT-Link emulator to AT-START-F421 board and power on;
Note: The on-board AT-Link EZ does not support offline programming. If necessary, please use AT-Link other
than EZ version.

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Open Artery ICP programmer and select AT-Link to connect;
AT-Link Setting—AT-Link offline config settings;
Generate an offline project as follows:
1. Click on “Create”;
2. Enter project name;
3. Select MCU part number;
4. Add .hex file
5. Select SWD as the download interface;
6. Tick boot memory AP mode and enter the key;
7. Save project to AT-Link or save project file.
Complete other relevant settings as necessary.
Figure 28. Offline config settings in ICP Programmer
If you select “Save project file”, the project will be saved as an .atcp file for easy loading to other
versions of AT-Link.
The following window (as shown in Figure 29) will pop up in operation. If you tick “This project is
only used at the specific AT-Link”, this project file will be bound to a specific AT-Link and can
only be used on this AT-Link, and you need to set the AT-Link serial number. If you tick “This
project is only used once”, this project file can only be used once on the same AT-Link.