ARTERY AT32F425 Series User manual

AT32F425 Series Reference Manual
2022.03.30 Page 1 Ver 2.01
ARM®-based 32-bit Cortex®-M4F MCU with 32 to 64 KB Flash, sLib, CAN,
OTGFS, 13 timers, ADC, 12 communication interfaces
Feature
Core: ARM®32-bit Cortex®-M4F CPU
−96 MHz maximum frequency, with a Memory
Protection Unit (MPU), single-cycle multiplication
and hardware division
−DSP instructions
Memories
−32 to 64 KBytes of Flash memory
−4 Kbytes of boot code area used as a Bootloader or
as a general instruction/data memory (one-time-
configured)
−sLib: configurable part of main Flash set as a library
area with code excutable but secured, non-readable
−20 KBytes of SRAM
Power control (PWC)
−2.4 V ~ 3.6 V application suppy
−Power-on reset (POR)/ low-voltage reset (LVR), and
power voltage monitor (PVM)
−Low power: Sleep, Deepsleep, and Standby modes,
6 WKUP pins can wake up Standby mode
−5 x 32-bit battery power registers (BPR)
Clock and reset management (CRM)
−4 to 25 MHz crystal oscillator (HEXT)
−Internal 48 MHz factory-trimmed clock (HICK),
accuracy 1% at TA=25 °C, 2.5 % at TA=-40 to
+105 °C, with automatic clock calibration (ACC)
−PLL with configurable frequency multiplication and
division factor
−32.768 kHz crystal oscillator (LEXT)
−Internal 40 kHz RC oscillator (LICK)
Analog
−1 x 12-bit 2 MSPS A/D converter, up to 16 input
channels, hardware over-sampling up to equivalent
16-bit resolution
−Internal reference voltage (VINTRV)
DMA:
−1 x DMA controller for flexible mapping support
−7 channels in all
Up to 55 Fast I/O Interfaces
−All mappable to 16 external interrupt vectors
−Almost 5 V-tolerant
Up to 3 Timers (TMR)
−1 x 16-bit7-channel advanced timer, 6- channel PWM
output with dead-time generator and emergency stop
−Up to6 x 16-bit and 1 x 32-bit general-purpose timers,
each with 4 IC/OC/PWM or pulsecounter and
quadrature (incremental) encoder input
−Advancedand general-purpose timers provide up to 24-
channel PWM
−2 x 16-bitbasic timers
−2 x Watchdog timers (WDT and WWDT)
−SysTick timer: 24-bitdowncounter
ERTC: enhanced RTC with auto wakeup, alarm,
subsecond precision, hardware calendar and
calibration feature
Up to 12 communication interfaces
−Up to2 x I2Cinterfaces (SMBus/PMBus)
−Up to4 x USARTs,support master synchronous SPIand
modem control, with ISO7816 interface, LIN, IrDA and
RS485 driver enable;support TX/RX swap
−Up to3 x SPIs (36 Mbit/s), all with I2S interface
multiplexed, I2S2/ I2S3support full-duplex
−CANinterface (2.0B Active), with 256 bytes of dedicated
SRAM
−OTG full speed interface, with 1280 bytesof dedicated
SRAM, supportingcrystal-less in device mode
−Infrared transmitter (IRTMR)
CRC Calculation Unit
96-bit ID (UID)
Debug mode
−Serial wire debug (SWD) and serial wire output (SWO)
Temperature range: -40 to 105℃
Packaging
−LQFP64 10 x 10 mm LQFP32 7 x7 mm
−LQFP64 7 x7 mm LQFP48 7 x7 mm
−QFN48 6 x 6 mm QFN32 4 X 4 mm
−TSSOP20 6.5 x 4.4 mm
List of Models
Internal Flash
Model
64 KBytes
AT32F425R8T7, AT32F425R8T7 -7, AT32F425C8T7,
AT32F425C8U7, AT32F425K8T7, AT32F425K8U7-4,
AT32F425F8P7
32 KBytes
A T32F425R6T7, AT32F425R6T7 -7, AT32F425C6T7,
AT32F425C6U7, AT32F425K6T7, AT32F425K6U7-4,
AT32F425F6P7

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Contents
1System architecture...................................................................... 30
1.1 System overview..........................................................................32
1.1.1 ARM CortexTM-M4 processor........................................................ 32
1.1.2 Bit band...................................................................................... 32
1.1.3 Interrupt and exception vectors .................................................... 34
1.1.4 System Tick (SysTick) ................................................................. 36
1.1.5 Reset ......................................................................................... 36
1.2 List of abbreviations for registers ..................................................38
1.3 Device characteristics information.................................................38
1.3.1 Flash memory size register .......................................................... 38
1.3.2 Device electronic signature.......................................................... 38
2Memory resources ........................................................................ 39
2.1 Internal memory address map.......................................................39
2.2 Flash memory..............................................................................40
2.3 SRAM memory.............................................................................40
2.4 Peripheral address map................................................................41
3Power control (PWC)..................................................................... 43
3.1 Introduction .................................................................................43
3.2 Main Features .............................................................................43
3.3 POR/LVR ....................................................................................44
3.4 Power voltage monitor (PVM)........................................................44
3.5 Power domain..............................................................................45
3.6 Power saving modes ....................................................................45
3.7 PWC registers .............................................................................46
3.7.1 Power control register (PWC_CTRL) ............................................ 47
3.7.2 Power control/status register (PWC_CTRLSTS) ............................ 47
3.7.3 Power control register2 (PWC_CTRL2) ......................................... 48
4Clock and reset manage (CRM) ..................................................... 49
4.1 Clock ..........................................................................................49

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4.1.1 Clock sources ............................................................................. 49
4.1.2 System clock............................................................................... 50
4.1.3 Peripheral clock .......................................................................... 50
4.1.4 Clock fail detector ....................................................................... 51
4.1.5 Clock output................................................................................ 51
4.1.6 Interrupts.................................................................................... 51
4.2 Reset..........................................................................................51
4.2.1 System reset............................................................................... 51
4.2.2 Battery powered domain reset...................................................... 52
4.3 CRM registers .............................................................................52
4.3.1 Clock control register (CRM_CTRL).............................................. 53
4.3.2 Clock configuration register (CRM_CFG) ...................................... 54
4.3.3 Clock interrupt register (CRM_CLKINT) ........................................ 55
4.3.4 APB2 peripheral reset register (CRM_APB2RST) .......................... 57
4.3.5 APB1 peripheral reset register1 (CRM_APB1RST) ........................ 57
4.3.6 APB peripheral clock enable register (CRM_AHBEN)..................... 58
4.3.7 APB2 peripheral clock enable register (CRM_AHB2EN) ................. 59
4.3.8 APB1 peripheral clock enable register (CRM_AHB1EN)................. 60
4.3.9 Battery powered domain control register (CRM_BPDC).................. 61
4.3.10 Control/status register (CRM_CTRLSTS) ...................................... 61
4.3.11 APB peripheral reset register (CRM_APBRST).............................. 62
4.3.12 PLL configuration register (CRM_PLL).......................................... 62
4.3.13 Additional register1 (CRM_MISC1) ............................................... 63
4.3.14 Additional register2 (CRM_MISC2) ............................................... 64
5Flash memory controller (FLASH)................................................. 65
5.1 FLASH introduction......................................................................65
5.2 Flash memory operation ...............................................................67
5.2.1 Unlock/lock ................................................................................. 67
5.2.2 Erase operation........................................................................... 67
5.2.3 Programming operation................................................................ 69
5.2.4 Read operation ........................................................................... 70
5.3 Main Flash memory extension area ...............................................70
5.4 User system data area operation...................................................70
5.4.1 Unlock/lock ................................................................................. 70

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5.4.2 Erase operation........................................................................... 71
5.4.3 Programming operation................................................................ 72
5.4.4 Read operation ........................................................................... 73
5.5 Flash memory protection ..............................................................73
5.5.1 Access protection........................................................................ 73
5.5.2 Erase/program protection............................................................. 74
5.6 Special functions .........................................................................75
5.6.1 Security library settings ............................................................... 75
5.6.2 Bootloader code area used as Flash memory extension................. 76
5.6.3 CRC verify .................................................................................. 76
5.7 Flash memory registers ................................................................76
5.7.1 Flash performance select register (FLASH_PSR) .......................... 77
5.7.2 Flash unlock register (FLASH_UNLOCK) ...................................... 77
5.7.3 Flash user system data unlock register (FLASH_USD_UNLOCK) ... 78
5.7.4 Flash status register (FLASH_STS) .............................................. 78
5.7.5 Flash control register (FLASH_CTRL)........................................... 78
5.7.6 Flash address register (FLASH_ADDR) ........................................ 79
5.7.7 User system data register (FLASH_USD)...................................... 79
5.7.8 Erase/program protection status register (FLASH_EPPS) .............. 80
5.7.9 Flash security library status register0 (SLIB_STS0)....................... 80
5.7.10 Flash security library status register1 (SLIB_STS1)....................... 80
5.7.11 Security library password clear register (SLIB_PWD_CLR) ............ 81
5.7.12 Security library additional status register (SLIB_MISC_STS).......... 81
5.7.13 Flash CRC address register (FLASH_CRC_ARR) .......................... 81
5.7.14 Flash CRC control register (FLASH_CRC_CTRL) .......................... 81
5.7.15 Flash CRC check result register (FLASH_CRC_CHKR).................. 82
5.7.16 Security library password setting register (SLIB_SET_PWD).......... 82
5.7.17 Security library address setting register (SLIB_SET_RANGE) ........ 82
5.7.18 Flash extension memory security library setting register (EM_SLIB_SET)
83
5.7.19 Boot mode setting register (BTM_MODE_SET) ............................. 83
5.7.20 Security library unlock register (FLASH_UNLOCK) ........................ 83
6GPIOs and IOMUX ......................................................................... 84
6.1 Introduction .................................................................................84

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6.2 Function overview........................................................................84
6.2.1 GPIO structure............................................................................ 84
6.2.2 GPIO reset status........................................................................ 85
6.2.3 General-purpose input configuration............................................. 85
6.2.4 Analog input/output configuration ................................................. 85
6.2.5 General-purpose output configuration........................................... 85
6.2.6 GPIO port protection ................................................................... 86
6.2.7 IOMUX structure ......................................................................... 86
6.2.8 Multiplexed function pull-up/down configuration ............................ 86
6.2.9 IOMUX input/output ..................................................................... 87
6.2.10 Peripheral MUX function configuration.......................................... 90
6.2.11 IOMUX mapping priority............................................................... 90
6.2.12 External interrupt/wake-up lines ................................................... 90
6.3 GPIO registers.............................................................................90
6.3.1 GPIO configuration register (GPIOx_CFGR) (x=A/B/C/D/F) ............ 91
6.3.2 GPIO output mode register (GPIOx_OMODER) (x=A/B/C/D/F) ....... 91
6.3.3 GPIO drive capability register (GPIOx_ODRVR) (x=A/B/C/D/F) ...... 91
6.3.4 GPIO pull-up/pull-down register (GPIOx_PULL) (x=A/B/C/D/F)....... 91
6.3.5 GPIO input register (GPIOx_IDH) (x=A/B/C/D/F) ........................... 92
6.3.6 GPIO output register (GPIOx_IDH) (x= A/B/C/D/F) ........................ 92
6.3.7 GPIO set/clear register (GPIOx_SCR) (x=A/B/C/D/F)..................... 92
6.3.8 GPIO write protection register (GPIOx_WPR) (x=A/B/C/D/F) .......... 92
6.3.9 GPIO multiplexed function low register (GPIOx_MUXL) (x= A/B/C/D/F)93
6.3.10 GPIO multiplexed function high register (GPIOx_MUXH) (x= A/B/C/D/F)
93
6.3.11 GPIO port bit clear register (GPIOx_CLR) (x=A/B/C/D/F) ............... 93
6.3.12 GPIO huge current control register (GPIOx_HDRV) (x= A/B/C/D/F) 93
7System configuration controller (SCFG) ....................................... 94
7.1 Introduction .................................................................................94
7.2 SCFG registers............................................................................94
7.2.1 SCFG configuration register1 (SCFG_CFG1) ................................ 94
7.2.2 SCFG external interrupt configuration register1 (SCFG_ EXINTC1) 95
7.2.3 SCFG external interrupt configuration register2 (SCFG_ EXINTC2) 96
7.2.4 SCFG external interrupt configuration register3 (SCFG_ EXINTC3) 97

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7.2.5 SCFG external interrupt configuration register4 (SCFG_ EXINTC4) 97
7.2.6 SCFG configuration register2 (SCFG_CFG2) ................................ 98
8External interrupt/Event controller (EXINT) .................................. 99
8.1 EXINT introduction.......................................................................99
8.2 Function overview and configuration procedure ..............................99
8.3 EXINT registers ......................................................................... 100
8.3.1 Interrupt enable register (EXINT_INTEN).....................................100
8.3.2 Event enable register (EXINT_EVTEN) ........................................100
8.3.3 Polarity configuration register1 (EXINT_ POLCFG1).....................100
8.3.4 Polarity configuration register2 (EXINT_ POLCFG2).....................101
8.3.5 Software trigger register (EXINT_ SWTRG)..................................101
8.3.6 Interrupt status register (EXINT_ INTSTS) ...................................101
9DMA controller (DMA) ................................................................. 102
9.1 Introduction ............................................................................... 102
9.2 Main features ............................................................................ 102
9.3 Function overview...................................................................... 102
9.3.1 DMA configuration......................................................................102
9.3.2 Handshake mechanism...............................................................103
9.3.3 Arbiter .......................................................................................103
9.3.4 Programmable data transfer width ...............................................103
9.3.5 Errors ........................................................................................104
9.3.6 Interrupts...................................................................................105
9.3.7 Flexible DMA request mapping....................................................105
9.4 DMA registers............................................................................ 106
9.4.1 DMA interrupt status register (DMA_STS)....................................107
9.4.2 DMA interrupt flag clear register (DMA_CLR) ...............................108
9.4.3 DMA channel-x configuration register (DMA_CxCTRL) (x = 1…7) ..110
9.4.4 DMA channel-x number of data register (DMA_CxDTCNT)
(x = 1…7) ............................................................................................111
9.4.5 DMA channel-x peripheral address register (DMA_CxPADDR)
(x = 1…7) ............................................................................................111
9.4.6 DMA channel-x memory address register (DMA_CxMADDR)
(x = 1…7) ............................................................................................111

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9.4.7 DMA channel source register (DMA_SRC_SEL0)..........................112
9.4.8 DMA channel source register1 (DMA_SRC_SEL1)........................112
10 CRC calculation unit (CRC)......................................................... 113
10.1 CRC introduction ....................................................................... 113
10.2 CRC registers............................................................................ 113
10.2.1 Data register (CRC_DT)..............................................................113
10.2.2 Common data register (CRC_CDT)..............................................113
10.2.3 Control register (CRC_CTRL)......................................................114
10.2.4Initialization register (CRC_IDT) .................................................114
11 I2C interface ................................................................................ 115
11.1 I2C introduction.......................................................................... 115
11.2 I2C main features....................................................................... 115
11.3 I2C function overview ................................................................. 115
11.4 I2C interface .............................................................................. 116
11.4.1 I2C timing control .......................................................................118
11.4.2 Data transfer management..........................................................119
11.4.3 I2C master communication flow ...................................................120
11.4.4 I2C slave communication flow......................................................125
11.4.5 SMBus.......................................................................................129
11.4.6 SMBus master communication flow..............................................131
11.4.7 SMBus slave communication flow................................................135
11.4.8 Data transfer using DMA.............................................................139
11.4.9 Error management......................................................................139
11.5 I2C interrupt requests ................................................................. 141
11.6 I2C debug mode......................................................................... 141
11.7 I2C registers .............................................................................. 141
11.7.1 Control register1 (I2C_CTRL1)....................................................142
11.7.2 Control register2 (I2C_CTRL2)....................................................143
11.7.3 Own address register1 (I2C_OADDR1) ........................................143
11.7.4 Own address register2 (I2C_OADDR2) ........................................144
11.7.5 Timing register (I2C_CLKCTRL) ..................................................144
11.7.6 Timeout register (I2C_TIMEOUT) ................................................144
11.7.7 Status register (I2C_STS)...........................................................145

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11.7.8 Status clear register (I2C_CLR) ..................................................146
11.7.9 PEC register (I2C_PEC) .............................................................146
11.7.10 Receive data register (I2C_RXDT)............................................146
11.7.11 Transmit data register (I2C_TXDT) ...........................................146
12 Universal synchronous/asynchronous receiver/transmitter (USART)147
12.1 USART introduction ................................................................... 147
12.2 Full-duplex/half-duplex selector .................................................. 149
12.3 Mode selector............................................................................ 149
12.3.1 Introduction................................................................................149
12.3.2 Configuration procedure .............................................................149
12.4 USART frame format and configuration........................................ 150
12.5 DMA transfer introduction ........................................................... 150
12.5.1 Transmission using DMA ............................................................150
12.5.2 Reception using DMA .................................................................150
12.6 Baud rate generation.................................................................. 151
12.6.1 Introduction................................................................................151
12.6.2 Configuration .............................................................................151
12.7 Transmitter................................................................................ 152
12.7.1 Transmitter introduction..............................................................152
12.7.2 Transmitter configuration ............................................................152
12.8 Receiver ................................................................................... 152
12.8.1 Receiver introduction..................................................................152
12.8.2 Receiver configuration................................................................153
12.8.3 Start bit and noise detection .......................................................154
12.9 Tx/Rx swap ............................................................................... 154
12.10Interrupt requests ...................................................................... 155
12.11I/O pin control............................................................................ 156
12.12USART registers........................................................................ 156
12.12.1 Status register (USART_STS) ..................................................156
12.12.2 Data register (USART_DT).......................................................157
12.12.3 Baud rate register (USART_BAUDR) ........................................157
12.12.4 Control register1 (USART_CTRL1) ...........................................157
12.12.5 Control register2 (USART_CTRL2) ...........................................159

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12.12.6 Control register3 (USART_CTRL3) ...........................................160
12.12.7 Guard time and divider register (USART_GDIV) ........................161
13 Serial peripheral interface (SPI).................................................. 162
13.1 SPI introduction......................................................................... 162
13.2 Function overview...................................................................... 162
13.2.1 SPI description...........................................................................162
13.2.2 Full-duplex/half-duplex selector ..................................................163
13.2.3 Chip select controller..................................................................165
13.2.4 SPI_SCK controller ....................................................................166
13.2.5 CRC ..........................................................................................166
13.2.6 DMA transfer..............................................................................167
13.2.7 TI mode .....................................................................................167
13.2.8 Transmitter ................................................................................168
13.2.9 Receiver ....................................................................................168
13.2.10 Motorola mode ........................................................................169
13.2.11 TI mode ..................................................................................171
13.2.12 Interrupts ................................................................................172
13.2.13 IO pin control ..........................................................................172
13.2.14 Precautions.............................................................................173
13.3 I2S functional description............................................................ 173
13.3.1 I2S introduction ..........................................................................173
13.3.2 I2S full-duplex ............................................................................174
13.3.3 Operating mode selector.............................................................174
13.3.4 Audio protocol selector ...............................................................176
13.3.5 I2S_CLK controller .....................................................................177
13.3.6 DMA transfer..............................................................................178
13.3.7 Transmitter/Receiver ..................................................................179
13.3.8 I2S communication timings .........................................................179
13.3.9 Interrupts...................................................................................180
13.3.10 IO pin control ..........................................................................180
13.4 SPI registers ............................................................................. 181
13.4.1 SPI control register1 (SPI_CTRL1) (Not used in I2S mode) ...........181
13.4.2 SPI control register2 (SPI_CTRL2) ..............................................182
13.4.3 SPI status register (SPI_STS) .....................................................183

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13.4.4 SPI data register (SPI_DT) .........................................................184
13.4.5 SPICRC register (SPI_CPOLY) (Not used in I2S mode).................184
13.4.6 SPIRxCRC register (SPI_RCRC) (Not used in I2S mode) ..............184
13.4.7 SPITxCRC register (SPI_TCRC)..................................................184
13.4.8 SPI_I2S register (SPI_I2SCTRL) .................................................184
13.4.9 SPI_I2S prescaler register (SPI_I2SCLKP) ..................................185
14 Timer .......................................................................................... 186
14.1 Basic timer (TMR6 and TMR7) .................................................... 187
14.1.1 TMR6 and TMR7 introduction......................................................187
14.1.2 TMR6 and TMR7 main features ...................................................187
14.1.3 TMR6 and TMR7 function overview .............................................187
14.1.3.1 Count clock .......................................................................... 187
14.1.3.2 Counting mode ..................................................................... 187
14.1.3.3 Debug mode ......................................................................... 188
14.1.4 TMR6 and TMR7 registers ..........................................................188
14.1.4.1 TMR6 and TMR7 control register1 (TMRx_CTRL1)................... 188
14.1.4.2 TMR6 and TMR7 control register2 (TMRx_CTRL2)................... 189
14.1.4.3 TMR6 and TMR7 DMA/interrupt enable register (TMRx_IDEN) .. 189
14.1.4.4 TMR6 and TMR7 interrupt status register (TMRx_ISTS) ........... 189
14.1.4.5 TMR6 and TMR7 software event register (TMRx_SWEVT) ........ 190
14.1.4.6 TMR6 and TMR7 counter value (TMRx_CVAL) ........................ 190
14.1.4.7 TMR6 and TMR7 division (TMRx_DIV) .................................... 190
14.1.4.8 TMR6 and TMR7 period register (TMRx_PR) ........................... 190
14.2 General-purpose timer (TMR2 and TMR3).................................... 190
14.2.1 TMR2 and TMR3 introduction......................................................190
14.2.2 TMR2 and TMR3 main features ...................................................190
14.2.3 TMR2 and TMR3 functional overview...........................................191
14.2.3.1 Count clock .......................................................................... 191
14.2.3.2 Counting mode ..................................................................... 193
14.2.3.3 TMR input function................................................................ 195
14.2.3.4 TMR output function.............................................................. 196
14.2.3.5 TMR synchronization............................................................. 198
14.2.3.6 Debug mode ......................................................................... 201
14.2.4 TMR2 and TMR3 registers ..........................................................201
14.2.4.1 TMR2 and TMR3 control register1 (TMRx_CTRL1)................... 202
14.2.4.2 TMR2 and TMR3 control register2 (TMRx_CTRL2)................... 203

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14.2.4.3 TMR2 and TMR3 slave timer control register (TMRx_STCTRL) . 203
14.2.4.4 TMR2 and TMR3 DMA/interrupt enable register (TMRx_IDEN) .. 204
14.2.4.5 TMR2 and TMR3 interrupt status register (TMRx_ISTS) ........... 205
14.2.4.6 TMR2 and TMR3 software event register (TMRx_SWEVT) ........ 206
14.2.4.7 TMR2 and TMR3 channel mode register1 (TMRx_CM1)............ 206
14.2.4.8 TMR2 and TMR3 channel mode register2 (TMRx_CM2)............ 208
14.2.4.9 TMR2 and TMR3 channel control register (TMRx_CCTRL)........ 209
14.2.4.10 TMR2 and TMR3 counter value (TMRx_CVAL)..................... 209
14.2.4.11 TMR2 and TMR3 division value (TMRx_DIV) ....................... 210
14.2.4.12 TMR2 and TMR3 period register (TMRx_PR)....................... 210
14.2.4.13 TMR2 and TMR3 channel 1 data register (TMRx_C1DT)....... 210
14.2.4.14 TMR2 and TMR3 channel 2 data register (TMRx_C2DT)....... 210
14.2.4.15 TMR2 and TMR3 channel 3 data register (TMRx_C3DT)....... 210
14.2.4.16 TMR2 and TMR3 channel 4 data register (TMRx_C4DT)....... 211
14.2.4.17 TMR2 and TMR3 DMA control register (TMRx_DMACTRL) ... 211
14.2.4.18 TMR2 and TMR3 DMA data register (TMRx_DMADT) ........... 211
14.3 General-purpose timer (TMR9 to TMR14) .................................... 211
14.3.1 TMR13 and TMR14 introduction ..................................................211
14.3.2 TMR13 and TMR14 main features ...............................................211
14.3.3 TMR13 and TMR14 functional overview .......................................212
14.3.3.1 Count clock .......................................................................... 212
14.3.3.2 Counting mode ..................................................................... 212
14.3.3.3 TMR input function................................................................ 213
14.3.3.4 TMR output function.............................................................. 214
14.3.3.5 Debug mode ......................................................................... 215
14.3.4 TMR13 and TMR14 registers.......................................................215
14.3.4.1 TMR13 and TMR14 control register1 (TMRx_CTRL1) ............... 216
14.3.4.2 TMR13 and TMR14 DMA/interrupt enable register (TMRx_IDEN)216
14.3.4.3 TMR13 and TMR14 interrupt status register (TMRx_ISTS)........ 217
14.3.4.4 TMR13 and TMR14 software event register (TMRx_SWEVT) .... 217
14.3.4.5 TMR13 and TMR14 channel mode register1 (TMRx_CM1) ........ 217
14.3.4.6 TMR13 and TMR14 channel control register (TMRx_CCTRL) .... 219
14.3.4.7 TMR13 and TMR14 counter value (TMRx_CVAL) ..................... 219
14.3.4.8 TMR13 and TMR14 division value (TMRx_DIV)........................ 219
14.3.4.9 TMR13 and TMR14 period register (TMRx_PR) ....................... 219
14.3.4.10 TMR13 and TMR14 channel 1 data register (TMRx_C1DT) ... 220
14.3.4.11 TMR14 channel input remap register (TMR14_RMP) ............ 220
14.4 General-purpose timer (TMR15).................................................. 220

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14.4.1 TMR15 introduction ....................................................................220
14.4.2TMR15 main features .................................................................220
14.4.3 TMR15 functional overview .........................................................221
14.4.3.1 Count clock .......................................................................... 221
14.4.3.2 Counting mode ..................................................................... 222
14.4.3.3 TMR input function................................................................ 223
14.4.3.4 TMR output function.............................................................. 224
14.4.3.5 TMR break function............................................................... 227
14.4.3.6 TMR synchronization............................................................. 228
14.4.3.7 Debug mode ......................................................................... 229
14.4.4 TMR15 registers.........................................................................229
14.4.4.1 TMR15 control register1 (TMR15_CTRL1)............................... 230
14.4.4.2 TMR15 control register2 (TMR15_CTRL2)............................... 230
14.4.4.3 TMR15 slave timer control register (TMR15_STCTRL) ............. 231
14.4.4.4 TMR15 DMA/interrupt enable register (TMR15_IDEN) .............. 231
14.4.4.5 TMR15 interrupt status register (TMR15_ISTS) ....................... 232
14.4.4.6 TMR15 software event register (TMR15_SWEVT) .................... 233
14.4.4.7 TMR15 channel mode register1 (TMR15_CM1) ........................ 233
14.4.4.8 TMR15 Channel control register (TMR15_CCTRL) ................... 235
14.4.4.9 TMR15 counter value (TMR15_CVAL)..................................... 237
14.4.4.10 TMR15 division value (TMR15_DIV) ................................... 237
14.4.4.11 TMR15 period register (TMR15_PR) ................................... 237
14.4.4.12 TMR15 repetition period register (TMR15_RPR) .................. 237
14.4.4.13 TMR15 channel 1 data register (TMR15_C1DT)................... 237
14.4.4.14 TMR15 channel 2 data register (TMR15_C2DT) ................... 237
14.4.4.15 TMR15 break register (TMR15_BRK) .................................. 238
14.4.4.16 TMR15 DMA control register (TMR15_DMACTRL)................ 239
14.4.4.17 TMR15 DMA data register (TMR15_DMADT) ....................... 239
14.5 General-purpose timers (TMR16 and TMR17) .............................. 239
14.5.1 TMR16 and TMR17 introduction ..................................................239
14.5.2 TMR16 and TMR17 main features ...............................................240
14.5.3 TMR16 and TMR17 functional overview .......................................240
14.5.3.1 Count clock .......................................................................... 240
14.5.3.2 Counting mode ..................................................................... 240
14.5.3.3 TMR input function................................................................ 241
14.5.3.4 TMR output function.............................................................. 242
14.5.3.5 TMR break function............................................................... 244
14.5.3.6 Debug mode ......................................................................... 245

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14.5.4 TMR16 and TM17 registers .........................................................245
14.5.4.1 TMR16 and TMR17 control register1 (TMRx_CTRL1) ............... 246
14.5.4.2 TMR16 and TMR17 control register2 (TMRx_CTRL2) ............... 246
14.5.4.3 TMR16 and TMR17 DMA/interrupt enable register (TMRx_IDEN)247
14.5.4.4 TMR16 and TMR17 interrupt status register (TMRx_ISTS)........ 247
14.5.4.5 TMR16 and TMR17 software event register (TMRx_SWEVT) .... 248
14.5.4.6 TMR16 and TMR17 channel mode register1 (TMRx_CM1) ........ 248
14.5.4.7 TMR16 and TMR17 Channel control register (TMRx_CCTRL) ... 250
14.5.4.8 TMR16 and TMR17 counter value (TMRx_CVAL) ..................... 251
14.5.4.9 TMR16 and TMR17 division value (TMRx_DIV)........................ 251
14.5.4.10 TMR16 and TMR17 period register (TMRx_PR) ................... 251
14.5.4.11 TMR16 and TMR17 repetition period register (TMRx_RPR) .. 251
14.5.4.12 TMR16 and TMR17 channel 1 data register (TMRx_C1DT) ... 251
14.5.4.13 TMR16 and TMR17 break register (TMRx_BRK) .................. 252
14.5.4.14 TMR16 and TMR17 DMA control register (TMRx_DMACTRL) 253
14.5.4.15 TMR16 and TMR17 DMA data register (TMRx_DMADT) ....... 253
14.6 Advanced-control timers (TMR1) ................................................. 253
14.6.1 TMR1 introduction ......................................................................253
14.6.2 TMR1 main features ...................................................................254
14.6.3 TMR1 functional overview...........................................................254
14.6.3.1 Count clock .......................................................................... 254
14.6.3.2 Counting mode ..................................................................... 256
14.6.3.3 TMR input function................................................................ 259
14.6.3.4 TMR output function.............................................................. 260
14.6.3.5 TMR break function............................................................... 263
14.6.3.6 TMR synchronization............................................................. 263
14.6.3.7 Debug mode ......................................................................... 264
14.6.4 TMR1 registers ..........................................................................265
14.6.4.1 TMR1 control register1 (TMR1_CTRL1) .................................. 265
14.6.4.2 TMR1 control register2 (TMR1_CTRL2) .................................. 266
14.6.4.3 TMR1 slave timer control register (TMR1_STCTRL) ................. 267
14.6.4.4 TMR1 DMA/interrupt enable register (TMR1_IDEN).................. 268
14.6.4.5 TMR1 interrupt status register (TMR1_ISTS) ........................... 269
14.6.4.6 TMR1 software event register (TMR1_SWEVT)........................ 270
14.6.4.7 TMR1 channel mode register1 (TMR1_CM1) ........................... 270
14.6.4.8 TMR1 channel mode register2 (TMR1_CM2) ........................... 272
14.6.4.9 TMR1 Channel control register (TMR1_CCTRL)....................... 273
14.6.4.10 TMR1 counter value (TMR1_CVAL) .................................... 275

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14.6.4.11 TMR1 division value (TMR1_DIV) ....................................... 275
14.6.4.12 TMR1 period register (TMR1_PR)....................................... 275
14.6.4.13 TMR1 repetition period register (TMR1_RPR)...................... 275
14.6.4.14 TMR1 channel 1 data register (TMR1_C1DT) ...................... 275
14.6.4.15 TMR1 channel 2 data register (TMR1_C2DT) ...................... 275
14.6.4.16 TMR1 channel 3 data register (TMR1_C3DT) ...................... 276
14.6.4.17 TMR1 channel 4 data register (TMRx_C4DT)....................... 276
14.6.4.18 TMR1 break register (TMR1_BRK)...................................... 276
14.6.4.19 TMR1 DMA control register (TMR1_DMACTRL) ................... 277
14.6.4.20 TMR1 DMA data register (TMR1_DMADT)........................... 278
14.6.4.21 TMR1 channel mode register3 (TMR1_ CM3) ...................... 278
14.6.4.22 TMR1 channel 5 data register (TMR1_C5DT) ...................... 278
15 Window watchdog timer (WWDT) ................................................ 279
15.1 WWDT introduction .................................................................... 279
15.2 WWDT main features ................................................................. 279
15.3 WWDT functional overview ......................................................... 279
15.4 Debug mode.............................................................................. 280
15.5 WWDT registers ........................................................................ 280
15.5.1 Control register (WWDT_CTRL) ..................................................280
15.5.2 Configuration register (WWDT_CFG)...........................................280
15.5.3 Status register (WWDT_STS)......................................................281
16 Watchdog timer (WDT) ................................................................ 282
16.1 WDT introduction ....................................................................... 282
16.2 WDT main features .................................................................... 282
16.3 WDT functional overview ............................................................ 282
16.4 Debug mode.............................................................................. 283
16.5 WDT registers ........................................................................... 283
16.5.1 Command register (WDT_CMD) ..................................................284
16.5.2 Divider register (WDT_DIV).........................................................284
16.5.3 Reload register (WDT_RLD)........................................................284
16.5.4 Status register (WDT_STS).........................................................284
16.5.5 Window register (WDT_WIN).......................................................284
17 Enhanced real-time clock (ERTC) ............................................... 285

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17.1 ERTC introduction...................................................................... 285
17.2 ERTC main features................................................................... 285
17.3 ERTC function overview ............................................................. 285
17.3.1 ERTC clock................................................................................285
17.3.2 ERTC initialization......................................................................286
17.3.3 Periodic automatic wakeup .........................................................288
17.3.4 ERTC calibration ........................................................................288
17.3.5 Time stamp function ...................................................................289
17.3.6 Tamper detection .......................................................................289
17.3.7 Multiplexed function output .........................................................290
17.3.8 ERTC wakeup ............................................................................290
17.4 ERTC registers.......................................................................... 291
17.4.1 ERTC time register (ERTC_TIME) ...............................................291
17.4.2 ERTC date register (ERTC_DATE) ..............................................291
17.4.3 ERTC control register (ERTC_CTRL)...........................................292
17.4.4 ERTC initialization and status register (ERTC_STS).....................293
17.4.5 ERTC divider register (ERTC_DIV)..............................................294
17.4.6 ERTC wakeup timer register (ERTC_WAT) ..................................295
17.4.7 ERTC alarm clock A register (ERTC_ALA) ...................................295
17.4.8 ERTC write protection register (ERTC_WP) .................................295
17.4.9 ERTC subsecond register (ERTC_SBS) .......................................295
17.4.10 ERTC time adjustment register (ERTC_TADJ) ...........................295
17.4.11 ERTC time stamp time register (ERTC_TSTM) ..........................296
17.4.12 ERTC time stamp date register (ERTC_TSDT) ..........................296
17.4.13 ERTC time stamp subsecond register (ERTC_TSSBS) ...............296
17.4.14 ERTC smooth calibration register (ERTC_SCAL) .......................296
17.4.15 ERTC tamper configuration register (ERTC_TAMP) ...................297
17.4.16 ERTC alarm clock A subsecond register (ERTC_ALASBS) .........298
17.4.17 ERTC battery powered domain data register (ERTC_BPRx) .......298
18 Analog-to-digital converter (ADC)............................................... 299
18.1 ADC introduction ....................................................................... 299
18.2 ADC main features..................................................................... 299
18.3 ADC structure............................................................................ 299
18.4 ADC functional overview............................................................. 300

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18.4.1 Channel management.................................................................300
18.4.1.1 Internal reference voltage...................................................... 301
18.4.2 ADC operation process...............................................................301
18.4.2.1 Power-on and calibration ....................................................... 301
18.4.2.2 Trigger................................................................................. 302
18.4.2.3 Sampling and conversion sequence........................................ 302
18.4.3 Conversion sequence management .............................................303
18.4.3.1 Sequence mode .................................................................... 303
18.4.3.2 Automatic preempted group conversion mode ......................... 303
18.4.3.3 Repetition mode.................................................................... 304
18.4.3.4 Partition mode ...................................................................... 304
18.4.4 Oversampling.............................................................................304
18.4.4.1 Oversampling of ordinary group of channels............................ 305
18.4.4.2 Oversampling of preempted group of channels ........................ 306
18.4.5 Data management ......................................................................307
18.4.5.1 Data alignment ..................................................................... 307
18.4.5.2 Data read ............................................................................. 307
18.4.6 Voltage monitoring .....................................................................307
18.4.7 Status flag and interrupts............................................................308
18.5 ADC registers............................................................................ 308
18.5.1 ADC status register (ADC_STS) ..................................................308
18.5.2 ADC control register1 (ADC_CTRL1) ...........................................309
18.5.3 ADC control register2 (ADC_CTRL2) ...........................................310
18.5.4 ADC sampling time register 1 (ADC_SPT1)..................................312
18.5.5 ADC sampling time register 2 (ADC_SPT2)..................................313
18.5.6 ADC preempted channel data offset register x
(ADC_ PCDTOx) (x=1..4)......................................................................315
18.5.7 ADC voltage monitor high threshold register (ADC_VWHB)...........315
18.5.8 ADC voltage monitor low threshold register (ADC_ VWLB)............315
18.5.9 ADC ordinary sequence register 1 (ADC_ OSQ1) .........................315
18.5.10 ADC ordinary sequence register 2 (ADC_ OSQ2) ......................316
18.5.11 ADC ordinary sequence register 3 (ADC_ OSQ3) ......................316
18.5.12 ADC preempted sequence register (ADC_ PSQ)........................316
18.5.13 ADC preempted data register x (ADC_ PDTx) (x=1..4) ...............317
18.5.14 ADC ordinary data register (ADC_ ODT) ...................................317
18.5.15 ADC oversampling register (ADC_ OVSP).................................318

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19 Controller area network (CAN) .................................................... 319
19.1 CAN introduction ....................................................................... 319
19.2 CAN main features..................................................................... 319
19.3 Baud rate .................................................................................. 319
19.4 Interrupt management ................................................................ 322
19.5 Design tips................................................................................ 322
19.6 Functional overview ................................................................... 323
19.6.1 General description ....................................................................323
19.6.2 Operating modes........................................................................323
19.6.3 Test modes ................................................................................324
19.6.4 Message filtering........................................................................324
19.6.5 Message transmission ................................................................327
19.6.6 Message reception .....................................................................328
19.6.7 Error management......................................................................329
19.7 CAN registers............................................................................ 329
19.7.1 CAN control and status registers.................................................330
19.7.1.1 CAN master control register (CAN_MCTRL) ............................ 330
19.7.1.2 CAN master status register (CAN_MSTS)................................ 331
19.7.1.3 CAN transmit status register (CAN_TSTS) .............................. 333
19.7.1.4 CAN receive FIFO 0 register (CAN_RF0) ................................ 335
19.7.1.5 CAN receive FIFO 1 register (CAN_RF1) ................................ 336
19.7.1.6 CAN interrupt enable register (CAN_INTEN) ........................... 336
19.7.1.7 CAN error status register (CAN_ESTS) ................................... 338
19.7.1.8 CAN bit timing register (CAN_BTMG) ..................................... 338
19.7.2 CAN mailbox registers ................................................................339
19.7.2.1 Transmit mailbox identifier register (CAN_TMIx) (x=0..2) ......... 339
19.7.2.2 Transmit mailbox data length and time stamp register
(CAN_TMCx) (x=0..2)......................................................................... 340
19.7.2.3 Transmit mailbox data low register (CAN_TMDTLx) (x=0..2) ..... 340
19.7.2.4 Transmit mailbox data high register (CAN_TMDTHx) (x=0..2) ... 340
19.7.2.5 Receive FIFO mailbox identifier register (CAN_RFIx) (x=0..1) .. 340
19.7.2.6 Receive FIFO mailbox data length and time stamp register
(CAN_RFCx) (x=0..1) ......................................................................... 341
19.7.2.7 Receive FIFO mailbox data low register
(CAN_RFDTLx) (x=0..1) ..................................................................... 341
19.7.2.8 Receive FIFO mailbox data high register (CAN_RFDTHx) (x=0..1)341

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19.7.3 CAN filter registers.....................................................................341
19.7.3.1 CAN filter control register (CAN_FCTRL) ................................ 341
19.7.3.2 CAN filter mode configuration register (CAN_FMCFG) ............. 341
19.7.3.3 CAN filter bit width configuration register (CAN_ FBWCFG)...... 342
19.7.3.4 CAN filter FIFO association register (CAN_ FRF) .................... 342
19.7.3.5 CAN filter activation control register (CAN_ FACFG) ................ 342
19.7.3.6 CAN filter bank i filter bit register (CAN_ FiFBx) (i=0..13; x=1..2)342
20 Universal serial bus full-seed device interface (OTGFS)............. 343
20.1 USBFS structure........................................................................ 343
20.2 OTGFS functional description ..................................................... 343
20.3 OTGFS clock and pin configuration ............................................. 344
20.3.1 OTGFS clock configuration .........................................................344
20.3.2 OTGFS pin configuration ............................................................344
20.4 OTGFS interrupts ...................................................................... 345
20.5 OTGFS functional description ..................................................... 345
20.5.1 OTGFS initialization ...................................................................345
20.5.2 OTGFS FIFO configuration .........................................................346
20.5.2.1 Device mode ........................................................................ 346
20.5.2.2 Host mode............................................................................ 347
20.5.2.3 Refresh controller transmit FIFO ............................................ 348
20.5.3 OTGFS host mode......................................................................348
20.5.3.1 Host initialization .................................................................. 348
20.5.3.2 OTGFS channel initialization.................................................. 349
20.5.3.3 Halting a channel.................................................................. 349
20.5.3.4 Queue depth......................................................................... 349
20.5.3.5 Special cases ....................................................................... 351
20.5.3.6 Host HFIR feature ................................................................. 351
20.5.3.7 Initialize bulk and control IN transfers..................................... 353
20.5.3.8 Initialize bulk and control OUT/SETUP transfers...................... 355
20.5.3.9 Initialize interrupt IN transfers................................................ 357
20.5.3.10 Initialize interrupt OUT transfers ........................................ 359
20.5.3.11 Initialize synchronous IN transfers...................................... 361
20.5.3.12 Initialize synchronous OUT transfers .................................. 362
20.5.4 OTGFS device mode ..................................................................364
20.5.4.1 Device initialization............................................................... 364
20.5.4.2 Endpoint initialization on USB reset........................................ 364

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20.5.4.3 Endpoint initialization on enumeration completion.................... 365
20.5.4.4 Endpoint initialization on SetAddress command....................... 365
20.5.4.5 Endpoint initialization on SetConfiguration/SetInterface command365
20.5.4.6 Endpoint activation ............................................................... 365
20.5.4.7 USB endpoint deactivation..................................................... 366
20.5.4.8 Control write transfers (SETUP/Data OUT/Status IN) ............... 366
20.5.4.9 Control read transfers (SETUP/Data IN/Status OUT)................ 366
20.5.4.10 Control transfers (SETUP/Status IN)................................... 367
20.5.4.11 Read FIFO packets ........................................................... 367
20.5.4.12 OUT data transfers ........................................................... 368
20.5.4.13 IN data transfers............................................................... 370
20.5.4.14 Non-periodic (bulk and control) IN data transfers................. 371
20.5.4.15 Non-synchronous OUT data transfers ................................. 372
20.5.4.16 Synchronous OUT data transfers........................................ 374
20.5.4.17 Enable synchronous endpoints........................................... 375
20.5.4.18 Incomplete synchronous OUT data transfers ....................... 377
20.5.4.19 Incomplete synchronous IN data transfers........................... 378
20.5.4.20 Periodic IN (interrupt and synchronous) data transfers......... 378
20.6 OTGFS control and status registers............................................. 380
20.6.1 CSR register map.......................................................................380
20.6.2 OTGFS register address map......................................................381
20.6.3 OTGFS global registers ..............................................................385
20.6.3.1 OTGFS status and control register (OTGFS_GOTGCTL) .......... 385
20.6.3.2 OTGFS interrupt status control register (OTGFS_GOTGINT) .... 385
20.6.3.3 OTGFS AHB configuration register (OTGFS_GAHBCFG).......... 386
20.6.3.4 OTGFS USB configuration register (OTGFS_GUSBCFG) .......... 386
20.6.3.5 OTGFS reset register (OTGFS_GRSTCTL).............................. 387
20.6.3.6 OTGFS interrupt register (OTGFS_GINTSTS).......................... 389
20.6.3.7 OTGFS interrupt mask register (OTGFS_GINTMSK) ................ 392
20.6.3.8 OTGFS receive status debug read/OTG status read and POP
registers (OTGFS_GRXSTSR / OTGFS_GRXSTSP) .............................. 393
20.6.3.9 OTGFS receive FIFO size register (OTGFS_GRXFSIZ) ............ 394
20.6.3.10 OTGFS non-periodic Tx FIFO size (OTGFS_GNPTXFSIZ)/
Endpoint 0 Tx FIFO size registers (OTGFS_DIEPTXF0) ........................ 394
20.6.3.11 OTGFS non-periodic Tx FIFO size/request queue status register
(OTGFS_GNPTXSTS) ........................................................................ 395
20.6.3.12 OTGFS general controller configuration register
(OTGFS_GCCFG) .............................................................................. 395

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20.6.3.13 OTGFS controller ID register (OTGFS_GUID)...................... 396
20.6.3.14 OTGFS host periodic Tx FIFO size register
(OTGFS_HPTXFSIZ) .......................................................................... 396
20.6.3.15 OTGFS device IN endpoint Tx FIFO size register
(OTGFS_DIEPTXFn) (x=1…7, where n is the FIFO number) .................. 396
20.6.4 Host-mode registers ...................................................................396
20.6.4.1 OTGFS host mode configuration register (OTGFS_HCFG)........ 396
20.6.4.2 OTGFS host frame interval register (OTGFS_HFIR) ................. 397
20.6.4.3 OTGFS host frame number/frame time remaining register
(OTGFS_HFNUM) .............................................................................. 397
20.6.4.4 OTGFS host periodic Tx FIFO/request queue register
(OTGFS_HPTXSTS)........................................................................... 398
20.6.4.5 OTGFS host all channels interrupt register (OTGFS_HAINT) .... 398
20.6.4.6 OTGFS host all channels interrupt mask register
(OTGFS_HAINTMSK) ......................................................................... 398
20.6.4.7 OTGFS host port control and status register (OTGFS_HPRT) ... 399
20.6.4.8 OTGFS host channelx characteristics register
(OTGFS_HCCHARx) (x = 0...15, where x= channel number) .................. 400
20.6.4.9 OTGFS host channelx interrupt register (OTGFS_HCINTx)
(x = 0...15, where x= channel number)................................................. 401
20.6.4.10 OTGFS host channelx interrupt mask register (OTGFS_HCINTMSKx)
(x = 0...15, where x= channel number)................................................. 402
20.6.4.11 OTGFS host channelx transfer size register (OTGFS_HCTSIZx) (x =
0...15, where x= channel number) ....................................................... 402
20.6.5 Device-mode registers................................................................403
20.6.5.1 OTGFS device configure register (OTGFS_DCFG)................... 403
20.6.5.2 OTGFS device control register (OTGFS_DCTL) ....................... 403
20.6.5.3 OTGFS device status register (OTGFS_DSTS) ........................ 405
20.6.5.4 OTGFS device OTGFSIN endpoint common interrupt mask register
(OTGFS_DIEPMSK) ........................................................................... 405
20.6.5.5 OTGFS device OUT endpoint common interrupt mask register
(OTGFS_DOEPMSK).......................................................................... 406
20.6.5.6 OTGFS device all endpoints interrupt mask register (OTGFS_DAINT)
406
20.6.5.7 OTGFS all endpoints interrupt mask register (OTGFS_DAINTMSK)407
20.6.5.8 OTGFS device IN endpoint FIFO empty interrupt mask register
(OTGFS_DIEPEMPMSK) .................................................................... 407
20.6.5.9 OTGFS device control IN endpoint 0 control register
(OTGFS_DIEPCTL0) .......................................................................... 407
20.6.5.10 OTGFS device IN endpoint-x control register (OTGFS_DIEPCTLx)