ARTERY AT32F435 Series User manual

AT32F435/437 Series Reference Manual
2022.11.11 Page 1 Rev 2.03
ARM®-based 32-bit Cortex®-M4F MCU+FPU with 256 to 4032 KB Flash, sLib,
dual QSPI, SDRAM, dual OTGFS, Ethernet, camera, 18 timers, 3 ADCs, 23
communication interfaces
Feature
Core: ARM®32-bit Cortex®-M4F CPU with FPU
−288 MHz maximum frequency, with a Memory
Protection Unit (MPU), single-cycle multiplication
and hardware division
−Floating Point Unit (FPU)
−DSP instructions
Memories
−256 to 4032 KBytes of Flash memory
−sLib: configurable part of main Flash set as a library
area with code executable but secured, non-
readable
−384 to 512 KBytes of SRAM
−External memory controller (XMC) with 16-bit data
bus: supports CF, SRAM, PSRAM, NOR, NAND,
SDRAM memories
−Up to 2 x QSPI interfaces for external SPI Flash or
SPI RAM extension, and memory mapping mode
LCD parallel interface, 8080/6800 modes
Power control (PWC)
−2.6 V ~ 3.6 V application supply
−Power-on reset (POR)/ low-voltage reset (LVR), and
power voltage monitor (PVM)
−Low power: Sleep, Deepsleep, and Standby modes
−VBAT supply for LEXT, ERTC and 20 x 32-bit battery
power register (ERTC_BPR)
Clock and reset management (CRM)
−4 to 25 MHz crystal oscillator (HEXT)
−Internal 48 MHz factory-trimmed clock (HICK),
accuracy 1% at TA=25 °C, 2.5 % at TA=-40 to
+105 °C, with automatic clock calibration (ACC)
−PLL with configurable frequency multiplication and
division factor
−32.768 kHz crystal oscillator (LEXT)
−Internal 40 kHz RC oscillator (LICK)
Analog
−3 x 12-bit 5.33 MSPS A/D converters, up to 24 input
channels, 12-bit/10-bit/8-bit/6-bit configurable
resolution
−Temperature sensor (VTS), internal reference
voltage (VINTR), VBAT battery voltage monitor
(VBAT/4)
−2 x 12-bit D/A converters
DMA:
−2 x general-purpose DMAs and 1 x EDMA
−22 channels in all
Up to 116 Fast I/O Interfaces
−All mappable to 16 external interrupt vectors
−Almost 5 V-tolerant
Up to 18 Timers (TMR)
−Up to 13 x 16-bit timers + 2 x 32-bit timers, each with 4
IC/OC/PWMor pulse counter channels
−2 x Watchdog timers (WDTand WWDT)
−SysTick timer: 24-bit downcounter
ERTC: enhanced RTC with auto wakeup, alarm,
subsecond precision, hardware calendar and
calibration feature
Up to 23 communication interfaces
−Up to 3 x I2C interfaces (SMBus/PMBus)
−Up to 4 x USARTs/4 x UARTs (ISO7816 interface, LIN,
IrDA capability, modem control and RS485 drive enable,
with interchangeable TX/RX)
−Up to 4 x SPIs (36 Mbit/s),all with I2Sinterface
multiplexed, I2S2/ I2S3 support full-duplex
−Up to 2 x CANinterfaces (2.0B Active)
−Up to 2 x OTG FS controllers supporting crystal-less
−Up to 2 x SDIO interfaces
−Infrared transmitter (IRTMR)
−10/100M Ethernet MAC with dedicated DMA and
SRAM(4 Kbytes): IEEE1588 hardware support, MII/RMII
available (For AT32F437 only)
8~14 bit parallel digital camera interface (DVP)
CRC Calculation Unit
96-bit ID (UID)
Debug mode
−SWD andJTAGinterfaces
Temperature range: -40 to 105℃
Packaging
−LQFP144 20 x 20 mm LQFP100 14 x 14 mm
−LQFP64 10 x 10 mm LQFP48 7 x 7mm
−QFN48 6 x 6mm
List of Models
Internal Flash
Model
4032 KBytes
AT32F435ZMT7, AT32F435VMT7
AT32F435RMT7, AT32F435CMT7
AT32F435CMU7, AT32F437ZMT7,
AT32F437VMT7 AT32F437RMT7
1024 KBytes
AT32F435ZGT7, AT32F435VGT7,
AT32F435RGT7 AT32F435CGT7,
AT32F435CGU7, AT32F437ZGT7
AT32F437VGT7, AT32F437RGT7
256 KBytes
AT32F435ZCT7 AT32F435VCT7
AT32F435RCT7 AT32F435CCT7
AT32F435CCU7 AT32F437ZCT7
AT32F437VCT7 AT32F437RCT7

AT32F435/437 Series Reference Manual
2022.11.11 Page 2 Rev 2.03
Contents
1System architecture...................................................................... 43
1.1 System overview..........................................................................45
1.1.1 ARM CortexTM-M4F processor...................................................... 45
1.1.2 BusMatrix ................................................................................... 45
1.1.3 Bit band...................................................................................... 47
1.1.4 Interrupt and exception vectors .................................................... 49
1.1.5 System Tick (SysTick) ................................................................. 52
1.1.6 Reset ......................................................................................... 53
1.2 List of abbreviations for registers ..................................................55
1.3 Device characteristics information.................................................55
1.3.1 Flash memory size register .......................................................... 55
1.3.2 Device electronic signature.......................................................... 55
2Memory resources ........................................................................ 56
2.1 Internal memory address map.......................................................56
2.2 Flash memory..............................................................................56
2.3 SRAM memory.............................................................................59
2.4 Peripheral address map................................................................59
3Power control (PWC)..................................................................... 62
3.1 Introduction .................................................................................62
3.2 Main Features .............................................................................62
3.3 POR/LVR ....................................................................................62
3.4 Power voltage monitor (PVM)........................................................63
3.5 Power domain..............................................................................63
3.6 Power saving modes ....................................................................64
3.7 PWC registers .............................................................................66
3.7.1 Power control register (PWC_CTRL) ............................................ 67
3.7.2 Power control/status register (PWC_CTRLSTS) ............................ 67
3.7.3 LDO output voltage select register (PWC_LDOOV)........................ 68
4Clock and reset manage (CRM) ..................................................... 69

AT32F435/437 Series Reference Manual
2022.11.11 Page 3 Rev 2.03
4.1 Clock ..........................................................................................69
4.1.1 Clock sources ............................................................................. 69
4.1.2 System clock............................................................................... 70
4.1.3 Peripheral clock .......................................................................... 70
4.1.4 Clock fail detector ....................................................................... 71
4.1.5 Auto step-by-step system clock switch.......................................... 71
4.1.6 Clock output................................................................................ 71
4.1.7 Interrupts.................................................................................... 71
4.2 Reset..........................................................................................71
4.2.1 System reset............................................................................... 71
4.2.2 Battery powered domain reset...................................................... 72
4.3 CRM registers .............................................................................72
4.3.1 Clock control register (CRM_CTRL).............................................. 73
4.3.2 PLL clock configuration register (CRM_PLLCFG) .......................... 74
4.3.3 Clock configuration register (CRM_CFG) ...................................... 75
4.3.4 Clock interrupt register (CRM_CLKINT) ........................................ 77
4.3.5 APB peripheral reset register1 (CRM_APBRST1) .......................... 78
4.3.6 APB peripheral reset register2 (CRM_APBRST2) .......................... 79
4.3.7 APB peripheral reset register3 (CRM_APBRST3) .......................... 79
4.3.8 APB1 peripheral reset register (CRM_APB1RST) .......................... 79
4.3.9 APB2 peripheral reset register (CRM_APB2RST) .......................... 81
4.3.10 APB peripheral clock enable register1 (CRM_AHBEN1) ................. 82
4.3.11 APB peripheral clock enable register2 (CRM_AHBEN2) ................. 83
4.3.12 APB1 peripheral clock enable register3 (CRM_AHBEN3) ............... 83
4.3.13 APB1 peripheral clock enable register (CRM_AHB1EN)................. 83
4.3.14 APB2 peripheral clock enable register (CRM_AHB2EN) ................. 85
4.3.15 APB peripheral clock enable in low power mode register1
(CRM_AHBLPEN1)................................................................................ 86
4.3.16 APB peripheral clock enable in low power mode register2
(CRM_AHBLPEN2)................................................................................ 87
4.3.17 APB peripheral clock enable in low power mode register3
(CRM_AHBLPEN3)................................................................................ 88
4.3.18 APB1 peripheral clock enable in low power mode register
(CRM_AHB1LPEN)................................................................................ 88

AT32F435/437 Series Reference Manual
2022.11.11 Page 4 Rev 2.03
4.3.19 APB2 peripheral clock enable in low power mode register
(CRM_AHB2LPEN)................................................................................ 89
4.3.20 Battery powered domain control register (CRM_BPDC).................. 90
4.3.21 Control/status register (CRM_CTRLSTS) ...................................... 91
4.3.22 Additional register1 (CRM_MISC1) ............................................... 92
4.3.23 Additional register2 (CRM_MISC2) ............................................... 93
5Flash memory controller (FLASH)................................................. 94
5.1 FLASH introduction......................................................................94
5.2 Flash memory operation ...............................................................99
5.2.1 Unlock/lock ................................................................................. 99
5.2.2 Erase operation........................................................................... 99
5.2.3 Programming operation...............................................................102
5.2.4 Read operation ..........................................................................103
5.3 User system data area operation................................................. 103
5.3.1 Unlock/lock ................................................................................103
5.3.2 Erase operation..........................................................................104
5.3.3 Programming operation...............................................................105
5.3.4 Read operation ..........................................................................106
5.4 Flash memory protection ............................................................ 106
5.4.1 Access protection.......................................................................106
5.4.2 Erase/program protection............................................................106
5.5 Special functions ....................................................................... 106
5.5.1 Security library settings ..............................................................106
5.6 Flash memory registers .............................................................. 107
5.6.1 Flash performance select register (FLASH_PSR) .........................108
5.6.2 Flash unlock register (FLASH_UNLOCK) .....................................109
5.6.3 Flash user system data unlock register (FLASH_USD_UNLOCK) ..109
5.6.4 Flash status register (FLASH_STS) .............................................109
5.6.5 Flash control register (FLASH_CTRL)..........................................109
5.6.6 Flash address register (FLASH_ADDR) .......................................110
5.6.7 User system data register (FLASH_USD).....................................110
5.6.8 Erase/program protection status register0 (FLASH_EPPS0)..........111
5.6.9 Erase/program protection status register1 (FLASH_EPPS1)..........111
5.6.10 Flash unlock register2 (FLASH_UNLOCK2)..................................111

AT32F435/437 Series Reference Manual
2022.11.11 Page 5 Rev 2.03
5.6.11 Flash status register2 (FLASH_STS2) .........................................111
5.6.12 Flash control register2 (FLASH_CTRL2) ......................................111
5.6.13 Flash address register2 (FLASH_ADDR2)....................................112
5.6.14 Flash continue read register (FLASH_CONTR).............................112
5.6.15 Flash divider register (FLASH_DIVR) ..........................................112
5.6.16 Flash security library status register2 (SLIB_STS2)......................113
5.6.17 Flash security library status register0 (SLIB_STS0)......................113
5.6.18 Flash security library status register1 (SLIB_STS1)......................113
5.6.19 Flash security library password clear register (SLIB_PWD_CLR)...113
5.6.20 Security library additional status register (SLIB_MISC_STS).........113
5.6.21 Security library password setting register (SLIB_SET_PWD).........114
5.6.22 Security library address setting register0 (SLIB_SET_RANGE0) ...114
5.6.23 Security library address setting register1 (SLIB_SET_RANGE1) ...114
5.6.24 Security library unlock register (SLIB_UNLOCK) ..........................115
5.6.25 Flash CRC calibration control register (FLASH_CRC_CTRL).........115
5.6.26 Flash CRC check result register (FLASH_CRC_CHKR).................115
6GPIOs and IOMUX ....................................................................... 116
6.1 Introduction ............................................................................... 116
6.2 Function overview...................................................................... 116
6.2.1 GPIO structure...........................................................................116
6.2.2 GPIO reset status.......................................................................116
6.2.3 General-purpose input configuration............................................117
6.2.4 Analog input/output configuration ................................................117
6.2.5 General-purpose output configuration..........................................117
6.2.6 I/O port protection ......................................................................117
6.2.7 IOMUX structure ........................................................................118
6.2.8 Multiplexed function pull-up/down configuration ...........................118
6.2.9 IOMUX input/output ....................................................................119
6.2.10 Peripheral MUX function configuration.........................................133
6.2.11 IOMUX map priority ....................................................................133
6.2.12 External interrupt/wake-up lines ..................................................134
6.3 GPIO registers........................................................................... 134
6.3.1 GPIO configuration register (GPIOx_CFGR) (x=A..H) ...................134
6.3.2 GPIO output mode register (GPIOx_OMODE) (x=A..H) .................134

AT32F435/437 Series Reference Manual
2022.11.11 Page 6 Rev 2.03
6.3.3 GPIO drive capability register (GPIOx_ODRVR) (x=A..H)..............135
6.3.4 GPIO pull-up/pull-down register (GPIOx_PULL) (x=A..H) ..............135
6.3.5 GPIO input register (GPIOx_IDH) (x=A..H)...................................135
6.3.6 GPIO output register (GPIOx_IDH) (x=A..H).................................135
6.3.7 GPIO set/clear register (GPIOx_SCR) (x=A..H) ............................135
6.3.8 GPIO write protection register (GPIOx_WPR) (x=A..H) .................136
6.3.9 GPIO multiplexed function low register (GPIOx_MUXL) (x=A..H) ...136
6.3.10 GPIO multiplexed function high register (GPIOx_MUXH) (x=A..H) .137
6.3.11 GPIO port bit clear register (GPIOx_CLR) (x=A..H) ......................137
6.3.12 GPIO huge current control register (GPIOx_HDRV) (x=A..E).........137
7System configuration controller (SCFG) ..................................... 138
7.1 Introduction ............................................................................... 138
7.2 IOMUX registers ........................................................................ 138
7.2.1 SCFG configuration register1 (SCFG_CFG1) ...............................138
7.2.2 SCFG configuration register2 (SCFG_CFG2) ...............................139
7.2.3 SCFG external interrupt configuration register1 (SCFG_ EXINTC1)139
7.2.4 SCFG external interrupt configuration register2 (SCFG_ EXINTC2)140
7.2.5 SCFG external interrupt configuration register3 (SCFG_ EXINTC3)141
7.2.6 SCFG external interrupt configuration register4 (SCFG_ EXINTC4)142
7.2.7 SCFG ultra high sourcing/sinking strength (SCFG_UHDRV)..........144
8External interrupt/Event controller (EXINT) ................................ 146
8.1 EXINT introduction..................................................................... 146
8.2 Function overview and configuration procedure ............................ 146
8.3 EXINT registers ......................................................................... 147
8.3.1 Interrupt enable register (EXINT_INTEN).....................................147
8.3.2 Event enable register (EXINT_EVTEN) ........................................147
8.3.3 Polarity configuration register1 (EXINT_ POLCFG1).....................147
8.3.4 Polarity configuration register2 (EXINT_ POLCFG2).....................148
8.3.5 Software trigger register (EXINT_ SWTRG)..................................148
8.3.6 Interrupt status register (EXINT_ INTSTS) ...................................148
9DMA controller (DMA) ................................................................. 149
9.1 Introduction ............................................................................... 149

AT32F435/437 Series Reference Manual
2022.11.11 Page 7 Rev 2.03
9.2 Main features ............................................................................ 149
9.3 Function overview...................................................................... 150
9.3.1 DMA configuration......................................................................150
9.3.2 Handshake mechanism ...............................................................150
9.3.3 Arbiter .......................................................................................151
9.3.4 Programmable data transfer width ...............................................151
9.3.5 Errors ........................................................................................152
9.3.6 Interrupts...................................................................................152
9.4 DMA multiplexer (DMAMUX) ....................................................... 152
9.4.1 DMAMUX functional overview .....................................................153
9.4.2 DMAMUX overflow interrupts ......................................................155
9.5 DMA registers............................................................................ 156
9.5.1 DMA interrupt status register (DMA_STS) ....................................157
9.5.2 DMA interrupt flag clear register (DMA_CLR)...............................159
9.5.3 DMA channel-x configuration register (DMA_CxCTRL) (x = 1…7) ..161
9.5.4 DMA channel-x number of data register (DMA_CxDTCNT) (x = 1…7)162
9.5.5 DMA channel-x peripheral address register (DMA_CxPADDR)
(x = 1…7) ............................................................................................162
9.5.6 DMA channel-x memory address register (DMA_CxMADDR) (x = 1…7)162
9.5.7 DMAMUX selection register (DMA_MUXSEL) ...............................162
9.5.8 DMAMUX channel-x control register (DMA_MUXCxCTRL) (x = 1…7)162
9.5.9 DMAMUX generator x control register (DMA_MUXGxCTRL) (x = 1…4) 163
9.5.10 DMAMUX channel synchronization status register
(DMA_MUXSYNCSTS) .........................................................................164
9.5.11 DMAMUX channel interrupt clear flag register (DMA_MUXSYNCCLR)164
9.5.12 DMAMUX generator interrupt status register (DMA_MUXGSTS) ....164
9.5.13 DMAMUX generator interrupt flga clear register (DMA_MUXGCLR)165
10 CRC calculation unit (CRC)......................................................... 166
10.1 CRC introduction ....................................................................... 166
10.2 CRC registers............................................................................ 166
10.2.1 Data register (CRC_DT)..............................................................166
10.2.2 Common data register (CRC_CDT)..............................................166
10.2.3 Control register (CRC_CTRL)......................................................166
10.2.4 Initialization register (CRC_IDT) .................................................167

AT32F435/437 Series Reference Manual
2022.11.11 Page 8 Rev 2.03
11 I2C interface ................................................................................ 168
11.1 I2C introduction.......................................................................... 168
11.2 I2C main features....................................................................... 168
11.3 I2C function overview ................................................................. 168
11.4 I2C interface .............................................................................. 169
11.4.1 I2C timing control .......................................................................171
11.4.2 Data transfer management..........................................................172
11.4.3 I2C master communication flow ...................................................173
11.4.4 I2C slave communication flow......................................................178
11.4.5 SMBus.......................................................................................182
11.4.6 SMBus master communication flow..............................................184
11.4.7 SMBus slave communication flow................................................188
11.4.8 Data transfer using DMA.............................................................192
11.4.9 Error management......................................................................192
11.5 I2C interrupt requests ................................................................. 194
11.6 I2C debug mode......................................................................... 194
11.7 I2C registers .............................................................................. 194
11.7.1 Control register1 (I2C_CTRL1)....................................................195
11.7.2 Control register2 (I2C_CTRL2)....................................................196
11.7.3 Address register1 (I2C_OADDR1) ...............................................197
11.7.4 Own address register2 (I2C_OADDR2) ........................................197
11.7.5 Timing register (I2C_CLKCTRL)..................................................197
11.7.6 Timeout register (I2C_TIMEOUT) ................................................197
11.7.7 Status register (I2C_STS)...........................................................198
11.7.8 Status clear register (I2C_CLR) ..................................................199
11.7.9 PEC register (I2C_PEC) .............................................................200
11.7.10 Receive data register (I2C_RXDT)............................................200
11.7.11 Transmit data register (I2C_TXDT) ...........................................200
12 Universal synchronous/asynchronous receiver/transmitter
(USART).............................................................................. 201
12.1 USART introduction ................................................................... 201
12.2 Full-duplex/half-duplex selector .................................................. 203
12.3 Mode selector............................................................................ 203

AT32F435/437 Series Reference Manual
2022.11.11 Page 9 Rev 2.03
12.3.1 Introduction................................................................................203
12.3.2 Configuration procedure .............................................................203
12.4 USART frame format and configuration........................................ 206
12.5 DMA transfer introduction........................................................... 208
12.5.1 Transmission using DMA ............................................................208
12.5.2 Reception using DMA .................................................................208
12.6 Baud rate generation.................................................................. 209
12.6.1 Introduction................................................................................209
12.6.2 Configuration .............................................................................209
12.7 Transmitter................................................................................ 210
12.7.1 Transmitter introduction..............................................................210
12.7.2 Transmitter configuration ............................................................210
12.8 Receiver ................................................................................... 211
12.8.1 Receiver introduction..................................................................211
12.8.2Receiver configuration................................................................211
12.8.3 Start bit and noise detection .......................................................212
12.9 Tx/Rx swap ............................................................................... 213
12.10Interrupt requests ...................................................................... 214
12.11I/O pin control............................................................................ 215
12.12USART registers........................................................................ 215
12.12.1 Status register (USART_STS) ..................................................215
12.12.2 Data register (USART_DT).......................................................216
12.12.3 Baud rate register (USART_BAUDR) ........................................217
12.12.4 Control register1 (USART_CTRL1) ...........................................217
12.12.5 Control register2 (USART_CTRL2) ...........................................218
12.12.6 Control register3 (USART_CTRL3) ...........................................219
12.12.7 Guard time and divider register (USART_GDIV) ........................220
13 Serial peripheral interface (SPI).................................................. 221
13.1 SPI introduction ......................................................................... 221
13.2 Function overview...................................................................... 221
13.2.1 SPI description...........................................................................221
13.2.2 Full-duplex/half-duplex selector ..................................................222
13.2.3 Chip select controller..................................................................224

AT32F435/437 Series Reference Manual
2022.11.11 Page 10 Rev 2.03
13.2.4 SPI_SCK controller ....................................................................225
13.2.5 CRC ..........................................................................................225
13.2.6 DMA transfer..............................................................................226
13.2.7 TI mode .....................................................................................226
13.2.8 Transmitter ................................................................................227
13.2.9 Receiver ....................................................................................227
13.2.10 Motorola mode ........................................................................228
13.2.11 TI mode ..................................................................................230
13.2.12 Interrupts ................................................................................231
13.2.13 IO pin control ..........................................................................231
13.2.14 Precautions.............................................................................232
13.3 I2S functional description............................................................ 232
13.3.1 I2S introduction ..........................................................................232
13.3.2 I2S full-duplex ............................................................................233
13.3.3 Operating mode selector.............................................................233
13.3.4 Audio protocol selector ...............................................................235
13.3.5 I2S_CLK controller .....................................................................236
13.3.6 DMA transfer..............................................................................238
13.3.7 Transmitter/Receiver ..................................................................238
13.3.8 I2S communication timings .........................................................239
13.3.9 Interrupts...................................................................................240
13.3.10 IO pin control ..........................................................................240
13.4 SPI registers ............................................................................. 241
13.4.1 SPI control register1 (SPI_CTRL1) (Not used in I2S mode) ...........241
13.4.2 SPI control register2 (SPI_CTRL2) ..............................................242
13.4.3 SPI status register (SPI_STS).....................................................243
13.4.4 SPI data register (SPI_DT) .........................................................244
13.4.5 SPICRC register (SPI_CPOLY) (Not used in I2S mode).................244
13.4.6 SPIRxCRC register (SPI_RCRC) (Not used in I2S mode) ..............244
13.4.7 SPITxCRC register (SPI_TCRC)..................................................244
13.4.8 SPI_I2S register (SPI_I2SCTRL) .................................................244
13.4.9 SPI_I2S prescaler register (SPI_I2SCLKP) ..................................245
14 Timer .......................................................................................... 246
14.1 Basic timer (TMR6 and TMR7) .................................................... 247

AT32F435/437 Series Reference Manual
2022.11.11 Page 11 Rev 2.03
14.1.1 TMR6 and TMR7 introduction......................................................247
14.1.2 TMR6 and TMR7 main features ...................................................247
14.1.3 TMR6 and TMR7 function overview .............................................247
14.1.3.1 Count clock .......................................................................... 247
14.1.3.2 Counting mode ..................................................................... 247
14.1.3.3 Debug mode ......................................................................... 249
14.1.4 TMR6 and TMR7 registers ..........................................................249
14.1.4.1 TMR6 and TMR7 control register1 (TMRx_CTRL1)................... 250
14.1.4.2 TMR6 and TMR7 control register2 (TMRx_CTRL2)................... 250
14.1.4.3 TMR6 and TMR7 DMA/interrupt enable register (TMRx_IDEN) .. 250
14.1.4.4 TMR6 and TMR7 interrupt status register (TMRx_ISTS) ........... 251
14.1.4.5 TMR6 and TMR7 software event register (TMRx_SWEVT) ........ 251
14.1.4.6 TMR6 and TMR7 counter value (TMRx_CVAL) ........................ 251
14.1.4.7 TMR6 and TMR7 division (TMRx_DIV) .................................... 251
14.1.4.8 TMR6 and TMR7 period register (TMRx_PR) ........................... 251
14.2 General-purpose timer (TMR2 to TMR5) ...................................... 252
14.2.1 TMR2 to TMR5 introduction ........................................................252
14.2.2 TMR2 to TMR5 main features......................................................252
14.2.3 TMR2 to TMR5 functional overview .............................................252
14.2.3.1 Count clock .......................................................................... 252
14.2.3.2 Counting mode ..................................................................... 256
14.2.3.3 TMR input function................................................................ 259
14.2.3.4 TMR output function.............................................................. 261
14.2.3.5 TMR synchronization............................................................. 264
14.2.3.6 Debug mode ......................................................................... 267
14.2.4 TMRx registers...........................................................................267
14.2.4.1 TMR2 to TMR5 control register1 (TMRx_CTRL1) ..................... 268
14.2.4.2 TMR2 to TMR5 control register2 (TMRx_CTRL2) ..................... 269
14.2.4.3 TMR2 to TMR5 slave timer control register (TMRx_STCTRL) .... 269
14.2.4.4 TMR2 to TMR5 DMA/interrupt enable register (TMRx_IDEN) .... 270
14.2.4.5 TMR2 to TMR5 interrupt status register (TMRx_ISTS).............. 271
14.2.4.6 TMR2 to TMR5 software event register (TMRx_SWEVT) .......... 272
14.2.4.7 TMR2 to TMR5 channel mode register1 (TMRx_CM1) .............. 272
14.2.4.8 TMR2 to TMR5 channel mode register2 (TMRx_CM2) .............. 274
14.2.4.9 TMR2 to TMR5 channel control register (TMRx_CCTRL) .......... 275
14.2.4.10 TMR2 to TMR5 counter value (TMRx_CVAL) ....................... 275
14.2.4.11 TMR2 to TMR5 division value (TMRx_DIV).......................... 276

AT32F435/437 Series Reference Manual
2022.11.11 Page 12 Rev 2.03
14.2.4.12 TMR2 to TMR5 period register (TMRx_PR) ......................... 276
14.2.4.13 TMR2 to TMR5 channel 1 data register (TMRx_C1DT) ......... 276
14.2.4.14 TMR2 to TMR5 channel 2 data register (TMRx_C2DT) ......... 276
14.2.4.15 TMR2 to TMR5 channel 3 data register (TMRx_C3DT) ......... 276
14.2.4.16 TMR2 to TMR5 channel 4 data register (TMRx_C4DT) ......... 277
14.2.4.17 TMR2 to TMR5 DMA control register (TMRx_DMACTRL) ...... 277
14.2.4.18 TMR2 to TMR5 DMA data register (TMRx_DMADT).............. 277
14.2.4.19 TMR5 channel input remapping register (TMR2_RMP) ......... 277
14.2.4.20 TMR2 channel input remapping register (TMR5_RMP) ......... 277
14.3 General-purpose timer (TMR9 to TMR14) .................................... 278
14.3.1 TMR9 to TMR14 introduction.......................................................278
14.3.2 TMR9 to TMR14 main features....................................................278
14.3.2.1 TMR9 and TMR12 main features ............................................ 278
14.3.2.2 TMR10, TMR11, TMR13 and TMR14 main features .................. 278
14.3.3 TMR9 to TMR14 functional overview ...........................................279
14.3.3.1 Count clock .......................................................................... 279
14.3.3.2 Counting mode ..................................................................... 282
14.3.3.3 TMR input function................................................................ 283
14.3.3.4 TMR output function.............................................................. 286
14.3.3.5 TMR synchronization............................................................. 288
14.3.3.6 Debug mode ......................................................................... 289
14.3.4 TMR9 and TMR12 registers ........................................................289
14.3.4.1 TMR9 and TMR12 control register1 (TMRx_CTRL1) ................. 289
14.3.4.2 TMR9 and TMR12 Slave timer control register (TMRx_STCTRL) 290
14.3.4.3 TMR9 and TMR12 DMA/interrupt enable register (TMRx_IDEN) 290
14.3.4.4 TMR9 and TMR12 interrupt status register (TMRx_ISTS) ......... 291
14.3.4.5 TMR9 and TMR12 software event register (TMRx_SWEVT) ...... 291
14.3.4.6 TMR9 and TMR12 channel mode register1 (TMRx_CM1) .......... 292
14.3.4.7 TMR9 and TMR12 channel control register (TMRx_CCTRL)...... 294
14.3.4.8 TMR9 and TMR12 counter value (TMRx_CVAL)....................... 294
14.3.4.9 TMR9 and TMR12 division value (TMRx_DIV) ......................... 294
14.3.4.10 TMR9 and TMR12 period register (TMRx_PR) ..................... 294
14.3.4.11 TMR9 and TMR12 channel 1 data register (TMRx_C1DT) ..... 294
14.3.4.12 TMR9 and TMR12 channel 2 data register (TMRx_C2DT) ..... 295
14.3.5 TMR10,TMR11, TMR13 and TMR14 registers...............................295
14.3.5.1 TMR10, TMR11, TMR13 and TMR14 control register1 (TMRx_CTRL1)
295
14.3.5.2 TMR10, TMR11, TMR13 and TMR14 DMA/interrupt enable register

AT32F435/437 Series Reference Manual
2022.11.11 Page 13 Rev 2.03
(TMRx_IDEN) .................................................................................... 296
14.3.5.3 TMR10, TMR11, TMR13 and TMR14 interrupt status register
(TMRx_ISTS) .................................................................................... 296
14.3.5.4 TMR10, TMR11, TMR13 and TMR14 software event register
(TMRx_SWEVT)................................................................................. 296
14.3.5.5 TMR10, TMR11, TMR13 and TMR14 channel mode register1
(TMRx_CM1) ..................................................................................... 297
14.3.5.6 TMR10, TMR11, TMR13 and TMR14 channel control register
(TMRx_CCTRL) ................................................................................. 298
14.3.5.7 TMR10, TMR11, TMR13 and TMR14 counter value (TMRx_CVAL)299
14.3.5.8 TMR10, TMR11, TMR13 and TMR14 division value (TMRx_DIV) 299
14.3.5.9 TMR10, TMR11, TMR13 and TMR14 period register (TMRx_PR)299
14.3.5.10 TMR10, TMR11, TMR13 and TMR14 channel 1 data register
(TMRx_C1DT) ................................................................................... 299
14.4 Advanced-control timers (TMR1,TMR8 and TMR20)...................... 300
14.4.1 TMR1,TMR8 and TMR20 introduction ..........................................300
14.4.2 TMR1,TMR8 and TMR20 main features .......................................300
14.4.3 TMR1 and TMR8 functional overview...........................................300
14.4.3.1 Count clock .......................................................................... 300
14.4.3.2 Counting mode ..................................................................... 304
14.4.3.3 TMR input function................................................................ 308
14.4.3.4 TMR output function.............................................................. 310
14.4.3.5 TMR brake function............................................................... 314
14.4.3.6 TMR synchronization............................................................. 316
14.4.3.7 Debug mode ......................................................................... 317
14.4.4 TMR1, TMR8 and TM20 registers ................................................318
14.4.4.1 TMR1, TMR8 and TMR20 control register1 (TMRx_CTRL1) ...... 318
14.4.4.2 TMR1, TMR8 and TMR20 control register2 (TMRx_CTRL2) ...... 319
14.4.4.3 TMR1, TMR8 and TMR20 slave timer control register
(TMRx_STCTRL) ............................................................................... 320
14.4.4.4 TMR1, TMR8 and TMR20 DMA/interrupt enable register
(TMRx_IDEN) .................................................................................... 321
14.4.4.5 TMR1, TMR8 and TMR20 interrupt status register (TMRx_ISTS)322
14.4.4.6 TMR1, TMR8 and TMR20 software event register (TMRx_SWEVT)323
14.4.4.7 TMR1, TMR8 and TMR20 channel mode register1 (TMRx_CM1) 323
14.4.4.8 TMR1, TMR8 and TMR20 channel mode register2 (TMRx_CM2) 325
14.4.4.9 TMR1, TMR8 and TMR20 Channel control register (TMRx_CCTRL)326
14.4.4.10 TMR1, TMR8 and TMR20 counter value (TMRx_CVAL) ........ 328
14.4.4.11 TMR1, TMR8 and TMR20 division value (TMRx_DIV) ........... 328

AT32F435/437 Series Reference Manual
2022.11.11 Page 14 Rev 2.03
14.4.4.12 TMR1, TMR8 and TMR20 period register (TMRx_PR)........... 328
14.4.4.13 TMR1, TMR8 and TMR20 repetition period register (TMRx_RPR)328
14.4.4.14 TMR1, TMR8 and TMR20 channel 1 data register (TMRx_C1DT)328
14.4.4.15 TMR1, TMR8 and TMR20 channel 2 data register (TMRx_C2DT)329
14.4.4.16 TMR1, TMR8 and TMR20 channel 3 data register (TMRx_C3DT)329
14.4.4.17 TMR1, TMR8 and TMR20 channel 4 data register (TMRx_C4DT)329
14.4.4.18 TMR1, TMR8 and TMR20 brake register (TMRx_BRK).......... 329
14.4.4.19 TMR1, TMR8 and TMR20 DMA control register
(TMRx_DMACTRL) ............................................................................ 330
14.4.4.20 TMR1, TMR8 and TMR20 DMA data register (TMRx_DMADT)331
14.4.4.21 TMR1, TMR8 and TMR20 channel mode register3 (TMRx_ CM3)331
14.4.4.22 TMR1, TMR8 and TMR20 channel 5 data register (TMRx_C5DT)331
15 Window watchdog timer (WWDT) ................................................ 332
15.1 WWDT introduction .................................................................... 332
15.2 WWDT main features ................................................................. 332
15.3 WWDT functional overview ......................................................... 332
15.4 Debug mode.............................................................................. 333
15.5 WWDT registers ........................................................................ 333
15.5.1 Control register (WWDT_CTRL) ..................................................333
15.5.2 Configuration register (WWDT_CFG)...........................................333
15.5.3 Status register (WWDT_STS)......................................................334
16 Watchdog timer (WDT) ................................................................ 335
16.1 WDT introduction ....................................................................... 335
16.2 WDT main features .................................................................... 335
16.3 WDT functional overview ............................................................ 335
16.4 Debug mode.............................................................................. 336
16.5 WDT registers ........................................................................... 336
16.5.1 Command register (WDT_CMD) ..................................................337
16.5.2 Divider register (WDT_DIV).........................................................337
16.5.3 Reload register (WDT_RLD)........................................................337
16.5.4 Status register (WDT_STS).........................................................337
16.5.5 Window register (WDT_WIN).......................................................337
17 Enhanced real-time clock (ERTC) ............................................... 338

AT32F435/437 Series Reference Manual
2022.11.11 Page 15 Rev 2.03
17.1 ERTC introduction...................................................................... 338
17.2 ERTC main features................................................................... 338
17.3 ERTC function overview ............................................................. 339
17.3.1ERTC clock................................................................................339
17.3.2 ERTC initialization......................................................................339
17.3.3 Periodic automatic wakeup .........................................................341
17.3.4 ERTC calibration ........................................................................342
17.3.5 Reference clock detection...........................................................343
17.3.6 Time stamp function ...................................................................343
17.3.7 Tamper detection .......................................................................343
17.3.8 Multiplexed function output .........................................................344
17.3.9 ERTC wakeup ............................................................................344
17.4 ERTC registers.......................................................................... 345
17.4.1 ERTC time register (ERTC_TIME) ...............................................346
17.4.2 ERTC date register (ERTC_DATE) ..............................................346
17.4.3 ERTC control register (ERTC_CTRL)...........................................346
17.4.4 ERTC initialization and status register (ERTC_STS).....................348
17.4.5 ERTC divider register (ERTC_DIV)..............................................349
17.4.6 ERTC wakeup timer register (ERTC_WAT) ..................................349
17.4.7 ERTC coarse calibration register (ERTC_CCAL) ..........................349
17.4.8 ERTC alarm clock A register (ERTC_ALA) ...................................350
17.4.9 ERTC alarm clock B register (ERTC_ALB) ...................................350
17.4.10 ERTC write protection register (ERTC_WP) ..............................351
17.4.11 ERTC subsecond register (ERTC_SBS) ....................................351
17.4.12 ERTC time adjustment register (ERTC_TADJ) ...........................351
17.4.13 ERTC time stamp time register (ERTC_TSTM) ..........................351
17.4.14 ERTC time stamp date register (ERTC_TSDT) ..........................352
17.4.15 ERTC time stamp subsecond register (ERTC_TSSBS)...............352
17.4.16 ERTC smooth calibration register (ERTC_SCAL) .......................352
17.4.17 ERTC tamper configuration register (ERTC_TAMP) ...................352
17.4.18 ERTC alarm clock A subsecond register (ERTC_ALASBS) .........354
17.4.19 ERTC alarm clock B subsecond register (ERTC_ALBSBS) .........354
17.4.20 ERTC battery powered domain data register (ERTC_BPRx) .......354
18 Analog-to-digital converter (ADC)............................................... 355

AT32F435/437 Series Reference Manual
2022.11.11 Page 16 Rev 2.03
18.1 ADC introduction ....................................................................... 355
18.2 ADC main features..................................................................... 355
18.3 ADC structure............................................................................ 355
18.4 ADC functional overview............................................................. 356
18.4.1 Channel management.................................................................356
18.4.1.1 Internal temperature sensor ................................................... 357
18.4.1.2 Internal reference voltage...................................................... 357
18.4.1.3 Battery voltage ..................................................................... 357
18.4.2 ADC operation process...............................................................357
18.4.2.1 Power-on and calibration ....................................................... 358
18.4.2.2 Trigger................................................................................. 359
18.4.2.3 Sampling and conversion sequence........................................ 360
18.4.3 Conversion sequence management .............................................360
18.4.3.1 Sequence mode .................................................................... 360
18.4.3.2 Automatic preempted group conversion mode ......................... 361
18.4.3.3 Repetition mode.................................................................... 361
18.4.3.4 Partition mode ...................................................................... 362
18.4.4 End of conversion ......................................................................362
18.4.5 Oversampling.............................................................................363
18.4.5.1 Oversampling of ordinary group of channels............................ 364
18.4.5.2 Oversampling of preempted group of channels ........................ 365
18.4.6 Data management ......................................................................365
18.4.6.1 Data alignment ..................................................................... 365
18.4.6.2 Data read ............................................................................. 366
18.4.7 Voltage monitoring .....................................................................366
18.4.7.1 Status flag and interrupts ...................................................... 367
18.5 Master/Slave mode .................................................................... 367
18.5.1 Data management ......................................................................368
18.5.2 Simultaneous mode ....................................................................368
18.5.3 Alternate preempted trigger mode ...............................................369
18.5.4 Regular shift mode .....................................................................370
18.6 ADC registers............................................................................ 371
18.6.1 ADC status register (ADC_STS) ..................................................373
18.6.2 ADC control register1 (ADC_CTRL1) ...........................................374
18.6.3 ADC control register2 (ADC_CTRL2) ...........................................375
18.6.4 ADC sampling time register 1 (ADC_SPT1)..................................377

AT32F435/437 Series Reference Manual
2022.11.11 Page 17 Rev 2.03
18.6.5 ADC sampling time register 2 (ADC_SPT2)..................................378
18.6.6 ADC preempted channel data offset register x
(ADC_ PCDTOx) (x=1..4)......................................................................380
18.6.7 ADC voltage monitor high threshold register (ADC_VWHB)...........380
18.6.8 ADC voltage monitor low threshold register (ADC_ VWLB)............381
18.6.9 ADC ordinary sequence register 1 (ADC_ OSQ1) .........................381
18.6.10 ADC ordinary sequence register 2 (ADC_ OSQ2) ......................381
18.6.11 ADC ordinary sequence register 3 (ADC_ OSQ3) ......................381
18.6.12 ADC preempted sequence register (ADC_ PSQ)........................382
18.6.13 ADC preempted data register x (ADC_ PDTx) (x=1..4) ...............382
18.6.14 ADC ordinary data register (ADC_ ODT) ...................................382
18.6.15 ADC oversampling register (ADC_ OVSP).................................382
18.6.16 ADC calibration value register (ADC_CALVAL)..........................383
18.6.17 ADC common status register (ADC_CSTS)................................383
18.6.18 ADC common control register (ADC_CSTS) ..............................385
18.6.19 ADC common data register (ADC_CODT)..................................387
19 Digital-to-analog converter (DAC)............................................... 388
19.1 DAC introduction ....................................................................... 388
19.2 DAC main features..................................................................... 388
19.3 Design tips................................................................................ 388
19.4 Functional overview ................................................................... 389
19.4.1 Trigger events............................................................................389
19.4.2 Noise/Triangular-wave generation ...............................................389
19.4.3 DAC data alignment ...................................................................390
19.5 DAC registers............................................................................ 391
19.5.1 DAC control register (DAC_CTRL)...............................................391
19.5.2 DAC software trigger register (DAC_SWTRG) ..............................393
19.5.3 DAC1 12-bit right-aligned data holding register (DAC_ D1DTH12R)394
19.5.4 DAC1 12-bit left-aligned data holding register (DAC_ D1DTH12L) .394
19.5.5 DAC1 8-bit right-aligned data holding register (DAC_ D1DTH8R) ..394
19.5.6 DAC2 12-bit right-aligned data holding register (DAC_ D2DTH12R)394
19.5.7 DAC2 12-bit left-aligned data holding register (DAC_ D2DTH12L) .394
19.5.8 DAC2 8-bit right-aligned data holding register (DAC_ D2DTH8R) ..394
19.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_ DDTH12R)394

AT32F435/437 Series Reference Manual
2022.11.11 Page 18 Rev 2.03
19.5.10 Dual DAC 12-bit left-aligned data holding register (DAC_ DDTH12L)395
19.5.11 Dual DAC 8-bit right-aligned data holding register (DAC_ DDTH8R)395
19.5.12 DAC1 data output register (DAC_ D1ODT) ................................395
19.5.13 DAC2 data output register (DAC_ D2ODT) ................................395
19.5.14 DAC status register (DAC_STS) ...............................................395
20 CAN 396
20.1 CAN introduction ....................................................................... 396
20.2 CAN main features..................................................................... 396
20.3 Baud rate .................................................................................. 396
20.4 Interrupt management ................................................................ 399
20.5 Design tips................................................................................ 400
20.6 Functional overview ................................................................... 400
20.6.1 General description ....................................................................400
20.6.2 Operating modes........................................................................401
20.6.3 Test modes ................................................................................401
20.6.4 Message filtering........................................................................402
20.6.5 Message transmission ................................................................403
20.6.6 Message reception .....................................................................405
20.6.7 Error management......................................................................405
20.7 CAN registers............................................................................ 406
20.7.1 CAN control and status registers.................................................407
20.7.1.1 CAN master control register (CAN_MCTRL) ............................ 407
20.7.1.2 CAN master status register (CAN_MSTS)................................ 408
20.7.1.3 CAN transmit status register (CAN_TSTS) .............................. 409
20.7.1.4 CAN receive FIFO 0 register (CAN_RF0) ................................ 412
20.7.1.5 CAN receive FIFO 1 register (CAN_RF1) ................................ 412
20.7.1.6 CAN interrupt enable register (CAN_INTEN) ........................... 413
20.7.1.7 CAN error status register (CAN_ESTS) ................................... 414
20.7.1.8 CAN bit timing register (CAN_BTMG) ..................................... 415
20.7.2 CAN mailbox registers ................................................................415
20.7.2.1 Transmit mailbox identifier register (CAN_TMIx) (x=0..2) ......... 416
20.7.2.2 Transmit mailbox data length and time stamp register
(CAN_TMCx) (x=0..2)......................................................................... 416
20.7.2.3 Transmit mailbox data low register (CAN_TMDTLx) (x=0..2) ..... 417
20.7.2.4 Transmit mailbox data high register (CAN_TMDTHx) (x=0..2) ... 417

AT32F435/437 Series Reference Manual
2022.11.11 Page 19 Rev 2.03
20.7.2.5 Receive FIFO mailbox identifier register (CAN_RFIx) (x=0..1) .. 417
20.7.2.6 Receive FIFO mailbox data length and time stamp register
(CAN_RFCx) (x=0..1) ......................................................................... 417
20.7.2.7 Receive FIFO mailbox data low register (CAN_RFDTLx) (x=0..1)418
20.7.2.8 Receive FIFO mailbox data high register (CAN_RFDTHx) (x=0..1)418
20.7.3 CAN filter registers.....................................................................418
20.7.3.1 CAN filter control register (CAN_FCTRL) ................................ 418
20.7.3.2 CAN filter mode configuration register (CAN_FMCFG) ............. 418
20.7.3.3 CAN filter bit width configuration register (CAN_ FBWCFG)...... 418
20.7.3.4 CAN filter FIFO association register (CAN_ FRF) .................... 419
20.7.3.5 CAN filter activation control register (CAN_ FACFG) ................ 419
20.7.3.6 CAN filter bank i filter bit register (CAN_ FiFBx) (i=0..13; x=1..2)419
21 Universal serial bus full-seed device interface (OTGFS)............. 420
21.1 USBFS structure........................................................................ 420
21.2 OTGFS functional description ..................................................... 420
21.3 OTGFS clock and pin configuration ............................................. 421
21.3.1 OTGFS clock configuration .........................................................421
21.3.2 OTGFS pin configuration ............................................................421
21.4 OTGFS interrupts ...................................................................... 422
21.5 OTGFS functional description ..................................................... 422
21.5.1 OTGFS initialization ...................................................................422
21.5.2OTGFS FIFO configuration .........................................................423
21.5.2.1 Device mode ........................................................................ 423
21.5.2.2 Host mode............................................................................ 424
21.5.2.3 Refresh controller transmit FIFO ............................................ 425
21.5.3 OTGFS host mode......................................................................425
21.5.3.1 Host initialization .................................................................. 425
21.5.3.2 OTGFS channel initialization.................................................. 426
21.5.3.3 Halting a channel .................................................................. 426
21.5.3.4 Queue depth......................................................................... 427
21.5.3.5 Special cases ....................................................................... 428
21.5.3.6 Host HFIR feature ................................................................. 428
21.5.3.7 Initialize bulk and control IN transfers..................................... 430
21.5.3.8 Initialize bulk and control OUT/SETUP transfers...................... 432
21.5.3.9 Initialize interrupt IN transfers................................................ 434
21.5.3.10 Initialize interrupt OUT transfers ........................................ 436

AT32F435/437 Series Reference Manual
2022.11.11 Page 20 Rev 2.03
21.5.3.11 Initialize synchronous IN transfers...................................... 438
21.5.3.12 Initialize synchronous OUT transfers .................................. 439
21.5.4 OTGFS device mode ..................................................................441
21.5.4.1 Device initialization............................................................... 441
21.5.4.2 Endpoint initialization on USB reset........................................ 441
21.5.4.3 Endpoint initialization on enumeration completion.................... 442
21.5.4.4 Endpoint initialization on SetAddress command....................... 442
21.5.4.5 Endpoint initialization on SetConfiguration/SetInterface
command .......................................................................................... 442
21.5.4.6 Endpoint activation ............................................................... 442
21.5.4.7 USB endpoint deactivation..................................................... 443
21.5.4.8 Control write transfers (SETUP/Data OUT/Status IN) ............... 443
21.5.4.9 Control read transfers (SETUP/Data IN/Status OUT)................ 443
21.5.4.10 Control transfers (SETUP/Status IN)................................... 444
21.5.4.11 Read FIFO packets ........................................................... 444
21.5.4.12 OUT data transfers ........................................................... 445
21.5.4.13 IN data transfers............................................................... 447
21.5.4.14 Non-periodic (bulk and control) IN data transfers................. 448
21.5.4.15 Non-synchronous OUT data transfers ................................. 449
21.5.4.16 Synchronous OUT data transfers........................................ 451
21.5.4.17 Enable synchronous endpoints........................................... 452
21.5.4.18 Incomplete synchronous OUT data transfers ....................... 454
21.5.4.19 Incomplete synchronous IN data transfers........................... 455
21.5.4.20 Periodic IN (interrupt and synchronous) data transfers......... 455
21.6 OTGFS control and status registers............................................. 457
21.6.1 CSR register map.......................................................................457
21.6.2 OTGFS register address map......................................................458
21.6.3 OTGFS global registers ..............................................................462
21.6.3.1 OTGFS status and control register (OTGFS_GOTGCTL) .......... 462
21.6.3.2 OTGFS interrupt status control register (OTGFS_GOTGINT) .... 462
21.6.3.3 OTGFS AHB configuration register (OTGFS_GAHBCFG).......... 462
21.6.3.4 OTGFS USB configuration register (OTGFS_GUSBCFG).......... 463
21.6.3.5 OTGFS reset register (OTGFS_GRSTCTL).............................. 464
21.6.3.6 OTGFS interrupt register (OTGFS_GINTSTS).......................... 466
21.6.3.7 OTGFS interrupt mask register (OTGFS_GINTMSK) ................ 469
21.6.3.8 OTGFS receive status debug read/OTG status read and POP
registers (OTGFS_GRXSTSR / OTGFS_GRXSTSP).............................. 470
21.6.3.9 OTGFS receive FIFO size register (OTGFS_GRXFSIZ) ............ 471