ARTERY AT32F423 Series User manual

AT32F423 Series Reference Manual
2023.04.25Page 1 Rev 2.01
ARM®-based 32-bit CortexTM-M4F MCU, 64 to 256 KB Flash, sLib, 15 timers,
1 ADC, 18 communication interfaces (CAN and OTGFS)
Core: ARM®32-bit CortexTM-M4F CPU with FPU
−150 MHz maximum frequency, with a Memory
Protection Unit (MPU), single-cycle multiplication
and hardware division
−Floating Point Unit (FPU)
−DSP instructions
Memories
−64 to 256 Kbytes of Flash memory
−20 Kbytes of boot memory used as a Bootloader or
as a general instruction/data memory (one-time
configured)
−sLib: configurable part of main Flash as a library
area with code executable but secured, non-
readable
−Up to 48 Kbytes of SRAM
−External memory controller (XMC) with 16-bit data
bus supporting multiplexed PSRAM and NOR
memories
XMC as LCD parallel interface, 8080/6800 modes
Power control (PWC)
−2.4 V to 3.6 V power supply
−Power-on reset (POR)/low-voltage reset (LVR), and
power voltage monitor (PVM)
−Low-power modes: Sleep, Deepsleep and Standby
modes
−20 x 32-bit battery powered registers (ERTC_BPR)
Clock and reset management (CRM)
−4 to 25 MHz crystal (HEXT)
−48 MHz internal factory-trimmed HICK (±1% at
TA=25 °C, ±2.5% at TA=-40 to +105 °C), with
automatic clock calibration (ACC)
−32 kHz crystal (LEXT)
−Low speed internal clock (LICK)
Analog
−1 x 12-bit 5.33 MSPS A/D converter, up to 24 input
channels, 12/10/8/6-bit configurable resolution;
hardware over-sampling up to equivalent 16-bit
resolution
−Temperature sensor (VTS), internal reference voltage
(VINTR)
−2 x 12-bit D/A converters
DMA: 14-channel DMA controller
Up to 87 fast GPIOs
−All mappable on 16 external interrupts (EXINT)
−Almost 5 V-tolerant
Up to 15 timers (TMR)
−1 x 16-bit 7-channel advanced timer with dead-time
generator and emergency break
−Up to 8 x16-bit and 1x 32-bit general-purpose
timers, each with up to 4 IC/OC/PWM or pulse
counter and quadrature (incremental) encoder input
−2 x 16-bit basic timers
−2 x watchdog timers (general WDT and windowed
WWDT)
−SysTick timer: a 24-bit downcounter
ERTC: enhanced RTC with auto wakeup, alarm,
subsecond accuracy, hardware calendar and
calibration feature
Up to 18 communication interfaces
−Up to 3 x I2C interfaces (SMBus/PMBus)
−Up to 3 x SPIs (36 Mbit/s), all with multiplexed half-
duplex I2S; 2 x half-duplex I2S combined for full-
duplex support
−Up to 8 x USARTs support master synchronization
SPI and modem control, ISO7816 interface, LIN,
IrDA, and RS485 drive enable, TX/RX swap
−Up to 2 x CAN (2.0B Active), each with dedicated
256KB buffer
−USB OTG full speed controller with on-chip PHY,
dedicated 1280KB buffer, supporting crystal-less in
device mode
−Infrared transmitter (IRTMR)
CRC calculation unit
96-bit ID (UID)
Debug mode
−SWD and JTAG interfaces
Temperature range: -40 to +105℃
Packaging
−LQFP100 14 x 14 mm LQFP64 10 x 10 mm
LQFP64 7 x 7 mm LQFP48 7 x 7 mm
QFN48 6 x 6 mm QFN36 6 x 6 mm
QFN32 4 x 4 mm
List of models
Internal Flash
Model
64 Kbytes
AT32F423K8U7-4 AT32F423T8U7
AT32F423C8U7 AT32F423C8T7
AT32F423R8T7-7 AT32F423R8T7
AT32F423V8T7
128 Kbytes
AT32F423KBU7-4 AT32F423TBU7
AT32F423CBU7 AT32F423CBT7
AT32F423RBT7-7 AT32F423RBT7
AT32F423VBT7
256 Kbytes
AT32F423KCU7-4 AT32F423TCU7
AT32F423CCU7 AT32F423CCT7
AT32F423RCT7-7 AT32F423RCT7
AT32F423VCT7

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Contents
1System architecture...................................................................... 34
1.1 System overview..........................................................................35
1.1.1 ARM CortexTM-M4F processor ...................................................... 35
1.1.2 Bit band...................................................................................... 35
1.1.3 Interrupt and exception vectors .................................................... 38
1.1.4 System Tick (SysTick) ................................................................. 41
1.1.5 Reset ......................................................................................... 41
1.2 List of abbreviations for registers ..................................................43
1.3 Device characteristics information.................................................43
1.3.1 Flash memory size register .......................................................... 43
1.3.2 Device electronic signature.......................................................... 43
2Memory resources ........................................................................ 44
2.1 Internal memory address map.......................................................44
2.2 Flash memory..............................................................................44
2.3 SRAM memory.............................................................................46
2.4 Peripheral address map................................................................46
3Power control (PWC)..................................................................... 49
3.1 Introduction .................................................................................49
3.2 Main features ..............................................................................49
3.3 POR/LVR ....................................................................................49
3.4 Power voltage monitor (PVM)........................................................50
3.5 Power domain..............................................................................51
3.6 Power saving modes ....................................................................51
3.7 PWC registers .............................................................................53
3.7.1 Power control register (PWC_CTRL) ............................................ 53
3.7.2 Power control/status register (PWC_CTRLSTS) ............................ 54
3.7.3 LDO output voltage select register (PWC_LDOOV)........................ 55
4Clock and reset manage (CRM) ..................................................... 56
4.1 Clock ..........................................................................................56
4.1.1 Clock sources ............................................................................. 56

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4.1.2 System clock............................................................................... 58
4.1.3 Peripheral clock .......................................................................... 58
4.1.4 Clock fail detector ....................................................................... 58
4.1.5 Auto step-by-step system clock switch.......................................... 58
4.1.6 Internal clock output .................................................................... 58
4.1.7 Interrupts.................................................................................... 59
4.2 Reset..........................................................................................59
4.2.1 System reset............................................................................... 59
4.2.2 Battery powered domain reset...................................................... 59
4.3 CRM registers .............................................................................60
4.3.1 Clock control register (CRM_CTRL).............................................. 60
4.3.2 PLL clock configuration register (CRM_PLLCFG) .......................... 61
4.3.3 Clock configuration register (CRM_CFG) ...................................... 62
4.3.4 Clock interrupt register (CRM_CLKINT) ........................................ 64
4.3.5 AHB peripheral reset register 1 (CRM_AHBRST1)......................... 65
4.3.6 AHB peripheral reset register 2 (CRM_AHBRST2)......................... 65
4.3.7 AHB peripheral reset register 3 (CRM_AHBRST3)......................... 66
4.3.8 APB1 peripheral reset register (CRM_APB1RST) .......................... 66
4.3.9 APB2 peripheral reset register (CRM_APB2RST) .......................... 67
4.3.10 AHB peripheral clock enable register 1 (CRM_AHBEN1)................ 68
4.3.11 AHB peripheral clock enable register 2 (CRM_AHBEN2)................ 68
4.3.12 AHB peripheral clock enable register 3 (CRM_AHBEN3)................ 69
4.3.13 APB1 peripheral clock enable register (CRM_APB1EN) ................. 69
4.3.14 APB2 peripheral clock enable register (CRM_APB2EN) ................. 70
4.3.15 AHB peripheral clock enable in low power mode register
(CRM_AHBLPEN1)................................................................................ 71
4.3.16 AHB peripheral clock enable in low power mode register 2
(CRM_AHBLPEN2)................................................................................ 72
4.3.17 AHB peripheral clock enable in low power mode register 3
(CRM_AHBLPEN3)................................................................................ 72
4.3.18 APB1 peripheral clock enable in low power mode register
(CRM_APB1LPEN)................................................................................ 72
4.3.19 APB2 peripheral clock enable in low power mode register
(CRM_APB2LPEN)................................................................................ 73
4.3.20 Peripheral independent clock select register (CRM_PICLKS) ......... 74

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4.3.21 Battery powered domain control register (CRM_BPDC).................. 74
4.3.22 Control/status register (CRM_CTRLSTS) ...................................... 75
4.3.23 Additional register 1 (CRM_MISC1) .............................................. 76
4.3.24 Additional register 2 (CRM_MISC2) .............................................. 77
5Flash memory controller (FLASH) ................................................. 78
5.1 FLASH introduction......................................................................78
5.2 Flash memory operation ...............................................................80
5.2.1 Unlock/lock ................................................................................. 80
5.2.2 Erase operation........................................................................... 80
5.2.3 Programming operation................................................................ 82
5.2.4 Read operation ........................................................................... 84
5.3 Main Flash memory extension area ...............................................84
5.4 User system data area operation...................................................84
5.4.1 Unlock/lock ................................................................................. 84
5.4.2 Erase operation........................................................................... 84
5.4.3 Programming operation................................................................ 85
5.4.4 Read operation ........................................................................... 86
5.5 Flash memory protection ..............................................................86
5.5.1 Access protection........................................................................ 87
5.5.2 Erase/program protection............................................................. 87
5.6 Read access................................................................................88
5.7 Special functions .........................................................................88
5.7.1 Security library settings ............................................................... 88
5.7.2 Boot memory used as Flash memory extension ............................. 89
5.7.3 CRC verify .................................................................................. 89
5.8 FLASH memory registers..............................................................89
5.8.1 Flash performance select register (FLASH_PSR) .......................... 90
5.8.2 Flash unlock register (FLASH_UNLOCK) ...................................... 91
5.8.3 Flash user system data unlock register (FLASH_USD_UNLOCK) ... 91
5.8.4 Flash status register (FLASH_STS) .............................................. 91
5.8.5 Flash control register (FLASH_CTRL)........................................... 91
5.8.6 Flash address register (FLASH_ADDR) ........................................ 92
5.8.7 User system data register (FLASH_USD)...................................... 92

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5.8.8 Erase/program protection status register (FLASH_EPPS) .............. 92
5.8.9 Flash security library status register 0 (SLIB_STS0)...................... 93
5.8.10 Flash security library status register 1 (SLIB_STS1)...................... 93
5.8.11 Security library password clear register (SLIB_PWD_CLR) ............ 94
5.8.12 Security library additional status register (SLIB_MISC_STS).......... 94
5.8.13 Flash CRC address register (FLASH_CRC_ADDR)........................ 94
5.8.14 Flash CRC control register (FLASH_CRC_CTRL) .......................... 94
5.8.15 Flash CRC check result register (FLASH_CRC_CHKR).................. 95
5.8.16 Security library password setting register (SLIB_SET_PWD).......... 95
5.8.17 Security library address setting register (SLIB_SET_RANGE) ........ 95
5.8.18 Flash extension memory security library setting register
(EM_SLIB_SET).................................................................................... 96
5.8.19 Boot memory mode setting register (BTM_MODE_SET) ................. 96
5.8.20 Security library unlock register (SLIB_UNLOCK) ........................... 96
6GPIOs and IOMUX ......................................................................... 97
6.1 Introduction ...............................................................................97
6.2 Function overview......................................................................97
6.2.1 GPIO structure ............................................................................ 97
6.2.2 GPIO reset status........................................................................ 98
6.2.3 General-purpose input configuration............................................. 98
6.2.4 Analog input/output configuration ................................................. 98
6.2.5 General-purpose output configuration........................................... 98
6.2.6 I/O port protection ....................................................................... 99
6.2.7 IOMUX structure ......................................................................... 99
6.2.8 Multiplexed function pull-up/down configuration ...........................100
6.2.9 IOMUX input/output ....................................................................100
6.2.10 Peripheral MUX function configuration.........................................110
6.2.11 IOMUX mapping priority..............................................................110
6.2.12 External interrupt/wake-up lines...............................................111
6.3 GPIO registers ......................................................................... 111
6.3.1 GPIO configuration register (GPIOx_CFGR) (x=A..F)....................112
6.3.2 GPIO output mode register (GPIOx_OMODE) (x=A..F)..................112
6.3.3 GPIO drive capability register (GPIOx_ODRVR) (x=A..F)..............112
6.3.4 GPIO pull-up/pull-down register (GPIOx_PULL) (x=A..F) ..............112

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6.3.5 GPIO input data register (GPIOx_IDT) (x=A..F) ............................112
6.3.6 GPIO output data register (GPIOx_ODT) (x=A..F) ........................113
6.3.7 GPIO set/clear register (GPIOx_SCR) (x=A..F) ............................113
6.3.8 GPIO write protection register (GPIOx_WPR) (x=A..F)..................113
6.3.9 GPIO multiplexed function low register (GPIOx_MUXL) (x=A..F) ...113
6.3.10 GPIO multiplexed function high register (GPIOx_MUXH) (x=A..F)..114
6.3.11 GPIO port bit clear register (GPIOx_CLR) (x=A..F).......................114
6.3.12 GPIO port bit toggle register (GPIOx_TOGR) (x=A..F) ..................114
6.3.13 GPIO huge current control register (GPIOx_HDRV) (x=A..F) .........114
7System configuration controller (SCFG) ..................................... 115
7.1 Introduction ............................................................................... 115
7.2 SCFG registers.......................................................................... 115
7.2.1 SCFG configuration register 1 (SCFG_CFG1) ..............................115
7.2.2 SCFG configuration register 2 (SCFG_CFG2) ..............................115
7.2.3 SCFG external interrupt configuration register 1 (SCFG_EXINTC1)116
7.2.4 SCFG external interrupt configuration register 2 (SCFG_EXINTC2)117
7.2.5 SCFG external interrupt configuration register 3 (SCFG_EXINTC3)117
7.2.6 SCFG external interrupt configuration register 4 (SCFG_EXINTC4)118
7.2.7 SCFG ultra high souring/sinking strength (SCFG_UHDRV) ...........119
8External interrupt/event controller (EXINT)................................. 120
8.1 EXINT introduction..................................................................... 120
8.2 Function overview and configuration procedure ............................ 120
8.3 EXINT registers ......................................................................... 121
8.3.1 Interrupt enable register (EXINT_INTEN).....................................121
8.3.2 Event enable register (EXINT_EVTEN) ........................................121
8.3.3 Polarity configuration register 1 (EXINT_POLCFG1).....................121
8.3.4 Polarity configuration register 2 (EXINT_POLCFG2).....................122
8.3.5 Software trigger register (EXINT_SWTRG)...................................122
8.3.6 Interrupt status register (EXINT_INTSTS) ....................................122
9DMA controller (DMA) ................................................................. 123
9.1 Introduction ............................................................................... 123
9.2 Main features ............................................................................ 123

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9.3 Function overview...................................................................... 123
9.3.1 DMA configuration......................................................................123
9.3.2 Handshake mechanism ...............................................................124
9.3.3 Arbiter .......................................................................................124
9.3.4 Programmable data transfer width ...............................................124
9.3.5 Errors ........................................................................................125
9.3.6 Interrupts...................................................................................126
9.4 DMA multiplexer (DMAMUX) ....................................................... 126
9.4.1 DMAMUX function overview ........................................................126
9.4.2 DMAMUX overflow interrupts ......................................................128
9.5 DMA registers............................................................................ 129
9.5.1 DMA interrupt status register (DMA_STS)....................................130
9.5.2 DMA interrupt flag clear register (DMA_CLR) ...............................132
9.5.3 DMA channel-x configuration register (DMA_CxCTRL) (x = 1…7)..134
9.5.4 DMA channel-x number of data register (DMA_CxDTCNT) (x = 1…7)134
9.5.5 DMA channel-x peripheral address register (DMA_CxPADDR)
(x = 1…7) ............................................................................................135
9.5.6 DMA channel-x memory address register (DMA_CxMADDR) (x = 1…7)135
9.5.7 DMAMUX select register (DMA_MUXSEL) ...................................135
9.5.8 DMAMUX channel-x control register (DMA_MUXCxCTRL) (x = 1…7)135
9.5.9 DMAMUX generator-x control register (DMA_MUXGxCTRL) (x = 1…4)136
9.5.10 DMAMUX channel synchronization status register
(DMA_MUXSYNCSTS) .........................................................................136
9.5.11 DMAMUX channel interrupt clear register (DMA_MUXSYNCCLR)..137
9.5.12 DMAMUX generator interrupt status register (DMA_MUXGSTS) ....137
9.5.13 DMAMUX generator interrupt clear register (DMA_MUXGCLR)......137
10 CRC calculation unit (CRC)......................................................... 138
10.1 CRC introduction ....................................................................... 138
10.2 CRC function overview ............................................................... 138
10.3 CRC registers............................................................................ 139
10.3.1 Data register (CRC_DT)..............................................................139
10.3.2 Common data register (CRC_CDT)..............................................139
10.3.3 Control register (CRC_CTRL)......................................................140
10.3.4 Initialization register (CRC_IDT) .................................................140

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11 I2C interface ................................................................................ 141
11.1 I2C instruction............................................................................ 141
11.2 I2C main features....................................................................... 141
11.3 I2C function overview ................................................................. 141
11.4 I2C interface .............................................................................. 142
11.4.1 I2C timing control .......................................................................144
11.4.2 Data transfer management..........................................................146
11.4.3 I2C master communication flow ...................................................147
11.4.4 I
2
C slave communication flow .....................................................152
11.4.5 SMBus.......................................................................................156
11.4.6 SMBus master communication flow..............................................158
11.4.7 SMBus slave communication flow................................................161
11.4.8 Data transfer using DMA.............................................................165
11.4.9 Error management......................................................................166
11.4.10 Wakeup from Deepsleep mode at address matching event .........167
11.5 I2C interrupt requests ................................................................. 167
11.6 I2C debug mode......................................................................... 168
11.7 I2C registers .............................................................................. 168
11.7.1 Control register 1 (I2C_CTRL1)...................................................168
11.7.2 Control register 2 (I2C_CTRL2)...................................................169
11.7.3 Own address register 1 (I2C_OADDR1) .......................................170
11.7.4 Own address register 2 (I2C_OADDR2) .......................................170
11.7.5 Timing register (I2C_CLKCTRL) ..................................................170
11.7.6 Timeout register (I2C_TIMEOUT) ................................................171
11.7.7 Status register (I2C_STS)...........................................................171
11.7.8 Status clear register (I2C_CLR) ..................................................172
11.7.9 PEC register (I2C_PEC) .............................................................173
11.7.10 Receive data register (I2C_RXDT)............................................173
11.7.11 Transmit data register (I2C_TXDT) ...........................................173
12 Universal synchronous/asynchronous receiver/transmitter (USART)174
12.1 USART introduction ................................................................... 174
12.2 Full-duplex/half-duplex selector .................................................. 175
12.3 Mode selector............................................................................ 176

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12.3.1 Introduction................................................................................176
12.3.2 Configuration procedure .............................................................176
12.4 USART frame format and configuration........................................ 179
12.5 DMA transfer introduction ........................................................... 181
12.5.1 Transmission using DMA ............................................................181
12.5.2 Reception using DMA .................................................................182
12.6 Baud rate generation.................................................................. 182
12.6.1 Introduction................................................................................182
12.6.2 Configuration .............................................................................182
12.7 Transmitter................................................................................ 183
12.7.1 Transmitter introduction..............................................................183
12.7.2 Transmitter configuration ............................................................183
12.8 Receiver ................................................................................... 184
12.8.1 Receiver introduction..................................................................184
12.8.2 Receiver configuration................................................................184
12.8.3 Start bit and noise detection .......................................................185
12.9 Low-power wakeup .................................................................... 186
12.10Tx/Rx swap ............................................................................... 186
12.11Interrupt requests ...................................................................... 187
12.12I/O pin control............................................................................ 188
12.13USART registers........................................................................ 188
12.13.1 Status register (USART_STS) ..................................................188
12.13.2 Data register (USART_DT).......................................................190
12.13.3 Baud rate register (USART_BAUDR) ........................................190
12.13.4 Control register 1 (USART_CTRL1) ..........................................190
12.13.5 Control register 2 (USART_CTRL2) ..........................................192
12.13.6 Control register 3 (USART_CTRL3) ..........................................193
12.13.7 Guard time and divider register (GDIV) .....................................194
12.13.8 Receiver timeout detection register (RTOV) ..............................194
12.13.9 Interrupt flag clear register (IFC) ..............................................194
13 Serial peripheral interface (SPI).................................................. 195
13.1 SPI introduction......................................................................... 195
13.2 Functional overview ................................................................... 195

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13.2.1 SPI description...........................................................................195
13.2.2 Full-duplex/half-duplex selector ..................................................196
13.2.3 Chip select controller..................................................................198
13.2.4 SPI_SCK controller ....................................................................198
13.2.5 CRC ..........................................................................................199
13.2.6 DMA transfer..............................................................................200
13.2.7 TI mode .....................................................................................200
13.2.8 Transmitter ................................................................................201
13.2.9 Receiver ....................................................................................201
13.2.10 Motorola mode ........................................................................202
13.2.11 TI mode ..................................................................................204
13.2.12 Interrupts ................................................................................205
13.2.13 IO pin control ..........................................................................205
13.2.14 Precautions.............................................................................205
13.3 I2S functional description............................................................ 206
13.3.1 I2S introduction ..........................................................................206
13.3.2I2S full-duplex ............................................................................207
13.3.3 Operating mode selection ...........................................................207
13.3.4 Audio protocol selector ...............................................................209
13.3.5 I2S_CLK controller .....................................................................210
13.3.6 DMA transfer..............................................................................211
13.3.7 Transmitter/Receiver ..................................................................212
13.3.8 Interrupts...................................................................................213
13.3.9 IO pin control .............................................................................213
13.4 SPI registers ............................................................................. 213
13.4.1 SPI control register1 (SPI_CTRL1) (Not used in I2S mode) ...........213
13.4.2 SPI control register2 (SPI_CTRL2) ..............................................215
13.4.3 SPI status register (SPI_STS) .....................................................215
13.4.4 SPI data register (SPI_DT) .........................................................216
13.4.5 SPICRC register (SPI_CPOLY) (Not used in I2S mode).................216
13.4.6 SPIRxCRC register (SPI_RCRC) (Not used in I2S mode) ..............216
13.4.7 SPITxCRC register (SPI_TCRC)..................................................217
13.4.8 SPI_I2S register (SPI_I2SCTRL) .................................................217
13.4.9 SPI_I2S prescaler register (SPI_I2SCLKP) ..................................218

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14 Timer .......................................................................................... 219
14.1 Basic timer (TMR6 and TMR7) .................................................... 220
14.1.1 TMR6 and TMR7 introduction......................................................220
14.1.2 TMR6 and TMR7 main features ...................................................220
14.1.3 TMR6 and TMR7 function overview .............................................220
14.1.3.1 Counting clock...................................................................... 220
14.1.3.2 Counting mode ..................................................................... 220
14.1.3.3 Debug mode ......................................................................... 221
14.1.4 TMR6 and TMR7 registers ..........................................................222
14.1.4.1 TMR6 and TMR7 control register1 (TMRx_CTRL1)................... 222
14.1.4.2 TMR6 and TMR7 control register2 (TMRx_CTRL2)................... 223
14.1.4.3 TMR6 and TMR7 DMA/interrupt enable register (TMRx_IDEN) .. 223
14.1.4.4 TMR6 and TMR7 interrupt status register (TMRx_ISTS) ........... 223
14.1.4.5 TMR6 and TMR7 software event register (TMRx_SWEVT) ........ 223
14.1.4.6 TMR6 and TMR7 counter value (TMRx_CVAL) ........................ 223
14.1.4.7 TMR6 and TMR7 division (TMRx_DIV) .................................... 223
14.1.4.8 TMR6 and TMR7 period register (TMRx_PR) ........................... 224
14.2 General-purpose timer (TMR2 to TMR4) ...................................... 225
14.2.1 TMR2 to TMR4 introduction ........................................................225
14.2.2 TMR2 to TMR4 main features......................................................225
14.2.3 TMR2 to TMR4 functional overview .............................................225
14.2.3.1 Counting clock...................................................................... 225
14.2.3.2 Counting mode ..................................................................... 228
14.2.3.3 TMR input function................................................................ 232
14.2.3.4 TMR output function.............................................................. 234
14.2.3.5 TMR synchronization............................................................. 238
14.2.3.6 Debug mode ......................................................................... 240
14.2.4 TMR2 to TMR4 registers.............................................................240
14.2.4.1 Control register 1 (TMRx_CTRL1) .......................................... 241
14.2.4.2 Control register 2 (TMRx_CTRL2) .......................................... 242
14.2.4.3 Slave timer control register (TMRx_STCTRL) .......................... 242
14.2.4.4 DMA/interrupt enable register (TMRx_IDEN) ........................... 243
14.2.4.5 Interrupt status register (TMRx_ISTS) .................................... 244
14.2.4.6 Software event register (TMRx_SWEVT) ................................. 245
14.2.4.7 Channel mode register1 (TMRx_CM1) .................................... 245
14.2.4.8 Channel mode register2 (TMRx_CM2) .................................... 247

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14.2.4.9 Channel control register (TMRx_CCTRL) ................................ 248
14.2.4.10 Counter value (TMRx_CVAL) ............................................. 249
14.2.4.11 Frequency division value (TMRx_DIV) ................................ 249
14.2.4.12 Period register (TMRx_PR) ................................................ 249
14.2.4.13 Channel 1 data register (TMRx_C1DT) ............................... 249
14.2.4.14 Channel 2 data register (TMRx_C2DT) ............................... 251
14.2.4.15 Channel 3 data register (TMRx_C3DT) ............................... 251
14.2.4.16 Channel 4 data register (TMRx_C4DT) ............................... 251
14.2.4.17 DMA control register (TMRx_DMACTRL) ............................. 251
14.2.4.18 DMA data register (TMRx_DMADT) .................................... 252
14.3 General-purpose timer (TMR9 and TMR12) .................................. 252
14.3.1 TMR9 and TMR12 introduction ....................................................252
14.3.2 TMR9 and TMR12 main features .................................................252
14.3.3 TMR9 and TMR12 functional overview .........................................252
14.3.3.1 Counting clock...................................................................... 252
14.3.3.2 Counting mode ..................................................................... 255
14.3.3.3 TMR input function................................................................ 260
14.3.3.4 TMR output function.............................................................. 263
14.3.3.5 TMR break function............................................................... 266
14.3.3.6 TMR synchronization............................................................. 267
14.3.3.7 Debug mode ......................................................................... 268
14.3.4 TMR9 and TMR12 registers ........................................................269
14.3.4.1 TMR9 and TMR12 control register1 (TMRx_CTRL1) ................. 269
14.3.4.2 TMR9 and TMR12 control register 2 (TMRx_CTRL2) ................ 270
14.3.4.3 TMR9 and TMR12 slave timer control register (TMR1_STCTRL) 271
14.3.4.4 TMR9 and TMR12 DMA/interrupt enable register (TMRx_IDEN) 271
14.3.4.5 TMR9 and TMR12 interrupt status register (TMRx_ISTS) ......... 272
14.3.4.6 TMR9 and TMR12 software event register (TMRx_SWEVT) ...... 273
14.3.4.7 TMR9 and TMR12 channel mode register 1 (TMRx_CM1) ......... 273
14.3.4.8 TMR9 and TMR12 Channel control register (TMRx_CCTRL) ..... 275
14.3.4.9 TMR9 and TMR12 counter value (TMRx_CVAL)....................... 276
14.3.4.10 TMR9 and TMR12 division value (TMRx_DIV) ..................... 276
14.3.4.11 TMR9 and TMR12 period register (TMRx_PR) ..................... 276
14.3.4.12 TMR9 and TMR12 repetition period register (TMRx_RPR) .... 276
14.3.4.13 TMR9 and TMR12 channel 1 data register (TMRx_C1DT) ..... 276
14.3.4.14 TMR9 and TMR12 channel 2 data register (TMRx_C2DT) ..... 277
14.3.4.15 TMR9 and TMR12 break register (TMRx_BRK) .................... 277

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14.3.4.16 TMR9 and TMR12 DMA control register (TMRx_DMACTRL).. 278
14.3.4.17 TMR9 and TMR12 DMA data register (TMRx_DMADT) ......... 278
14.4 General-purpose timer (TMR10/11/13/14) .................................... 279
14.4.1 TMRx introduction ......................................................................279
14.4.2 TMRx main features ...................................................................279
14.4.3 TMRx functional overview ...........................................................279
14.4.3.1 Counting clock...................................................................... 279
14.4.3.2 Counting mode ..................................................................... 280
14.4.3.3 TMR input function................................................................ 283
14.4.3.4 TMR output function.............................................................. 284
14.4.3.5 TMR break function............................................................... 287
14.4.3.6 Debug mode ......................................................................... 288
14.4.4 TMRx registers...........................................................................289
14.4.4.1 TMRx control register1 (TMRx_CTRL1) (x=10/11/13/14)........... 289
14.4.4.2 TMRx control register 2 (TMRx_CTRL2) (x=10/11/13/14).......... 290
14.4.4.3 TMRx DMA/interrupt enable register (TMRx_IDEN) (x=10/11/13/14)290
14.4.4.4 TMRx interrupt status register (TMRx_ISTS) (x=10/11/13/14) ... 291
14.4.4.5 TMRx software event register (TMRx_SWEVT) (x=10/11/13/14) 291
14.4.4.6 TMRx channel mode register1 (TMRx_CM1) (x=10/11/13/14).... 292
14.4.4.7 TMRx Channel control register (TMRx_CCTRL) (x=10/11/13/14) 293
14.4.4.8 TMRx counter value (TMRx_CVAL) (x=10/11/13/14)................. 295
14.4.4.9 TMRx division value (TMRx_DIV) (x=10/11/13/14) ................... 295
14.4.4.10 TMRx period register (TMRx_PR) (x=10/11/13/14) ............... 295
14.4.4.11 TMRx repetition period register (TMRx_RPR) (x=10/11/13/14)295
14.4.4.12 TMRx channel 1 data register (TMRx_C1DT) (x=10/11/13/14)295
14.4.4.13 TMRx break register (TMRx_BRK) (x=10/11/13/14) .............. 295
14.4.4.14 TMRX DMA control register (TMRX_DMACTRL) (X=10/11/13/14)297
14.4.4.15 TMRx DMA data register (TMRx_DMADT) (X=10/11/13/14)... 297
14.4.4.16 TMR14 channel input remap register (TMRx_RMP) .............. 297
14.5 Advanced-control timers (TMR1) ................................................. 298
14.5.1 TMR1 introduction ......................................................................298
14.5.2 TMR1 main features ...................................................................298
14.5.3 TMR1 functional overview...........................................................298
14.5.3.1 Counting clock...................................................................... 298
14.5.3.2 Counting mode ..................................................................... 301
14.5.3.3 TMR input function................................................................ 307
14.5.3.4 TMR output function.............................................................. 309

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14.5.3.5 TMR break function............................................................... 313
14.5.3.6 TMR synchronization............................................................. 314
14.5.3.7 Debug mode ......................................................................... 316
14.5.4 TMR1 registers ..........................................................................316
14.5.4.1 TMR1 control register1 (TMR1_CTRL1) .................................. 316
14.5.4.2 TMR1 control register2 (TMR1_CTRL2) .................................. 317
14.5.4.3 TMR1 slave timer control register (TMR1_STCTRL) ................. 318
14.5.4.4 TMR1 DMA/interrupt enable register (TMR1_IDEN).................. 319
14.5.4.5 TMR1 interrupt status register (TMR1_ISTS) ........................... 320
14.5.4.6 TMR1 software event register (TMR1_SWEVT)........................ 321
14.5.4.7 TMR1 channel mode register1 (TMR1_CM1) ........................... 321
14.5.4.8 TMR1 channel mode register2 (TMR1_CM2) ........................... 323
14.5.4.9 TMR1 channel control register (TMR1_CCTRL) ....................... 324
14.5.4.10 TMR1 counter value (TMR1_CVAL) .................................... 326
14.5.4.11 TMR1 division value (TMR1_DIV) ....................................... 326
14.5.4.12 TMR1 period register (TMR1_PR)....................................... 326
14.5.4.13 TMR1 repetition period register (TMR1_RPR)...................... 326
14.5.4.14 TMR1 channel 1 data register (TMR1_C1DT) ...................... 326
14.5.4.15 TMR1 channel 2 data register (TMR1_C2DT) ...................... 326
14.5.4.16 TMR1 channel 3 data register (TMR1_C3DT) ...................... 328
14.5.4.17 TMR1 channel 4 data register (TMRx_C4DT)....................... 328
14.5.4.18 TMR1 break register (TMR1_BRK)...................................... 328
14.5.4.19 TMR1 DMA control register (TMR1_DMACTRL) ................... 329
14.5.4.20 TMR1 DMA data register (TMR1_DMADT)........................... 330
14.5.4.21 TMR1 channel mode register3 (TMR1_ CM3) ...................... 330
14.5.4.22 TMR1 channel 5 data register (TMR1_C5DT) ...................... 330
15 Window watchdog timer (WWDT) ................................................ 331
15.1 WWDT introduction .................................................................... 331
15.2 WWDT main features ................................................................. 331
15.3 WWDT functional overview ......................................................... 331
15.4 Debug mode.............................................................................. 332
15.5 WWDT registers ........................................................................ 332
15.5.1 Control register (WWDT_CTRL) ..................................................332
15.5.2 Configuration register (WWDT_CFG)...........................................333
15.5.3 Status register (WWDT_STS)......................................................333

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16 Watchdog timer (WDT) ................................................................ 334
16.1 WDT introduction ....................................................................... 334
16.2 WDT main features .................................................................... 334
16.3 WDT functional overview ............................................................ 334
16.4 Debug mode.............................................................................. 335
16.5 WDT registers ........................................................................... 335
16.5.1 Command register (WDT_CMD) ..................................................336
16.5.2 Divider register (WDT_DIV).........................................................336
16.5.3 Reload register (WDT_RLD)........................................................336
16.5.4 Status register (WDT_STS).........................................................336
16.5.5 Window register (WDT_WIN).......................................................337
17 Enhanced real-time clock (ERTC) ............................................... 338
17.1 ERTC introduction...................................................................... 338
17.2 ERTC main features................................................................... 338
17.3 ERTC function overview ............................................................. 339
17.3.1 ERTC clock................................................................................339
17.3.2 ERTC initialization......................................................................339
17.3.3 Periodic automatic wakeup .........................................................341
17.3.4 ERTC calibration ........................................................................341
17.3.5 Reference clock detection...........................................................342
17.3.6 Time stamp function ...................................................................342
17.3.7 Tamper detection .......................................................................343
17.3.8Multiplexed function output .........................................................343
17.3.9 ERTC wakeup ............................................................................344
17.4 ERTC registers.......................................................................... 345
17.4.1 ERTC time register (ERTC_TIME) ...............................................345
17.4.2 ERTC date register (ERTC_DATE) ..............................................346
17.4.3 ERTC control register (ERTC_CTRL)...........................................346
17.4.4 ERTC initialization and status register (ERTC_STS) .....................347
17.4.5 ERTC divider register (ERTC_DIV)..............................................349
17.4.6 ERTC wakeup timer register (ERTC_WAT) ..................................349
17.4.7 ERTC alarm clock A register (ERTC_ALA) ...................................349
17.4.8 ERTC alarm clock B register (ERTC_ALB) ...................................349

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17.4.9 ERTC write protection register (ERTC_WP) .................................350
17.4.10 ERTC subsecond register (ERTC_SBS) ....................................350
17.4.11 ERTC time adjustment register (ERTC_TADJ) ...........................350
17.4.12 ERTC time stamp time register (ERTC_TSTM) ..........................350
17.4.13 ERTC time stamp date register (ERTC_TSDT) ..........................351
17.4.14 ERTC time stamp subsecond register (ERTC_TSSBS) ...............351
17.4.15 ERTC smooth calibration register (ERTC_SCAL) .......................351
17.4.16 ERTC tamper configuration register (ERTC_TAMP) ...................352
17.4.17 ERTC alarm clock A subsecond register (ERTC_ALASBS) .........353
17.4.18 ERTC alarm clock B subsecond register (ERTC_ALBSBS) .........353
17.4.19 ERTC battery powered domain data register (ERTC_BPRx) .......353
18 Analog-to-digital converter (ADC)............................................... 354
18.1 ADC introduction ....................................................................... 354
18.2 ADC main features..................................................................... 354
18.3 ADC structure............................................................................ 355
18.4 ADC functional overview............................................................. 356
18.4.1 Channel management.................................................................356
18.4.1.1 Internal temperature sensor ................................................... 356
18.4.1.2 Internal reference voltage...................................................... 356
18.4.2 ADC operation process...............................................................356
18.4.2.1 Power-on and calibration ....................................................... 357
18.4.2.2 Trigger................................................................................. 358
18.4.2.3 Sampling and conversion sequence........................................ 358
18.4.3 Conversion sequence management .............................................359
18.4.3.1 Sequence mode .................................................................... 359
18.4.3.2 Preempted group automatic conversion mode ......................... 359
18.4.3.3 Repetition mode.................................................................... 360
18.4.3.4 Partition mode ...................................................................... 360
18.4.4 End of conversion ......................................................................361
18.4.5 Oversampling.............................................................................361
18.4.5.1 Oversampling of ordinary group of channels............................ 362
18.4.5.2 Oversampling of preempted group of channels ........................ 363
18.4.6 Data management ......................................................................363
18.4.6.1 Data alignment ..................................................................... 363
18.4.6.2 Data read ............................................................................. 364

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18.4.7 Voltage monitoring .....................................................................364
18.4.7.1 Status flag and interrupts ...................................................... 365
18.5 ADC registers ............................................................................ 365
18.5.1 ADC status register (ADC_STS) ..................................................366
18.5.2 ADC control register1 (ADC_CTRL1) ...........................................366
18.5.3 ADC control register2 (ADC_CTRL2) ...........................................368
18.5.4 ADC sampling time register 1 (ADC_SPT1)..................................369
18.5.5 ADC sampling time register 2 (ADC_SPT2)..................................371
18.5.6 ADC preempted channel data offset register x
(ADC_ PCDTOx) (x=1..4)......................................................................373
18.5.7 ADC voltage monitoring high threshold register (ADC_VWHB) ......373
18.5.8 ADC voltage monitor low threshold register (ADC_ VWLB)............373
18.5.9 ADC ordinary sequence register 1 (ADC_ OSQ1) .........................373
18.5.10 ADC ordinary sequence register 2 (ADC_ OSQ2) ......................373
18.5.11 ADC ordinary sequence register 3 (ADC_ OSQ3) ......................374
18.5.12 ADC preempted sequence register (ADC_PSQ).........................374
18.5.13 ADC preempted data register x (ADC_ PDTx) (x=1..4) ...............374
18.5.14 ADC ordinary data register (ADC_ ODT) ...................................374
18.5.15 ADC sampling time register 3 (ADC_SPT3) ...............................375
18.5.16 ADC ordinary sequence register 4 (ADC_OSQ4) .......................376
18.5.17 ADC ordinary sequence register 5 (ADC_OSQ5) .......................376
18.5.18 ADC ordinary sequence register 6 (ADC_OSQ6) .......................377
18.5.19 ADC oversampling register (ADC_OVSP)..................................377
18.5.20 ADC calibration value register (ADC_CALVAL)..........................378
18.5.21 ADC common control register (ADC_CCTRL) ............................378
19 Digital-to-analog converter (DAC) ............................................... 379
19.1 DAC introduction ....................................................................... 379
19.2 DAC main features..................................................................... 379
19.3 Design hints and tips.................................................................. 379
19.4 Functional overview ................................................................... 380
19.4.1 Trigger events............................................................................380
19.4.2 Noise/Triangular-wave generation ...............................................380
19.4.3 DAC data alignment ...................................................................382
19.5 DAC registers ............................................................................ 382

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19.5.1 DAC control register (DAC_CTRL)...............................................382
19.5.2 DAC software trigger register (DAC_SWTRG) ..............................385
19.5.3 DAC1 12-bit right-aligned data holding register (DAC_D1DTH12R)385
19.5.4 DAC1 12-bit left-aligned data holding register (DAC_D1DTH12L)..385
19.5.5 DAC1 8-bit right-aligned data holding register (DAC_D1DTH8R) ...385
19.5.6 DAC2 12-bit right-aligned data holding register (DAC_D2DTH12R)385
19.5.7 DAC2 12-bit left-aligned data holding register (DAC_D2DTH12L)..385
19.5.8 DAC2 8-bit right-aligned data holding register (DAC_D2DTH8R) ...386
19.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_DDTH12R)386
19.5.10 Dual DAC 12-bit left-aligned data holding register (DAC_DDTH12L)386
19.5.11 Dual DAC 8-bit right-aligned data holding register (DAC_DDTH8R)386
19.5.12 DAC1 data output register (DAC_D1ODT) .................................386
19.5.13 DAC2 data output register (DAC_D2ODT) .................................386
19.5.14 DAC status register (DAC_STS) ...............................................386
20 Controller area network (CAN) .................................................... 387
20.1 CAN introduction ....................................................................... 387
20.2 CAN main features..................................................................... 387
20.3 Baud rate .................................................................................. 387
20.4 Interrupt management ................................................................ 390
20.5 Design tips ................................................................................ 391
20.6 Functional overview ................................................................... 391
20.6.1 General description ....................................................................391
20.6.2 Operating modes........................................................................392
20.6.3Test modes................................................................................392
20.6.4 Message filtering........................................................................393
20.6.5 Message transmission ................................................................395
20.6.6 Message reception .....................................................................397
20.6.7 Error management......................................................................397
20.7 CAN registers ............................................................................ 398
20.7.1 CAN control and status registers.................................................400
20.7.1.1 CAN master control register (CAN_MCTRL) ............................ 400
20.7.1.2 CAN master status register (CAN_MSTS)................................ 401
20.7.1.3 CAN transmit status register (CAN_TSTS) .............................. 402
20.7.1.4 CAN receive FIFO 0 register (CAN_RF0) ................................ 406

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20.7.1.5 CAN receive FIFO 1 register (CAN_RF1) ................................ 406
20.7.1.6 CAN interrupt enable register (CAN_INTEN) ........................... 407
20.7.1.7 CAN error status register (CAN_ESTS) ................................... 409
20.7.1.8 CAN bit timing register (CAN_BTMG) ..................................... 409
20.7.2 CAN mailbox registers ................................................................410
20.7.2.1 Transmit mailbox identifier register (CAN_TMIx) (x=0..2) ......... 410
20.7.2.2 Transmit mailbox data length and time stamp register
(CAN_TMCx) (x=0..2)......................................................................... 411
20.7.2.3 Transmit mailbox data low register (CAN_TMDTLx) (x=0..2) ..... 411
20.7.2.4 Transmit mailbox data high register (CAN_TMDTHx) (x=0..2) ... 411
20.7.2.5 Receive FIFO mailbox identifier register (CAN_RFIx) (x=0..1) .. 411
20.7.2.6 Receive FIFO mailbox data length and time stamp register
(CAN_RFCx) (x=0..1) ......................................................................... 412
20.7.2.7 Receive FIFO mailbox data low register (CAN_RFDTLx) (x=0..1)412
20.7.2.8 Receive FIFO mailbox data high register (CAN_RFDTHx) (x=0..1)412
20.7.3 CAN filter registers.....................................................................412
20.7.3.1 CAN filter control register (CAN_FCTRL) ................................ 412
20.7.3.2 CAN filter mode configuration register (CAN_FMCFG) ............. 412
20.7.3.3 CAN filter bit width configuration register (CAN_ FBWCFG)...... 413
20.7.3.4 CAN filter FIFO association register (CAN_ FRF) .................... 413
20.7.3.5 CAN filter activation control register (CAN_ FACFG) ................ 413
20.7.3.6 CAN filter bank i filter bit register (CAN_ FiFBx) (i=0..13; x=1..2)413
21 Universal serial bus full-seed device interface (OTGFS)............. 414
21.1 OTGFS structure ....................................................................... 414
21.2 OTGFS functional description ..................................................... 414
21.3 OTGFS clock and pin configuration ............................................. 415
21.3.1 OTGFS clock configuration .........................................................415
21.3.2 OTGFS pin configuration ............................................................415
21.4 OTGFS interrupts ...................................................................... 416
21.5 OTGFS functional description ..................................................... 416
21.5.1 OTGFS initialization ...................................................................416
21.5.2 OTGFS FIFO configuration .........................................................417
21.5.2.1 Device mode ........................................................................ 417
21.5.2.2 Host mode............................................................................ 418
21.5.2.3 Refresh controller transmit FIFO ............................................ 419
21.5.3 OTGFS host mode......................................................................419

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21.5.3.1 Host initialization .................................................................. 419
21.5.3.2 OTGFS channel initialization.................................................. 420
21.5.3.3 Halting a channel .................................................................. 420
21.5.3.4 Queue depth......................................................................... 420
21.5.3.5 Special cases ....................................................................... 422
21.5.3.6 Host HFIR feature ................................................................. 422
21.5.3.7 Initialize bulk and control IN transfers..................................... 424
21.5.3.8 Initialize bulk and control OUT/SETUP transfers...................... 426
21.5.3.9 Initialize interrupt IN transfers................................................ 428
21.5.3.10 Initialize interrupt OUT transfers ........................................ 430
21.5.3.11 Initialize synchronous IN transfers...................................... 432
21.5.3.12 Initialize synchronous OUT transfers .................................. 433
21.5.4 OTGFS device mode ..................................................................435
21.5.4.1 Device initialization............................................................... 435
21.5.4.2 Endpoint initialization on USB reset........................................ 435
21.5.4.3 Endpoint initialization on enumeration completion.................... 436
21.5.4.4 Endpoint initialization on SetAddress command ....................... 436
21.5.4.5 Endpoint initialization on SetConfiguration/SetInterface command436
21.5.4.6 Endpoint activation ............................................................... 436
21.5.4.7 USB endpoint deactivation..................................................... 437
21.5.4.8 Control write transfers (SETUP/Data OUT/Status IN) ............... 437
21.5.4.9 Control read transfers (SETUP/Data IN/Status OUT)................ 437
21.5.4.10 Control transfers (SETUP/Status IN)................................... 438
21.5.4.11 Read FIFO packets ........................................................... 438
21.5.4.12 OUT data transfers ........................................................... 439
21.5.4.13 IN data transfers............................................................... 441
21.5.4.14 Non-periodic (bulk and control) IN data transfers................. 442
21.5.4.15 Non-synchronous OUT data transfers ................................. 443
21.5.4.16 Synchronous OUT data transfers........................................ 445
21.5.4.17 Enable synchronous endpoints........................................... 446
21.5.4.18 Incomplete synchronous OUT data transfers ....................... 448
21.5.4.19 Incomplete synchronous IN data transfers........................... 449
21.5.4.20 Periodic IN (interrupt and synchronous) data transfers......... 449
21.6 OTGFS control and status registers............................................. 451
21.6.1 CSR register map.......................................................................451
21.6.2 OTGFS register address map......................................................452
21.6.3 OTGFS global registers ..............................................................457