ARTERY AT32F421 Series User manual

AT32F421 GPIO user guide
2021.11.29 1Rev.2.0.0
www.arterytek.com
AN0069
Application Note
AT32F421 GPIO user guide
Introduction
AT32F421xx general-purpose I/Os (GPIOs) provide a wide range of interfaces to achieve digital or
analog communications between MCU and other embedded devices. Besides, AT32F421 series
GPIOs feature rich I/O multiplexed functions to enable multiple peripherals to work at the same
time, and make sure that each pin is connected to only one peripheral at a certain time so as to
avoid conflicts among peripherals.
Reference materials:
AT32F421_Firmware_Library_V2.x.x\project\at_start_f421\examples\gpio
GPIO and IOMUX section in the reference manual of AT32F421
Note: The code in this application note is based on Artery’s V2.x.x BSP (the version of board support
package). When in use, attention should be paid to the differences regarding to the versions of
BSP.
Applicable products:
MCU
AT32F421xx

AT32F421 GPIO user guide
2021.11.29 2Rev.2.0.0
www.arterytek.com
Contents
GPIO features ......................................................................................................... 5
GPIO ........................................................................................................................ 6
GPIO toggle.............................................................................................................. 8
5V-tolerant or 3V-tolerant IO..................................................................................... 8
Standard 3.3V-tolerant pins (TC).................................................................................8
5V-tolerant pin with analog function (FTa)...................................................................8
5V-tolerant pin (FT) ......................................................................................................9
IOMUX ................................................................................................................... 10
I/O multiplexed function input/output ...................................................................... 10
Special I/Os............................................................................................................12
Debug multiplexed function pin .................................................................................12
Oscillator multiplexed function pin.............................................................................12
Backup domain pin ....................................................................................................12
GPIO firmware driver API .................................................................................... 13
Output mode........................................................................................................... 13
Input mode ............................................................................................................. 13
Analog mode ..........................................................................................................14
Multiplexed function mode......................................................................................14
USART I/O multiplexed function mode configuration ...............................................15
TMR I/O multiplexed function mode configuration ....................................................15
I2C I/O multiplexed function mode configuration ......................................................16
Revision history................................................................................................... 17

AT32F421 GPIO user guide
2021.11.29 3Rev.2.0.0
www.arterytek.com
List of tables
Table 1. I/O port bit configuration table................................................................................................7
Table 2. TC pin example ......................................................................................................................8
Table 3. FTa pin example.....................................................................................................................9
Table 4. FT pin example.......................................................................................................................9
Table 5. Configure port A alternate function by GPIOA_AFR register...............................................10
Table 6. Configure port B alternate function by GPIOB_AFR register .............................................. 11
Table 7. Configure port F alternate function by GPIOF_AFR register...............................................11
Table 8. Document revision history....................................................................................................17

AT32F421 GPIO user guide
2021.11.29 4Rev.2.0.0
www.arterytek.com
List of figures
Figure 1. Basic structure of I/O port bit................................................................................................6
Figure 2. I/O toggle speed ...................................................................................................................8

AT32F421 GPIO user guide
2021.11.29 5Rev.2.0.0
www.arterytek.com
GPIO features
48-pin package (largest) has 39 multi-function bidirectional I/O ports
All I/O ports can be mapped to 16 external interrupt vectors
Almost all I/O ports are 5V tolerant (except for 4x OSC/OSC32 pins)
All fast IIOs, control registers accessible with fAHB speed
The peripheral function of the I/O pin can be locked through a specific operation to avoid
unwanted writing to I/O registers
Each GPIO pin can be individually configured by software as output (push-pull or open-drain),
input (with or without pull-up or pull-down) or a multiplexed function peripheral port
Optional current sourcing/sinking strength
Port bit set/clear register (GPIOx_BSRE) and port bit clear register (GPIOx_BRE) provide bit
access ability for the GPIOx_OPTDT register

AT32F421 GPIO user guide
2021.11.29 6Rev.2.0.0
www.arterytek.com
GPIO
During and just after reset, the multiplexed functions of GPIOs are not active, and most I/O ports
are configured in input floating mode.
When configured as output, the value written to the output data register (GPIOx_OPTDT) is output
on the I/O pin. It is possible to use the output driver in push-pull mode or open-drain mode (only low
level is activated while the high level shows high impedance)
The input data register (GPIOx_IPTDT) captures the data present on the I/O pin at every AHB clock
cycle.
All GPIO pins have an internal weak pull-up and weak pull-down, which can be activated or not,
depending on the value of the GPIOx_PUPDR register.
Figure 1. Basic structure of GPIO
IO
ESD
protect
SMT trigger
PU
PD
output data
output enable
input enable
input data
push/pull
strength control
analog input/output
AHB bus
GPIO controller
Single IO
Analog
module

AT32F421 GPIO user guide
2021.11.29 7Rev.2.0.0
www.arterytek.com
Table 1. I/O port bit configuration table
CFGR[1：0]
OMODE
ODRVR[1：0]
PULL[1：0]
I/O configuration
01
0
ODRV[1：0]
0
0
GP output
PP
0
0
1
GP output
PP
0
1
0
GP output
PP
0
1
1
Reserved
1
0
0
GP output
OD
1
0
1
GP output
OD
1
1
0
GP output
OD
1
1
1
Reserved (GP output OD)
10
0
0
0
AF output
PP
0
0
1
AF output
PP
0
1
0
AF output
PP
0
1
1
Reserved
1
0
0
AF output
OD
1
0
1
AF output
OD
1
1
0
AF output
OD
1
1
1
Reserved
00
x
x
x
0
0
Input
Floating
x
x
x
0
1
Input
PU
x
x
x
1
0
Input
PD
x
x
x
1
1
Reserved (floating input)
11
x
x
x
0
0
Input/output
Analog
x
x
x
0
1
Reserved
x
x
x
1
0
x
x
x
1
1

AT32F421 GPIO user guide
2021.11.29 8Rev.2.0.0
www.arterytek.com
GPIO toggle
All I/O ports of AT32F421 series are fast I/Os with control registers accessible at fAHB speed so that
the GPIO toggle frequency can reach 60 MHz with ease.
Figure 2. I/O toggle speed
5V-tolerant or 3V-tolerant IO
Standard 3.3V-tolerant pins (TC)
All oscillators use standard 3.3V-tolerant pins.
PC14/PC15 (OSC32_IN/ OUT)
PF0/PF1 (OSC_IN/ OUT)
Table 2. TC pin example
Pin name
Pin name
IO structure
Multiplexed function
Additional function
PF0/OSC_IN(PF0)
I/O
TC
I2C1_SDA
OSC_IN
5V-tolerant pin with analog function (FTa)
The ports occupied by comparator input pins and ADC are 5V-tolerant pins with analog function.
PA0 –PA7
PB0 –PB2, PB12 –PB15
When configured as input floating, input pull-up or input pull-down, FTa pins are 5V tolerant;
when configured in analog mode, they are not 5V-tolerant, and input level must be less than
VDD + 0.3V at this time.

AT32F421 GPIO user guide
2021.11.29 9Rev.2.0.0
www.arterytek.com
Table 3. FTa pin example
Pin name
Pin name
IO structure
Multiplexed function
Additional function
PA0
I/O
FTa
TMR1_ETR /
USART2_CTS
/I2C2_SCL /
COMP_OUT
ADC_IN0COMP_INP2
/ COMP_INM6 /
WKUP1
5V-tolerant pin (FT)
Other GPIOs are all 5V tolerant.
Table 4. FT pin example
Pin name
Pin name
IO structure
Multiplexed function
Additiona
l function
PA8
I/O
FT
TMR1_CH1 / USART1_CK /
UART2_TX / I2C2_SCL /
CLKOUT / EVENTOUT
-

AT32F421 GPIO user guide
2021.11.29 10 Rev.2.0.0
www.arterytek.com
IOMUX
I/O multiplexed function input/output
Most peripherals share the same GPIO pin (For example, PA0 can be used as TMR1_ETR /
USART2_CTS /I2C2_SCL / COMP_OUT)
A GPIO pin is connected to only one peripheral at any time.
Some peripheral functions can also be remapped to other pins so as to get more peripherals
that can be used at the same time
Selecting one of the active multiplexed functions on each port line is determined by GPIOx_MUXL
or GPIOx_MUXH multiplexed function register. The user can use these two registers to connect
multiplexed function module to other pins according to the application requirements.
Table 5. Configure port A multiplexed function by GPIOA_MUX register
Pin
name
MUX0
MUX1
MUX2
MUX3
MUX4
MUX5
MUX6
MUX7
PA0
USART2_CTS
I2C2_SCL
TMR1_ETR
COMP_OUT
PA1
EVENTOUT
USART2_RTS
I2C2_SDA
TMR15_CH1
N
PA2
TMR15_CH1
USART2_TX
PA3
TMR15_CH2
USART2_RX
I2S2_MCLK
PA4
SPI1_NSS/I2S1_
WS
USART2_CK
TMR14_CH1
PA5
SPI1_SCK/I2S1_
CK
PA6
SPI1_MISO/I2S1
_MCLK
TMR3_CH1
TMR1_BKIN
I2S2_MCLK
TMR16_CH1
EVENTOUT
COMP_OUT
PA7
SPI1_MOSI/I2S1
_SD
TMR3_CH2
TMR1_CH1N
TMR14_CH1
TMR17_CH1
EVENTOUT
PA8
CLKOUT
USART1_CK
TMR1_CH1
EVENTOUT
USART2_TX
I2C2_SCL
PA9
TMR15_BKIN
USART1_TX
TMR1_CH2
I2C1_SCL
CLKOUT
I2C2_SMBA
PA10
TMR17_BKIN
USART1_RX
TMR1_CH3
I2C1_SDA
PA11
EVENTOUT
USART1_CTS
TMR1_CH4
I2C1_SMBA
I2C2_SCL
COMP_OUT
PA12
EVENTOUT
USART1_RTS
TMR1_ETR
I2C2_SDA
PA13
SWDIO
IR_OUT
SPI2_MISO/I
2S2_MCLK
PA14
SWCLK
USART2_TX
SPI2_MOSI/I
2S2_SD
PA15
SPI1_NSS/I2S1_
WS
USART2_RX
EVENTOUT
SPI2_NSS/I
2S2_WS