ARTERY AT32F423 Series User manual

Getting-started guide for AT32F423
2023.03.20 1Ver 2.0.0
AN0165
Application Note
Getting-started guide for AT32F423
Introduction
This document is aimed at helping users with a quick start of developing application solutions
based on AT32F423 MCU.
Note: The codes in this document are built around ARTERY’s V2.x.x BSP. Attention should be paid to the
differences between different versions of BSP when in use.
Applicable products：
Product series
AT32F423xx

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Contents
Development resources ........................................................................................ 5
Set up AT32 development environment ....................................................................5
Debug tools and evaluation board ...............................................................................5
Programming tools and software resources ................................................................6
AT32 development environment ..................................................................................6
How to quickly replace AT32F415 with AT32F423.....................................................12
AT32F423 functionality enhancement.....................................................................12
Instruction prefetch buffer ..........................................................................................12
PLL clock settings ......................................................................................................13
Encryption...................................................................................................................14
Set system memory as main memory extension.......................................................17
How to distinguish AT32 MCU from other MCUs.......................................................21
Frequently-asked questions for download and compiling.............................. 22
Program enters Hard Fault Handler........................................................................ 22
Jlink unable to recognize IC in Keil project .............................................................22
Possible questions occurred during download........................................................ 22
Flash Download failed–“Cortex-M4”..........................................................................22
No Debug Unit Device found......................................................................................23
RDDI-DAP Error.........................................................................................................23
ISP serial interface gets stuck during download........................................................23
How to resume program download............................................................................23
sLib (Security Library)......................................................................................... 24
Introduction.............................................................................................................24
Application principles.............................................................................................. 24
How to use sLib...................................................................................................... 24
Revision history................................................................................................... 25

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List of tables
Table 1. Document revision history....................................................................................................25

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List of figures
Figure 1. AT-START-F423 and AT-Link-EZ........................................................................................5
Figure 2. AT-START-F423 evaluation board package from ARTERY official website.........................5
Figure 3. ICP/ISP/AT-Link-Family package from ARTERY official website.........................................6
Figure 4. BSP resources from ARTERY official website .....................................................................6
Figure 5. Keil_v5 template ...................................................................................................................7
Figure 6. Pack resources from ARTERY official website ....................................................................8
Figure 7. Install ArteryTek.AT32F423_DFP .........................................................................................8
Figure 8. Install Keil4_AT32MCU_AddOn ...........................................................................................8
Figure 9. Click “Pack Installer” icon in Keil ..........................................................................................9
Figure 10. Install IAR_AT32MCU_AddOn ...........................................................................................9
Figure 11. Keil Debug option .............................................................................................................10
Figure 12. Settings option in Keil Debug ...........................................................................................10
Figure 13. Keil Utilities option ............................................................................................................10
Figure 14. IAR Debug option ............................................................................................................. 11
Figure 15. IAR CMSIS-DAP option....................................................................................................11
Figure 16. Wait state bit in FLASH_PSR register..............................................................................12
Figure 17. system_clock_config function...........................................................................................12
Figure 18. AT32F423 150MHz output clock configuration ................................................................13
Figure 19. AT32 PLL auto step-by-step frequency switch configuration example ............................13
Figure 20. Use ISP tool to enable or disable access protection........................................................14
Figure 21. Use ISP to enable access protection ...............................................................................15
Figure 22. Use ISP to unlock access protection................................................................................15
Figure 23. Use ICP tool to enable erase/write protection..................................................................16
Figure 24. Use ICP tool to disable erase/write protection .................................................................17
Figure 25. Use ICP tool to set boot memory AP mode......................................................................18
Figure 26. Boot memory AP mode operating progress .....................................................................18
Figure 27. Use ICP tool to set offline boot mode AP mode...............................................................19
Figure 28. Use ICP tool to set offline project programming ..............................................................20
Figure 29. ICP tool to monitor offline download status......................................................................20
Figure 30. Read Cortex ID.................................................................................................................21
Figure 31. Read UID,PID...................................................................................................................21
Figure 32. Flash Download failed–“Cortex- M4” during download....................................................22

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Development resources
Resources download link:
Visit Artery website: http://www.arterychip.com
Set up AT32 development environment
Debug tools and evaluation board
The AT-START-AT32F423 evaluation board comes with AT-Link-EZ for the debug purpose. The
picture of AT-Link-EZ is marked with red rectangle in Figure 1 below. It can also be separated from
the board and works with other circuit boards. The debug tool can be used for several purposes such
as IDE online debugging and programming, as well as USB-to-serial interface.
Figure 1. AT-START-F423 and AT-Link-EZ
Note: For details on AT-START-AT32F423 evaluation board, refer to the “UM_AT_START_F423_Vx.x”that is
available from ARTERY’s official website. You can go to ARTERY official website → PRODUCT → Value line
→ AT32F423 series → Resources → Evaluation board, where you can download a ZIP-format AT-START-
F423 and get AT_START_F423_Vx.x\03_Documents.
Figure 2. AT-START-F423 evaluation board package from ARTERY official website

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Programming tools and software resources
ATERTY programming tools and software: AT-Link /AT-Link+ /AT-Link-Pro /AT-Link-IS
O /AT-Link-EZ, and ICP/ISP
ICP user guide: Refer to the “UM_ICP_Programmer”, which is stored at ARTERY official
website → Product → Value line → AT32F4xx → Tool → download ICP document
ISP user guide: Refer to the UM_ISP_Programmer, which is stored at ARTERY official
website → Product → Value line → AT32F4xx → Tool → download ISP document
AT-Link user guide: Refer to the “UM0004_AT-Link_User_Manual”, which is stored at
ARTERY official website → Product → Value line → AT32F4xx → Tool → download AT-Link
document.
Figure 3. ICP/ISP/AT-Link-Family package from ARTERY official website
AT32 development environment
Template project
The frequently-used IDE template projects are included in ARTERY’s firmware BSP. You can get
these resources by visiting ARTERY official website → Product → Value line → AT32F423 series
→ BSP.
Figure 4. BSP resources from ARTERY official website
BPS offers such template projects as at32_ide/eclipse_gcc/Keil_v5/Keil_v4/IAR_6.10/IAR_7.4/
IAR_8.2/IAR_9.3, which are stored at AT32F423_Firmware_Library_V2.x.x\project\at_start_f4x
x\templates.
Just simply open the desired folder and IDE project. Figure 5 below shows an example of
Keil_v5 project.

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Figure 5. Keil_v5 template
Taking Keil_v5 template as an example, it mainly contains the following items:
①at32F423_clock.c: it is a clock configuration file defining the default clock frequency and
clock path
②at32F423_int.c: it refers to an interrupt file that contains the default process of handling
some core interrupts
③main.c: it refers to the main code file
④at32F423_board.c: it refers to the board configuration file that defines common hardware
such as buttons and LEDs on AT-START evaluation board
⑤firmware: it contains “at32F423_xx.c” that is used as a driver file for peripherals
⑥system_at32F423.c: system initialization file
⑦startup_at32F423.s: a startup file
⑧readme.txt: a read-me txt file that describes some application functions, configuration
method and application notes relating to a template project.
In addition to “Templates”, a large number of examples are included in BSP for users’ reference.
These example codes are stored at AT32F423_Firmware_Library_V2.x.x \ project \at_start_f4xx
\examples.
Note: For details on BSP, refer to Section 4 of the document “AT32F423_firmware_BSP&Pack_user_guide”.
This guideline is available from ARTERY official website → Product → Value line → AT32F423 series → BSP.

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Pack installation
The installation of Pack is required to add AT32 MCU part number in Keil/IAR.
This Pack can be downloaded from ARTERY official website → Product → Value line → AT32F423
series → Pack.
Figure 6. Pack resources from ARTERY official website
Regarding the Keil compiling system, the keil 4.74 or above V5.23 is recommended.
For Kei_v5 system, users need first unzip “Keil5_AT32MCU_AddOn” and then install the
“ArteryTek.AT32F423_DFP”.
For Keil_v4 system, users directly install “Keil4_AT32MCU_AddOn”.
By default, the installation path of Keil can be automatically recognized when installing. In case of
recognition failure, it is necessary for users to manually choose an installation path for Keil.
Figure 7. Install ArteryTek.AT32F423_DFP
Figure 8. Install Keil4_AT32MCU_AddOn

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Additionally, you can also open Keil, click the icon “Pack Installer”, then click “File”, and choose
“Import” to import and install “Pack”you download from ARTERTY official website.
Figure 9. Click “Pack Installer” icon in Keil
If IAR compiling system is to be used, its IAR7.0 or IAR6.1 above versions are recommended. While
installing the “IAR_AT32MCU_AddOn”, the installation path of Keil can be automatically recognized.
In case of recognition failure, it is necessary for users to manually choose an installation path for
IAR.
Figure 10. Install IAR_AT32MCU_AddOn
Note: For details on Pack, refer to Section 2 of the document “AT32F423_firmware_BSP&Pack_user_guide”.
This guideline is available from ARTERY official website → Product → Value line → AT32F423 series → BSP,
and download BSP zip file and view the AT32F423_Firmware_Library_Vx.x.x\document into it.
Debug and download with AT-Link tool
If AT-Link is to beused in Keil environment, click “Debug”, and then choose “CMSIS-DAP Debugger”.

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Figure 11. Keil Debug option
Next, click “Settings” to enter “Cortex-M Target Driver Setup” window, as shown in Figure 12 below.
1. Choose “AT-Link(WinUSB)-CMSIS-DAP/AT-Link-CMSIS-DAP”
Note: For more information on WinUSB, refer to “FAQ0136_How_to_use_AT-LINK_WinUSB_EN_V2.0.0”.
This FAQ is stored at ARTERY official website → Support → FAQ → FAQ0136.
2. In “Port”option, choose “SW”, and then check “SWJ”option
3. As shown in step 3 below, the ARM SW-DP debug module is already recognized.
Figure 12. Settings option in Keil Debug
In “Utilities”option, first de-check “Use Debug Driver” (see step 1), then choose “CMSIS-DAP
Debugger” in Step 2, and finally re-check Step 1 option (noted that this step 1 must be first de-
checked before being checked again later)
Figure 13. Keil Utilities option

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If AT-Link is to be used in IAR environment, click “Project”, choose “Options”, go to “Debugger” and
choose “CMSIS-DAP”, and then check “SWD”option.
Figure 14. IAR Debug option
Figure 15. IAR CMSIS-DAP option
Note: The document AT32F423_firmware_BSP&Pack_user_guide provides details on Flash algorithm, MCU
product series replacement and J-Link. Thus they are not repeated hereof. This document is located at ARTERY
official website → Product → Value line → AT32F423 series → BSP.

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How to quickly replace AT32F415 with AT32F423
This migration guide from AT32F415 to AT32F423 is detailed in the document
“MG0023_Migrating_from_AT32F415_to_AT32F423_V2.0.0”, which is stored at ARTERY
official website → Product → Value line → AT32F423 series page
If program failure occurs, please refer to the corresponding sections of this document, or you
can contact your local or nearest ARTERY Tech team for assistance.
Note: For more information on how to get better AT32F423 operating performance, please refer to the
application note “AN0004_Performance_Optimization”. You can read or download this file by visiting
ARTERY official website → Product → AP Note → AN0004.
AT32F423 functionality enhancement
Instruction prefetch buffer
Instruction prefetch buffer is very useful for achieving quicker CPU execution speed. After
instruction prefetch buffer is enabled, the subsequent word is already awaiting in the buffer while
CPU is reading the existing word. The instruction prefetch controller will then determine whether or
not to access Flash memory according to available space in the buffer. Once there is at least a free
space in the instruction prefetch buffer, then the instruction prefetch controller will trigger a read
access.
Different system clocks require different wait states, which can be set through the bit [2:0] (WTCYC)
in the FLASH_PSR register.
Figure 16. Wait state bit in FLASH_PSR register
AT32 library has made relevant settings in the system_clock_config() function. For BSP of other
AT32 MCU series, you can also find this settings at the same location.
Figure 17. system_clock_config function

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PLL clock settings
PLL settings
AT32F423 embeds a PLL with a maximum of 150MHz clock output. The CRM_PLLCFG register
(PLL clock configuration register) can be used to configure different PLL clock frequencies, with the
following formula:
            
      

In AT32 BSP, example of PLL settings is based on HEXT=8MHz, PLL=150MHz.
Figure 18. AT32F423 150MHz output clock configuration
/* config pll clock resource PLL_FR =4*/
crm_pll_config(CRM_PLL_SOURCE_HEXT, 150, 1, CRM_PLL_FR_4);
Where, the first parameter “CRM_PLL_SOURCE_HEXT” represents that HEXT is used as an
external clock source, PLL_NS is 150, PLL_MS is 1, and PLL_FR value is CRM_PLL_FR_4 (0x02,
divided by 4)
For more information on clock configurations, please refer to the document
“AN0158_AT32F423_CRM_Start_Guide”. This user guide can be downloaded from ATERTY
official website → Support → AN Note → AN0158. With this file, you can learn more about how to
configure and modify AT32F423 clock source code, and how to use ARTERY’s New Clock
Configuration tool to quickly generate the desired clock code and apply it to project.
The New Clock Configuration document is stored at ATERTY official website → Product → Value
line → AT32F423 series → Tool.
PLL automatic frequency switch feature
When the PLL multiplication frequency of AT32F423 series is greater than 108MHz, it is
recommended to enable PLL auto step-by-step frequency switch feature.
Figure 19 gives an example of PLL auto frequency switching function in AT32F423 BSP.
Figure 19. AT32 PLL auto step-by-step frequency switch configuration example
/* enable auto step mode */
crm_auto_step_mode_enable(TRUE);
/* select pll as system clock source */
crm_sysclk_switch(CRM_SCLK_PLL);
/* wait till pll is used as system clock source */
while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL)
{
}
/* disable auto step mode */
crm_auto_step_mode_enable(FALSE);
/* update system_core_clock global variable */
system_core_clock_update();

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Note: If this auto frequency switching function is enabled, it should be disabled right after the completion ofclock
switching operation. In other words, enabling and disabling must be operated in pair.
Encryption
Note: The BOOT1 bit of AT32F423 series is located in the user system data area (0x1FFF F800). When ISP
tool is used, it is mandatory to ensure that nBOOT1=1 is asserted (default value) so that the program is
booted from system memory instead of SRAM.
Access protection
Access protection is usually known as an encryption operation. It applies to the entire Flash
memory. Once the access protection is enabled, the embedded Flash memory can only be read out
through conducting normal program execution, rather than through JTAG or SWD.
Using ISP or ICP tool to unlock access protection will trigger erase operation to the Flash memory.
Note: Once enabled, high-level access protection can not be unlocked. Meanwhile, it is forbidden for
users to erase and write system area in any forms.
ISP or ISP tool can be used to enable and disable access protection.
Artery ICP Programmer (BOOT0=0)
Enable access protection: click Target –Access protection –Enable access protection or enable
high-level access protection. (See Figure 20 below)
Unlock access protection: click Target –Access protection –disable
Figure 20. Use ISP tool to enable or disable access protection
Artery ISP Programmer tool (BOOT0=1)
Enable access protection: Keep clicking “Next” until you enter the final interface. Then check
“Protection”, choose “Enable” and “Access protection”, click “Yes”. See figure 21 below.
Unlock access protection: check “Protection”, choose “Disable” and “Access protection”, click
“Yes”.
Artery ISP Multi-Port Programmer tool (BOOT0=1)
Enable access protection: check “Protection”, choose “Enable” and “Access protection” or “High-
level access protection”, click “Start”.
Unlock access protection: check “Protection”, choose “Disable” and “Access protection”, click
“Start”.

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Figure 21. Use ISP to enable access protection
Figure 22. Use ISP to unlock access protection
Note: Access protection, after enabled, cannot be unlocked through erase operation.

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Erase/write protection
Write protection applies to the entire Flash memory or to part of Flash area. Once Flash write
protection is enabled, the embedded Flash memory are write-protected against any writing operation.
ISP or ICP tool can be used to enable or disable erase/write protection based on procedure below.
Artery ICP Programmer tool (BOOT0=0)
Enable erase/write protection: click “Target” – User system area –choose the sectors to be
erase/write-protected –apply to device
Disable erase/write protection: click “Target” – User system area –cancel the sectors
to be erase/write-protected –apply to device
Artery ISP Programmer tool (BOOT0=1)
Enable erase/write protection: check “Protection” option, choose “Enable” and “Erase/write
protection”, and then click “Yes”
Disable erase/write protection: check “Protection” option, choose “Disable” and “Erase/
write protection”, and then click “Yes”
Artery ISP Multi-Port Programmer tool (BOOT0=1)
Enable erase/write protection: check “Protection” option, choose “Enable” and “Erase/write
protection”, and then click “Yes”
Disable erase/write protection: check “Protection” option, choose “Disable” and “Erase/
write protection”, and then click “Yes”
Figure 23. Use ICP tool to enable erase/write protection

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Figure 24. Use ICP tool to disable erase/write protection
Note: Erase/write protection, after enabled, cannot be unlocked through erase operation.
Set system memory as main memory extension
System memory is used as a boot mode by default to store microcontroller manufacturer’ Startup
Code. On top of this, in AT32F423 series, a new feature is added to the system memory by using it
to store user-defined codes as an extended memory area (AP mode).
Note: System memory AP mode is irreversible and can only be used once, meaning that after AP
mode is selected, its original BOOT mode cannot be resumed.
During product development stage, we can use Artery ICP Programmer to enable system memory
as an extended memory according to the following procedures.
Connect AT-Link or J-Link to AT-START-F423 evaluation board and supply power to it
Open Artery ICP programmer, choose AT-Link/J-Link connection
Go to menu bar: Target –Boot memory AP mode -- OK

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Figure 25. Use ICP tool to set boot memory AP mode
To prevent unexpected wrong operations, you need manually enter the passkey “0xA35F6D24”,
then you can check whether the operation is successful or not in “File info” column.
Figure 26. Boot memory AP mode operating progress
During mass-production stage, we can also use Artery ICP Programmer to enable system memory
as memory extension area according to the following procedures:
Connect AT-Link to AT-START-F423 evaluation board and supply power to it
Note:Theeditionof AT-LinkEZ onboardtheAT-START-F423does not supportofflineprogramming.Asaresult,
you can only use non-EZ AT-Link.
Open Artery ICP programmer, and choose AT-Link connection

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Go to menu bar: AT-Link setting -- AT-Link offline configuration setting
Follow the steps below to generate off-line project
1. Click “Create”
2. Enter a project name
3. Select a particular MCU series and MCU part number
4. Add.hex files
5. Choose SWD as download interface
6. Check “Boot mode AP mode” option and enter the passkey
7. Save project file or save project to AT-Link
In addition to above settings, you can also make other configurations according to the actual needs.
Figure 27. Use ICP tool to set offline boot mode AP mode
In Step 7, if you choose “Save project file”, this project will be saved as .atcp file so that it can
be loaded onto other AT-Link.
The following dialogue window will pop out during actual operation. If “This project is only used
at the specified AT-Link” option checked, it means that this project is bonded to a particular AT-
Link and can only be used in this AT-Link. In this case, you need to enter AT-Link serial
number which will be bonded to.
If “This project is only used once” option is checked, it means that this project could onlybe used
once in the same AT-Link.

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Figure 28. Use ICP tool to set offline project programming
In step 7, if you choose “Save project to AT-Link” and operation is successful, in “AT-Link offline
download status” option, you need to choose a project name for offline download, click “Save
and activate”, and click “Start download”.
Figure 29. ICP tool to monitor offline download status
For more information on system memory extension, please refer to the document
“AN0066_config_boot_memory_as_extension_of_main_memory(AP_mode)”, which is stored
at ARTERY official website → Support → AP Note → AN0066.
For DEMO on running user program in the system memory, please refer to BSP, which is
stored at ARTERY official website → Product → Value line → AT32F423 series → BSP.
After unzipping BSP file, you can get demo under
AT32F423_Firmware_Library_V2.x.x\utilities\at32F423_boot_memory_ap_demo.