ARTERY AT32F403A Series User manual

Getting Started with AT32F403A & AT32F407
2022.10.21 1 Ver 2.0.3
AN0023
Application Note
Getting Started with AT32F403A & AT32F407
Introduction
This application note is written to help users with rapid project development using AT32F403Axx
/AT32F407xx (compared with AT32F403A, AT32F407 is featured with Ethernet media access
control (EMAC) additionally).
Note: The corresponding code in this application note is developed on the basis of V2.x.x BSP provided by
Artery. For other versions of BSP, please pay attention to the differences in usage.
Applicable products:
Part number
AT32F403Axx
AT32F407xx

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2022.10.21 2 Ver 2.0.3
Contents
1Preliminary environment requirements...........................................................6
1.1 Build AT32 development environment.............................................................................6
1.1.1 Debug toolsand evaluation board............................................................................6
1.1.2 Programming tools and software..............................................................................6
1.1.3 AT32 development environment...............................................................................7
1.1.4 How to replace SXX...............................................................................................12
1.2 AT32F403A/AT32F407 chip enhanced functions ........................................................13
1.2.1 PLL clock settings..................................................................................................13
1.2.2 Howto enable FPUfunction...................................................................................15
1.2.3 AT32F403A /AT32F407 zero-wait/non-zero-wait Flash and embedded SRAM
configurations....................................................................................................................17
1.2.4 Encryption mode (access protection /erase and program protection /external Flash
encryption).........................................................................................................................22
1.2.5 Recognize AT32 MCUin program..........................................................................26
2FAQs in downloading/compiling...................................................................28
2.1 Hard Fault Handler..........................................................................................................28
2.2 J-Link cannot find IC .......................................................................................................28
2.3 Problems in program downloading................................................................................28
2.3.1 Error: Flash Download failed–“Cortex-M4” .............................................................28
2.3.2 No Debug Unit Device found..................................................................................29
2.3.3 RDDI-DAP Error.....................................................................................................29
2.3.4 ISP serial port gets stuck in downloading...............................................................29
2.3.5 Resume download.................................................................................................29
3Security Library (sLib) .................................................................................. 32
3.1 Introduction......................................................................................................................32
3.2 Principles of application..................................................................................................32
3.3 Security library application .............................................................................................33
4Revision history............................................................................................34

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List of Tables
Table 1. Document revision history............................................................................................... 34

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List of Figures
Figure 1. AT-START-F407 evaluation board with AT-Link-EZ........................................................... 6
Figure 2. AT-START-F407 evaluation board package...................................................................... 6
Figure 3. ICP/ISP/AT-Link-Family.................................................................................................... 7
Figure 4. BSP package................................................................................................................... 7
Figure 5. Keil_v5 templates............................................................................................................ 8
Figure 6. Pack download................................................................................................................ 9
Figure 7. Set up ArteryTek.AT32F403A_407_DFP.......................................................................... 9
Figure 8. Set up Keil4_AT32MCU_AddOn ...................................................................................... 9
Figure 9. Pack Installer icon in Keil............................................................................................... 10
Figure 10. Set up IAR_AT32MCU_AddOn .................................................................................... 10
Figure 11. Keil Debug option..........................................................................................................11
Figure 12. Keil Debug Settings......................................................................................................11
Figure 13. Keil Utilities...................................................................................................................11
Figure 14. IAR Debug option ........................................................................................................ 12
Figure 15. IAR CMSIS-DAP option ............................................................................................... 12
Figure 16. Use SXX to output 240 MHzclock on AT32F403A/AT32F407 ..................................... 13
Figure 17. AT32F403A /AT32F407 crm_pll_output_range parameter ............................................ 13
Figure 18. New Clock Configuration.............................................................................................. 14
Figure 19. SXXPLL auto step-by-step switch configurations......................................................... 14
Figure 20. AT32 PLL auto step-by-step switch configurations........................................................ 15
Figure 21. Enable FPUin Keil....................................................................................................... 15
Figure 22. Add FPUenabling codes in Keil................................................................................... 16
Figure 23. Enable FPUin IAR....................................................................................................... 16
Figure 24. Add FPUenabling codes in IAR................................................................................... 16
Figure 25. User system data in ICP Programmer.......................................................................... 17
Figure 26. Select SRAM size in user system data......................................................................... 18
Figure 27. Edit user system data in ISP Programmer.................................................................... 18
Figure 28. User system data setting in ISP Multi-Port Programmer............................................... 19
Figure 29. Define Extend_SRAM(void) function in SXXprogram .................................................. 19
Figure 30. Define Extend_SRAM(void) function in AT32 program ................................................. 20
Figure 31. Modify SRAM size in Keil startup file............................................................................ 20
Figure 32. Modify SRAM size in IAR startup file............................................................................ 21
Figure 33. Enable access protection in ISP Programmer .............................................................. 22

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Figure 34. Disable access protection in ISP Programmer.............................................................. 23
Figure 35. Enable erase and program protection in ICP Programmer ........................................... 24
Figure 36. Disable erase and program protection in ICP Programmer........................................... 24
Figure 37. Encrypt external memory in ICP Programmer .............................................................. 26
Figure 38. Encrypt external memory in ISP Programmer............................................................... 26
Figure 39. Read Cortex ID............................................................................................................ 27
Figure 40. Read PID and UID ....................................................................................................... 27
Figure 41. Add FPUenabling codes.............................................................................................. 28
Figure 42. Flash Download failed–“Cortex- M4” pops up in downloading ...................................... 29
Figure 43. Operate ConfigJLink_V1.0.0 in KEIL............................................................................ 30
Figure 44. ConfigJLink_V1.0.0 execution progress in KEIL ........................................................... 31
Figure 45. Operate ConfigJLink_V1.0.0 in IAR.............................................................................. 31
Figure 46. ConfigJLink_V1.0.0 execution progress in IAR............................................................. 32

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1 Preliminary environment requirements
Download development environment
ARTERY's official website
1.1 Build AT32 development environment
1.1.1 Debug tools and evaluation board
The AT32F403A /AT32F407 evaluation board has an AT-Link-EZ debug tool, as shown in the red
box in Figure 1 below. The AT-Link-EZ can be disassembled and used with other circuit boards,
supporting IDE online debugging, online programming and USB-to-serial port.
Figure 1. AT-START-F407 evaluation board with AT-Link-EZ
Note: For details about resources for AT-START evaluation board, please refer to
UM_AT_START_F40x_Vx.x. Path: ARTERY’s official website→PRODUCTS→Mainstream→AT32F4xx;
download and unzip Evaluation Board package, and get the “\AT_START_F40x_Vx.x\03_Documents”.
Figure 2. AT-START-F407 evaluation board package
1.1.2 Programming tools and software
AT programming tools and software: AT-Link / AT-Link+ /AT-Link-Pro / AT-Link-ISO /AT-Link-
EZ, ICP/ISP.
7-12V externalpower socket
Boot mode select(BOOT jumper cap)
20-pin ARM
Standard
JTAG port
AT-Linkport
RESET button
USER button
SPIM jumper cap
ArduinoUno extendport
USB port
I/O extendport
USART1 port
DM9162
Ethernet PHY
User LED*3

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3rd party programming tools: J-Link, Armfly, Alientek, XWOPEN, ICWORKSHOP, ZLG,
MaxWiz, Amomcu, Acroview, Forcreat, Galecomm, Prosystems, Rx-prog, Sinaen, XELTEK,
Zhifeng, etc.
Note: For more information, please visit ARTERY’s official website→SUPPORT→Hardware Development
Tool and 3RD Party Writer.
For ICP usage instructions, please refer to UM_ICP_Programmer. Path: ARTERY’s official
website→PRODUCTS→Mainstream→AT32F4xx; download and unzip ICP tool, and get the
“Artery_ICP_Programmer_Vx.x.xx\Document\UM_ICP_Programmer.
For ISP usage instructions, please refer to UM_ISP_Programmer. Path: ARTERY’s official
website→PRODUCTS→Mainstream→AT32F4xx; download and unzip ISP tool, and get the
“Artery_ISP_Programmer_Vx.x.xx\Document\UM_ISP_Programmer.
ForAT-Link usage instructions, please refer to UM0004_AT-Link_User_Manual.
Path: ARTERY’s official website→PRODUCTS→Mainstream→AT32F4xx; download and
unzip AT-Link-Family, and get the “AT_Link_CH_ Vx.x.x\05_Documents\UM0004_AT-
Link_User_Manual_ZH_Vx.x.x”.
Figure 3. ICP/ISP/AT-Link-Family
1.1.3 AT32 development environment
1.1.3.1 Templateprojects
The commonly used IDE template projects are available from BSP provided by ArteryTek. BSP
path: ARTERY’s official website→PRODUCTS→Mainstream→AT32F4xx.
Figure 4. BSP package
ForAT32F403A/407 series, template projects of
Keil_v5/Keil_v4/IAR_6.10/IAR_7.4/IAR_8.2/eclipse_gcc/at32_ide are created in BSP. Path:

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AT32F403A_407_Firmware_Library_V2.x.x\project\at_start_f4xx\templates. Open the project
folder and click on the project file to open the corresponding IDE project. The example of Keil_v5
template project is shown below.
Figure 5. Keil_v5 templates
Contents in the project:
①at32f403a_407_clock.c: clock configuration file, contains default clock frequency and
clock path;
②at32f403a_407_int.c: interrupt file, part of core interrupt function code flow is written by
default;
③main.c: main code file of the template project;
④at32f403a_407_board.c: board-level configuration file, contains settings ofAT-START
on-board buttons and LEDs;
⑤at32f403a_407_xx.c under firmware: driver file of on-chip peripherals;
⑥system_at32f403a_407.c: systeminitialization file;
⑦startup_at32f403a_407.s: startup file;
⑧readme.txt: project documentation, contains application functions, setting methods and
associated application notes (ApNote) of the template project.
Except for templates, BSP also includes code examples (Keil_v5 project files) in terms of
peripherals for reference.
Path: AT32F403A_407_Firmware_Library_V2.x.x\project\at_start_f4xx\examples.
Note: For more details about BSP, please refer to “Section 4 BSP application” of AT32F403A_407 Firmware
BSP&Pack User Guide. Path: ARTERY’s official website→PRODUCTS→Mainstream→AT32F4xx; download
and unzip BSP, and get the “\AT32F403A_407_Firmware_Library_Vx.x.x\document”.
1.1.3.2 Packinstallation
Install Pack and add the AT32 MCU part number to Keil/IAR. You can download Pack from
ARTERY’s official website→PRODUCTS→Mainstream→AT32F4xx.

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Figure 6. Pack download
For Keil compiling system, keil 4.74 /5.23 or above is recommended. If Keil_v5 is used, please
unzip Keil5_AT32MCU_AddOn and install the corresponding ArteryTek.AT32F403A_407_DFP. If
Keil_v4 is used, please install Keil4_AT32MCU_AddOn. By default, the Keil installation path can
be recognized automatically during installation. If the path is not recognized or incorrect, you need
to manually select the Keil installation path.
Figure 7. Set up ArteryTek.AT32F403A_407_DFP
Figure 8. Set up Keil4_AT32MCU_AddOn
You can also open keil and click on “Pack Installer” icon; then click on the top left “file” and select
“import” to import the corresponding pack downloaded from ARTERY's official website.

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Figure 9. Pack Installer icon in Keil
For IAR compiling system, IAR7.0 or IAR6.1 above is recommended. It is necessary to install
IAR_AT32MCU_AddOn. By default, the IAR installation path can be recognized automatically during
installation. If the path is not recognized or incorrect, you need to manuallyselect the IAR installation
path.
Figure 10. Set up IAR_AT32MCU_AddOn
Note: For more details about Pack setup, please refer to “Section 2 Pack setup” of AT32F403A_407 Firmware
BSP&Pack User Guide. Path: ARTERY’s official website→PRODUCTS→Mainstream→AT32F4xx; download
and unzip BSP, and get the “\AT32F403A_407_Firmware_Library_Vx.x.x\document”.
1.1.3.3 Use AT-Linkfor debuganddownload
If you want to use AT-Link in IAR, select CMSIS-DAP in Debugger option.

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Figure 11. Keil Debug option
Go to Debug and click on Settings to enter the Cortex-M Target Driver Setup interface.
1. Select AT-Link(WinUSB)-CMSIS-DAP/AT-Link-CMSIS-DAP;
Note: For details about WinUSB, please refer to FAQ0136_How to use AT-LINKWinUSB to improve download
speed (ARTERY’s official website→SUPPORT→FAQ→FAQ0136).
2. Find Port, select SW and then tick SWJ;
3. Confirm that the ARM SW-DP debug module is recognized.
Figure 12. Keil Debug Settings
Click on Utilities and untick option box 1; then select CMSIS-DAP Debugger in option box 2, and
finally tick option box 1 (it should be unticked first and then ticked).
Figure 13. Keil Utilities

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If you want to use AT-Link in IAR, please click on Project and select Options; then select CMSIS-
DAP in Debugger option, and select SWD in CMSIS DAP option.
Figure 14. IAR Debug option
Figure 15. IAR CMSIS-DAP option
Note: For details about Flash algorithmfile, MCU switch and solutions for “J-Link cannot find MCU”, please
refer to AT32F403A_407 Firmware BSP&Pack User Guide. Path: ARTERY’s official website→PRODUCTS
→Mainstream→AT32F4xx; download and unzip BSP (\AT32F403A_407_Firmware_Library_Vx.x.x\document).
1.1.4 How to replace SXX
Compare the peripheral specifications, Flash size and SRAM size, etc.; unsolder SXX32F103
and replace it with the corresponding AT32F403A/AT32F407 part;

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Step 2: Use ARTERY ICP/ISP or KEIL/ IAR and download SXX32F103 HEX files or BIN files;
Step 3: If necessary, download other materials together with SXX32F103 HEX files or BIN
files, or performsystem calibration;
Step 4: Check if the programcan run normally;
Step 5: For other issues, please refer to MG0007_ Migrating fromSXX32F103 to AT32F403A
(ARTERY’s official website→PRODUCTS→Mainstream→AT32F4xx);
Step 6: If the programstill cannot run properly after completing the above steps, please refer to
other sections of this application note or contact the agent and ARTERY technicians for help.
Note: Due to the flexible memory expansion design of AT32F403A/AT32F407, its internal Flash memory has
non-zero wait area, which may cause poor performance of some SXX32F103 programs on AT32F403A
/AT32F407. In this case, please refer to AN0004_Performance_Optimization (ARTERY’s official website→
SUPPORT→AP Note→AN0004).
1.2 AT32F403A /AT32F407 chip enhanced functions
1.2.1 PLL clock settings
1.2.1.1 PLLgreaterthan72 MHz
The internal PLL of AT32F403A/AT32F407 has a maximum output frequency of 240 MHz, and
settings are slightly different when the clock is greater than 72 MHz. The user needs to set the
PLLRANGE register according to the output frequency (PLL>72 MHz, PLLRANGE=1; PLL≤72 MHz,
PLLRANGE=0).
When the SXX32F103 BSP is used, the PLL setting example (HEXT=8 MHz, PLL=72 MHz)
RCC->CFGR|= (uint32_t)(RCC_CFGR_PLLSRC_HSE|RCC_CFGR_PLLMULL9);
If the user wants to use SXX32F103 programto output a lock greater than 72 MHz on AT32F403A
/AT32F407, it is necessary to configure the PLLRANGE bit.
When PLL=240 MHz, the corresponding setting is as follows:
Figure 16. Use SXX to output 240 MHz clock on AT32F403A /AT32F407
#define RCC_CFG_PLLRANGE_GT72MHZ ((uint32_t)0x80000000)
/*!< WhenPLL frequencyis greater than72MHz */
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL30 |
RCC_CFG_PLLRANGE_GT72MHZ);
When the AT32F403A /AT32F407 BSP is used, the PLL setting example (HEXT=8 MHz)
Figure 17. AT32F403A /AT32F407 crm_pll_output_range parameter
typedef enum
{
CRM_PLL_OUTPUT_RANGE_LE72MHZ= 0x00,/*!< pll clockoutput rangeless than orequal to 72mhz */
CRM_PLL_OUTPUT_RANGE_GT72MHZ= 0x01 /*!< pll clockoutputrange greater than72mhz */

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} crm_pll_output_range_type;
When PLL=72 MHz, the corresponding setting is as follows:
crm_pll_config(CRM_PLL_SOURCE_HEXT_DIV, CRM_PLL_MULT_18, CRM_PLL_OUTPUT_RANGE_LE72MHZ);
When PLL=240 MHz, the corresponding setting is as follows:
crm_pll_config(CRM_PLL_SOURCE_HEXT_DIV, CRM_PLL_MULT_60, CRM_PLL_OUTPUT_RANGE_GT72MHZ);
For details about clock configurations, refer to AN0082_AT32F403A_407_CRM_Start_Guide
(ARTERY’s official website→SUPPORT→AP Note→ AN0118) to learn how to configure and modify
AT32F403A/AT32F407 clock source codes and use New Clock Configuration (ARTERY’s official
website→PRODUCTS→ Mainstream→AT32F4xx) to generate the desired clock code and apply it to
the project.
Figure 18. New Clock Configuration
1.2.1.2 Auto step-by-stepclockswitch
When the internal PLL of AT32F403A/AT32F407 isset to 108 MHz and above, it is necessary to
performauto step-by-step clock switch function.
When the SXX32F103 programis used, the user needs to open system_Sxx32f10x.c, find out the
current system clock frequency configuration function (go through Section 1.2.1.1 PLL settings),
and add the following codes in Italic black to the static void SetSysClockToxxM(void) function.
Figure 19. SXX PLL auto step-by-step switch configurations
/* Wait tillPLL is ready*/
while((RCC->CR&RCC_CR_PLLRDY)== 0)
{
}
*((unsigned int *)0x40021054)|= (0x30); // Enable auto step-by-step clock switchfunction
/* Select PLL as system clocksource */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait tillPLL is usedas system clocksource*/
while ((RCC->CFGR& (uint32_t)RCC_CFGR_SWS)!= (uint32_t)0x08)
{
}
*((unsigned int *)0x40021054)&=~(0x30); // Disable auto step-by-step clock switch function

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When AT32F403A /AT32F407 BSP is used, the example of PLL auto step-by-step switch is shown
below:
Figure 20. AT32 PLL auto step-by-step switch configurations
/* enable autostepmode*/
crm_auto_step_mode_enable(TRUE);
/* selectpll as system clocksource*/
crm_sysclk_switch(CRM_SCLK_PLL);
/* wait till pll is usedas system clocksource*/
while(crm_sysclk_switch_status_get()!= CRM_SCLK_PLL)
{
}
/* disableautostepmode*/
crm_auto_step_mode_enable(FALSE);
/* updatesystem_core_clockglobalvariable*/
system_core_clock_update();
Note: If the auto step-by-step systemclock switch is enabled, it must be disabled after clock switch.
1.2.2 How to enable FPU function
There are two conditions in Keil:
①Use AT32F403A_407 BSP/Pack or the modified SXX BSP/Pack to modify the Floating Point
Hardware.
Figure 21. Enable FPU in Keil
②SXX32F10X does not support FPUfunction. If the user wants to enable FPU function in the
developed project in SXX library, the following operations should be done:
Refer to AT32F403A_407 Firmware BSP&Pack User Guide to set up Keil PACK and
modify the relevant header files;
Select the corresponding AT part number in Options—Target;
Add the following configuration codes at the beginning of SystemInit function of
system_stm32f10x.c, and add cm4.h to the project.

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Figure 22. Add FPU enabling codes in Keil
/* Enable FPU*/
#if defined (__FPU_USED) && (__FPU_USED == 1U)
SCB->CPACR |= ((3U << 10U * 2U) | /* set CP10 Full Access*/
(3U << 11U * 2U) ); /* set CP11 Full Access*/
#endif
There are two conditions in IAR:
①Use AT32F403A_407 BSP/Pack or the modified SXX BSP/Pack to modify the Floating Point
Hardware.
Figure 23. Enable FPU in IAR
②SXX32F10X does not support FPUfunction. If the user wants to enable FPU function in the
developed project in SXX library, the following operations should be done:
Refer to AT32F403A_407 Firmware Library BSP&Pack User Guide to set up IAR PACK and
modify the relevant header files;
Select the corresponding AT32 part number in General Options—Target;
Add the following configuration codes at the beginning of SystemInit function of
system_stm32f10x.c, and add cm4.h to the project.
Figure 24. Add FPU enabling codes in IAR
/* Enable FPU*/
#if defined (__FPU_USED) && (__FPU_USED == 1U)
SCB->CPACR |= ((3U << 10U * 2U) | /* set CP10 Full Access*/
(3U << 11U * 2U) ); /* set CP11 Full Access*/
#endif
For more information, please refer to AN0037_How_to_use_FPU (ARTERY’s official website→
SUPPORT→AP Note→AN0037), which details how to use FPU function on AT32 MCU and
configurations in Keil / IAR.

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1.2.3 AT32F403A /AT32F407 zero-wait/non-zero-wait Flash and
embedded SRAM configurations
Configure the user system data to allocate the internal Flash memory and SRAM.
Taking AT32F403AVGT7 as an example, the internal Flash memory and SRAM can be configured
as one of the followings:
- ZW: 256 KB, NZW: 768 KB, SRAM: 96 KB (factory default);
- ZW: 128 KB, NZW: 896 KB, SRAM: 224 KB.
The core reads the command code stored in zero-wait Flash without any latency, and it is
unnecessary to insert any wait state. For example, if the system clock is 240 MHz and AT32F403A
zero-wait Flash is 256 KB, the first 256 KB of 512 KB bin file can be executed at 240 MHz, and the
later 256 KB bin file is stored in the non-zero wait area and executed at 96 MHz, which is faster
than 72 MHz (the maximum frequency of SXX32F10X). The execution rate of non-zero-wait area is
0.4 times that of the zero-wait area.
Embedded SRAM 96 KB (default)/224 KB, which can be selected in anyof the following
ways:
To configuretheAT32F403ASRAM, theuser needsto referto the description of FLASHuser system
data and set EOPB0 (address: 0x1FFF_F810). EOPB0=0xFF indicates that the on-chip SRAM is 96
KB, and EOPB0=0xFE indicates that the on-chip SRAM is 224 KB. To enable EOPB0, a power-off
or RESET must occur once.
The following section takes AT32F403AVGT7 as an example to introduce how to configure SRAM
size. For more information about the principle and method of SRAM expansion, please refer to
AN0026_Extending_SRAM_in_User's_Program (ARTERY’s officialwebsite→ SUPPORT→AP
Note→AN0026).
①ICP/ISP Programmer
Artery ICP Programmer (BOOT0=0, BOOT1=0)
Connect AT-Link-EZ /AT-Link /J-Link to MCU—Open Artery ICP Programmer—User system
data—Select EOPB0 96 KB/224 KB (complete other relevant settings if any) —Apply to
device
Figure 25.User system data in ICP Programmer

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Figure 26. Select SRAM size in user system data
Artery ISP Programmer (BOOT0=1, BOOT1=0)
Connect UART or USB to MCU—Click on “Next” until enter the final interface—Select “Edit
User system data”—Next—Select EOPB0 96 KB/224 KB (complete other relevant settings if
any) —Apply to device.
Figure 27. Edit user system data in ISP Programmer

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Artery ISP Multi-Port Programmer (BOOT0=1, BOOT1=0)
Select the port to be used—download user system data file after the port is recognized
successfully—Edit—Select 16 KB/32 KB/64 KB—Save to file (create a user system data
programfile)—Close—Start, or download user system data file—Open (the saved user system
data programfile) —Start.
Figure 28.User system data setting in ISP Multi-Port Programmer
②The user can also modify SRAM size in the Bootloader program(IAP). Note that the SRAM
should be set to the same size as the modified SRAM (refer to AN0026).
For example, when the SXX32F103 is used:
Figure 29. Define Extend_SRAM(void) function in SXX program
#define SRAM_96k 0xFF
#define SRAM_224k 0xFE
staticuint32_tF_EOPB0;
F_EOPB0=*(uint32_t*)(0x1FFFF810);
void Extend_SRAM(void)
{
if((F_EOPB0 & 0xFF) != 0xFE) // check if RAM has beensetto 224K, if not, changeEOPB0
{
FLASH_Unlock();
FLASH_EraseOptionBytes();
FLASH_ProgramOptionByteData(0x1FFFF810, SRAM_224k);
… //Set other usersystem data
FLASH_Lock();
NVIC_SystemReset();
}

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}
When the AT32F403A/ AT32F407 is used:
Figure 30. Define Extend_SRAM(void) function in AT32 program
#define SRAM_96k 0xFF
#define SRAM_224k 0xFE
staticuint32_tf_eopb0;
f_eopb0=*(uint32_t*)(0x1FFFF810);
void Extend_SRAM(void)
{
if((f_eopb0 & 0xFF) != 0xFE) // check if RAM has been setto 224K, if not, change EOPB0
{
flash_unlock();
flash_user_system_data_erase();
flash_user_system_data_program(0x1FFFF810,SRAM_224k);
… //Set other usersystem data
flash_lock();
nvic_system_reset();
}
}
It is necessary to erase the user system data before modification. If other options in the user
system data are set, these settings should be read and erased, and then written together with the
configured SRAM size.
③Modify SRAM size in the startup file.
When running the startup file, the SRAM will be loaded. If there is no IAR in the program and the
SRAM is greater than 96 KB, SRAM cannot be loaded successfully, and then a hardfault occurs,
causing the programto fail to run. To avoid this, you can set SRAM=224 KB before loading it to the
startup file.
Add the codes in bold (as shown in Figure 31) to the Keil startup file.
Figure 31. Modify SRAM size in Keil startup file
; Resethandler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
IMPORT Extend_SRAM
MOV32 R0, #0x20001000