ARTERY AT32F425 Series User manual

Getting Started with AT32F425
2022.10.21 1 Ver 2.0.3
AN0129
Application Note
Getting Started with AT32F425
Introduction
This document is aimed at helping users with project development based on AT32F425xx MCUs.
Note: The corresponding code in this application note is developed on the basis of V2.x.x BSP provided by
Artery. For other versions of BSP, please pay attention to the differences in usage.
Applicable products:
Part number
AT32F425xx

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Contents
1Development resources ..................................................................................5
1.1 Set up AT32 development environment ..........................................................................5
1.1.1 Debug tools and evaluation board............................................................................5
1.1.2 Programming tools and software resources .............................................................5
1.1.3 AT32 development environment...............................................................................6
1.1.4 How to quickly replace AT32F415 with AT32F425..................................................12
1.2 AT32F425 functionality configuration ............................................................................12
1.2.1 Instruction prefetch buffer ......................................................................................12
1.2.2 PLL clock configuration..........................................................................................13
1.2.3 Encryption..............................................................................................................14
1.2.4 Set system memory as main memory extension ....................................................17
1.2.5 How to distinguish AT32 MCU from other MCUs ....................................................21
2FAQs about download and compiling........................................................... 22
2.1 Program enters Hard Fault Handler ..............................................................................22
2.2 JLink unable to recognize IC in Keil project..................................................................22
2.3 Errors during download ..................................................................................................22
2.3.1 Flash Download failed–“Cortex-M4”.......................................................................22
2.3.2 No Debug Unit Device found..................................................................................23
2.3.3 RDDI-DAP Error.....................................................................................................23
2.3.4 ISP serial interface gets stuck during download .....................................................23
2.3.5 How to resume program download.........................................................................23
3Security Library (sLib) ..................................................................................24
3.1 Introduction......................................................................................................................24
3.2 Application principles ......................................................................................................24
3.3 How to use sLib...............................................................................................................24
4Revision history............................................................................................25

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List of tables
Table 1. Document revision history............................................................................................... 25

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List of figures
Figure 1. AT_START_F425 and AT-Link-EZ.................................................................................... 5
Figure 2. AT-START-F425 evaluation board package fromARTERY official website ....................... 5
Figure 3. ICP/ISP/AT-Link-Family package on ARTERY official website.......................................... 6
Figure 4. BSP resources on ARTERY official website ..................................................................... 6
Figure 5. Keil_v5 templates template.............................................................................................. 7
Figure 6. Pack resources on ARTERY official website..................................................................... 8
Figure 7. Install ArteryTek.AT32F425_DFP..................................................................................... 8
Figure 8. Install Keil4_AT32MCU_AddOn ....................................................................................... 8
Figure 9. Click “Pack Installer” in Keil.............................................................................................. 9
Figure 10. Install IAR_AT32MCU_AddOn ....................................................................................... 9
Figure 11. Keil Debug option......................................................................................................... 10
Figure 12. Settings option in Keil Debug....................................................................................... 10
Figure 13. Keil Utilities option.........................................................................................................11
Figure 14. IAR Debug option.........................................................................................................11
Figure 15. IAR CMSIS-DAP option ............................................................................................... 12
Figure 16. Wait state bit in FLASH_PSR register .......................................................................... 13
Figure 17. system_clock_config function....................................................................................... 13
Figure 18. AT32F425 94MHz output clock..................................................................................... 13
Figure 19. Use ICP tool to enable/disable access protection......................................................... 14
Figure 20. Use ISP to enable access protection............................................................................ 15
Figure 21. Use ISP to disable access protection........................................................................... 15
Figure 22. Use ICP tool to enable erase/program protection......................................................... 16
Figure 23. Use ICP tool to disable erase/program protection ........................................................ 17
Figure 24. Use ICP tool to set boot memory AP mode .................................................................. 18
Figure 25. Boot memoryAP mode operating progress.................................................................. 18
Figure 26. Use ICP tool to set offline boot mode AP mode............................................................ 19
Figure 27. Use ICP tool to set offline project programming............................................................ 20
Figure 28. ICP tool to monitor offline download status................................................................... 20
Figure 29. Read Cortex ID............................................................................................................ 21
Figure 30. Read PID and UID ....................................................................................................... 21
Figure 31. Error: Flash Download failed–“Cortex- M4” .................................................................. 22

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1 Development resources
Resources download link:
Visit Artery website: https://www.arterychip.com
1.1 Set up AT32 development environment
1.1.1 Debug tools and evaluation board
The AT32F425 evaluation board comes with AT-Link-EZfor the debug purpose, as shown in the
left red box of the figure below. It can also be disassembled from the evaluation board and used
separately with other circuit boards. This debug tool can be used for several purposes such IDE
online debugging, online programming and USB-to-serial interface.
Figure 1. AT_START_F425 and AT-Link-EZ
Note: For details on AT-START-AT32F425 evaluation board, refer to the “UM_AT_START_F425_Vx.x”, which
is available from ARTERY official website → Product → Value line → AT32F425 series → Resources → Evaluation
Board (download and unzip, and then go to “\AT_START_F425_Vx.x\03_Documents”).
Figure 2. AT-START-F425 evaluation board package from ARTERY official website
1.1.2 Programming tools and software resources
AT programming tools and software: AT-Link / AT-Link+ /AT-Link-Pro / AT-Link-ISO /AT-Link-
EZ, and ICP/ISP

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Third-party programming tools: J-Link, Armfly, Alientek, XWOPEN, ICWORKSHOP, ZLG,
MaxWiz, Amomcu, Acroview, Forcreat, Galecomm, Prosystems, Rx-prog, Sinaen, XELTEK,
and Zhifeng
Note: These programming tools are available from ARTERY official website → Support→Hardware
Development Tool or 3rd Party Writer.
ICP user guide:Refer to the UM_ICP_Programmer, which is available from ARTERY official
website→Products→Value line→AT32F4xx→Tool→ICP (download and unzip, and then go to
Artery_ICP_Programmer_Vx.x.xx\Document\UM_ICP_Programmer)
ISP user guide:Refer to the UM_ISP_Programmer, which is available from ARTERY official
website→Products→Value line→AT32F4xx→Tool→ISP (download and unzip, and then go to
Artery_ISP_Programmer_Vx.x.xx\Document\UM_ISP_Programmer)
AT-Link user guide: Refer to the UM0004_AT-Link_User_Manual, which is available from
ARTERY official website →Products→Value line→AT32F4xx→Tool→AT-Link-Family
(download and unzip, and then go to AT_Link_CH_ Vx.x.x\05_Documents\UM0004_AT-
Link_User_Manual_EN_Vx.x.x)
Figure 3. ICP/ISP/AT-Link-Family package on ARTERY official website
1.1.3 AT32 development environment
1.1.3.1 Templateproject
The frequently-used IDE template projects are included in ARTERY’s firmware BSP. You can get
these resources by visiting ARTERY official website→Products→Value line→AT32F425 series→
BSP.
Figure 4. BSP resources on ARTERY official website

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BSP offers such template projects as Keil_v5/Keil_v4/IAR_6.10/IAR_7.4/IAR_8.2/eclipse_gcc
/at32_ide, which are stored at AT32F425_Firmware_Library_V2.x.x\project\at_start_f4xx
\templates.
Just simply open the desired folder and IDE project. Figure 5 below shows an example of Keil_v5
project.
Figure 5. Keil_v5 templates template
This template mainly contains the following items:
①at32f425_clock.c: clock configuration file, which defines the default clock frequency and
clock path
②at32f425_int.c: interrupt file, which contains the default process of handling some core
interrupts
③main.c: main code file
④at32f425_board.c: board configuration file, which defines common hardware such as
buttons and LEDs on AT-START evaluation board
⑤firmware: it contains “at32f425_xx.c”that is used as a driver file for peripherals
⑥system_at32f425.c: systeminitialization file
⑦startup_at32f425.s: startup file
⑧readme.txt: a read-me txt file that describes some application functions, configuration
method and application notes relating to a template project.
In addition to “Templates”, a large number of examples are included in BSP for users’ reference.
These example codes are stored at:
AT32F425_Firmware_Library_V2.x.x\project\at_start_f4xx\examples.
Note: For details on BSP, refer to Section 4 of the document “AT32F425 _firmware_BSP&Pack_user_guide”,
which is available from ARTERY official website → Products→Value line→AT32F425 series→BSP (download
and unzip, and then go to “\AT32F425_Firmware_Library_Vx.x.x\document”).
1.1.3.2 Pack installation
The installation of Pack is required to add AT32 MCU part number in Keil/IAR.
The Pack is available from ARTERY official website→Products→Value line→AT32F425 series.

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Figure 6. Pack resources on ARTERY official website
For the Keil compiling system, Keil 4.74, Keil 5.23 and above versions are recommended.
For Keil_v5, users need to unzip the “Keil5_AT32MCU_AddOn”and then install the
“ArteryTek.AT32F425_DFP”.
For Keil_v4, users directly install the “Keil4_AT32MCU_AddOn”.
By default, the installation path of Keil can be automatically recognized when installing. In case of
recognition failure, users need to manually select the Keil installation path.
Figure 7. Install ArteryTek.AT32F425_DFP
Figure 8. Install Keil4_AT32MCU_AddOn

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Users can also open Keil→click “Pack Installer”→click “File”→choose “Import” to import the
corresponding pack downloaded from ARTERY official website.
Figure 9. Click “Pack Installer” in Keil
For the IAR compiling system, IAR7.0, IAR6.1 and above versions are recommended.
By default, when installing the “IAR_AT32MCU_AddOn”, the installation path of IAR can be
automatically recognized. In case of recognition failure, users need to manually select the IAR
installation path.
Figure 10. Install IAR_AT32MCU_AddOn
Note: For details on Pack, refer to Section 2 of the document “AT32F425_firmware_BSP&Pack_user_guide”,
which is available from ARTERY official website → Products→Value line→AT32F425 series→BSP (download
and unzip, and then go to “\AT32F425_Firmware_Library_Vx.x.x\document”).
1.1.3.3 Debuganddownloadwith AT-Linktool
If AT-Link is to be used in Keil environment, click “Debug”, and then choose “CMSIS-DAP
Debugger”.

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Figure 11. Keil Debug option
Next, click “Settings” to enter “Cortex-M Target Driver Setup” window, as shown in Figure 12 below.
1. Select “AT-Link(WinUSB)-CMSIS-DAP/AT-Link-CMSIS-DAP”;
Note: For more information on WinUSB, refer to “ FAQ0136_How_to_use_AT-LINK_WinUSB_EN_V2.0.0”,
which is available from ARTERY official website→Support→FAQ→FAQ0136.
2. In “Port” option, choose “SW”, and then tick “SWJ” option;
3. Confirm that the “ARM SW-DP” is recognized.
Figure 12. Settings option in Keil Debug
Then, click “Utilities”→untick “Use Debug Driver” (the red box marked 1)→select “CMSIS-DAP
Debugger” (the red box marked 2) →finally tick “Use Debug Driver” (note: users need to untick this
box first and then tick it).

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Figure 13. Keil Utilities option
If AT-Link is to be used in IAR environment, click “Project”→choose “Options” →go to “Debugger”
and choose “CMSIS-DAP”→tick “SWD”.
Figure 14. IAR Debug option

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Figure 15. IAR CMSIS-DAP option
Note: The document “AT32F425firmware_BSP&Pack_user_guide” provides details on Flash algorithms, MCU
product series replacement and J-Link. This document is available from ARTERY officialwebsite →
Products→Value line→AT32F425 series→BSP (download and unzip, and then go to
“\AT32F425_Firmware_Library_Vx.x.x\document”).
1.1.4 How to quickly replace AT32F415 with AT32F425
The migration guide from AT32F415 to AT32F425 is detailed in the document
“MG0019_Migrating from AT32F415 to AT32F425”, which is available from ARTERY official
website→Product→Value line→AT32F425 series page.
If program failure occurs, please refer to the corresponding sections of this document, or you
can contact the agent and Artery’s technical staff for support.
Note: For more information on how to get better AT32F425 operating performance, refer to the application
note “AN0004_Performance_Optimization” fromARTERY officialwebsite → Product → AP Note → AN0004.
1.2 AT32F425 functionality configuration
1.2.1 Instruction prefetch buffer
Instruction prefetch buffer helps to achieve quicker CPU execution speed.After instruction prefetch
buffer is enabled, the subsequent word is already awaiting in the buffer while CPU is reading the
current word. The instruction prefetch controller will then determine whether or not to access Flash
memory according to available space in the buffer. If there is at least a free space in the instruction
prefetch buffer, the instruction prefetch controller will performa read access.
Different system clocks require different wait states, which can be set through the bit [2:0] (WTCYC)
in the FLASH_PSR register.

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Figure 16. Wait state bit in FLASH_PSR register
AT32 library has made relevant settings in the “system_clock_config()” function. For BSP of other
AT32 MCU series, you can also find this settings at the same location.
Figure 17. system_clock_config function
1.2.2 PLL clock configuration
AT32F425 embeds a PLL with a maximum of 96 MHz clock output. The AT32F425 PLLclock can be
configured by setting the CRM_CFG or CRM_PLL register. The CRM_PLL register can be used to
configure different PLLclock frequencies, with the following formula:
PLL output clock = PLL reference input clock × PLL frequency multiplication factor PLL_NS
PLL predivider factor (PLL_MS) × PLL post − divider factor (PLL_FR)
Example of PLL settings using CRM_CFG register, based on HEXT=8MHz, PLL=96MHz
crm_pll_config(CRM_PLL_SOURCE_HEXT,CRM_PLL_MULT_12);
Example of PLL settings using CRM_PLL register, based on HEXT=8MHz, PLL=94MHz
Figure 18. AT32F425 94MHz output clock
#define CRM_PLL_NS ((uint16_t)0x2F) /* PLL_NS=47*/
#define CRM_PLL_MS ((uint16_t)0x01) /* PLL_MS=1 */
/* config pll clock resource PLL_FR =4*/
crm_pll_config2(CRM_PLL_SOURCE_HEXT,CRM_PLL_NS,CRM_PLL_MS, CRM_PLL_FR_4);

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Where, the “CRM_PLL_SOURCE_HEXT” parameter indicates that the HEXT is used as an
external clock source, PLL_NS=47, PLL_MS=1, and PLL_FR value is “CRM_PLL_FR_4 (0x02,
divided by 4)”.
For details about clock configuration, please refer to AN0121_AT32F425_CRM_Start_Guide. This
document is available fromATERTY official website→Support→AP Note→AN0121. It introduces
how to configure and modify AT32F425 clock source, and how to use the New Clock Configuration
tool to quickly generate the desired clock code and apply it to projects.
1.2.3 Encryption
Note: The BOOT1 bit of AT32F425 series is located in the user system data area (0x1FFF F800).
When ISP tool is used, it is mandatory to ensure that nBOOT1=1 is asserted (default value) so that
the programis booted from system memory instead of SRAM.
1.2.3.1 Accessprotection
Access protection is commonly referred to as “encryption” and applies to the entire Flash memory.
Once the Flash access protection is enabled, the internalFlash memory can only be read through
normal execution of the program, instead of through JTAG or SWD. Using ISP or ICP tool to unlock
access protection will trigger erase operation to the Flash memory.
Note: The high-level access protection, after being enabled, cannot be unlocked. Meanwhile, it is
forbidden for users to erase and write system data area in any way.
Users can use ICP/ISP programmer to enable or disable access protection.
Artery ICP Programmer (BOOT0=0)
Enable access protection: Target –Access protection –Enable access protection or enable
high-level access protection (see Figure 19 below).
Unlock access protection: Target –Access protection –Disable
Figure 19. Use ICP tool to enable/disable access protection
Artery ISP Programmer (BOOT0=1)
Enable access protection: Keep clicking “Next” until you enter the final interface. Then tick
“Protection” -- choose “Enable” and “Access protection” -- click “Yes” (see Figure 20 below).
Unlock access protection: Tick “Protection” -- choose “Disable” and “Access protection” –click
“Yes”.
Artery ISP Multi-Port Programmer (BOOT0=1)
Enable access protection: Tick “Protection” -- choose “Enable” and “Access protection” or
“High-level access protection” -- click “Start”.

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Unlock access protection: Tick “Protection” -- choose “Disable” and “Access protection” -- click
“Start”.
Figure 20. Use ISP to enable access protection
Figure 21.Use ISP to disable access protection
Note: Access protection, after being enabled, cannot be unlockedthrough erase operation.

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1.2.3.2 Erase/programprotection
Write protection applies to the entire Flash memory or to part of Flash area. Once the Flash write
protection is enabled, the internal Flash cannot be written.
Users can use ICP/ISP programmer to enable or disable erase/programprotection.
Artery ICP Programmer (BOOT0=0)
Enable erase/programprotection: Target –User system data –tick the page to be
erase/program-protected –Apply to device.
Disable erase/programprotection: Target –User system data –untick the page to be
erase/program-protected –Apply to device.
Artery ISP Programmer (BOOT0=1)
Enable erase/programprotection: Are you sure to enable erase/programprotection?--Yes.
Disable erase/programprotection: Are you sure to disable erase/programprotection?--Yes.
Artery ISP Multi-Port Programmer (BOOT0=1)
Enable erase/programprotection: Are you sure to enable erase/programprotection?--Yes.
Disable erase/programprotection: Are you sure to disable erase/programprotection?--Yes.
Figure 22. Use ICP tool to enable erase/program protection

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Figure 23. Use ICP tool to disable erase/program protection
Note: Erase/program protection, after beingenabled, cannot be unlockedthrough erase operation.
1.2.4 Set system memory as main memory extension
System memory is used as a boot mode by default to store microcontroller manufacturer’ Startup
Code. On top of this, in AT32F425 series, a new feature is added to the system memory by using it
to store user-defined codes as an extended memory area (AP mode).
Note: System memory AP mode is irreversible andcan only be set once, meaningthat after AP mode
is selected, its original BOOT mode cannot be resumed.
During product development, users can use Artery ICP Programmer to enable system memory as
an extended memory according to the following procedures.
Connect AT-Link or J-Link to AT-START-F425 board and supply power;
Open Artery ICP programmer and choose AT-Link or J-Link connection;
Go to menu bar: Target –Boot memory AP mode –OK.

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Figure 24. Use ICP tool to set boot memory AP mode
To avoid unexpected wrong operations, users need manuallyenter the passkey “0xA35F6D24,
and then check whether the operation is successful or not in “File info”.
Figure 25. Boot memory AP mode operating progress
In mass production stage, users can use Artery ICP Programmer to enable system memory as
memory extension area according to the following procedures:
Connect AT-Link to AT-START-F425 board and supply power;
Note: The onboard AT-Link EZ edition of AT-START-F425 does not support offline programming. Therefore,
users can only use other editions.
Open Artery ICP programmer and choose AT-Link connection;

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Go to menu bar: AT-Link setting -- AT-Link offline configuration setting;
Follow the steps below to generate off-line project:
1. Click “Create”
2. Enter the project name
3. Select a the desired MCU series and MCU part number
4. Add .hex file
5. Choose SWD as download interface
6. Tick “Boot mode AP mode” option and enter the passkey
7. Save project file or save project to AT-Link
In addition to above settings, users can also make other configurations as needed.
Figure 26. Use ICP tool to set offline boot mode AP mode
In Step 7, if you choose “Save project file”, the project will be saved as .atcp file so that it can be
loaded onto other AT-Link.
The following dialogue window will pop out during actual operation. If “This project is only used
at the specified AT-Link” option is ticked, it means that this project is bonded to a particular AT-
Link andcan only beused in this AT-Link.In this case, users needto enterAT-Linkserial number
which will be bonded to. If “This project is only used once” option is ticked, it means that this
project could only be used once in the same AT-Link.

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Figure 27. Use ICP tool to set offline project programming
In step 7, if you choose “Save project to AT-Link” and operation is successful, in “AT-Link
offline download status” option, you need to choose a project name for offline download; click
“Save and activate”, and then click “Start download”.
Figure 28. ICP tool to monitor offline download status
For more information on system memory extension, please refer to the document
AN0066_config_boot_memory_as_extension_of_main_memory(AP_mode), which is available
from ARTERY officialwebsite →Support →AP Note →AN0066.
For demos running user program in the system memory, please refer to the BSP, which is
available from ARTERY official website →Product →Value line →AT32F425 series →BSP
(download and unzip, and then go to
“AT32F425_Firmware_Library_V2.x.x\utilities\at32f425_boot_memory_ap_demo”)