Epson S1D13503 Series User manual

MF1020-02
S1D13503 Series Technical Manual
Technicl Manual
S1D13503 Series
Technical Manual
Dot Matrix Graphics LCD Controller
S1D13503 Series
EPSON Electronic Devices Website
ELECTRONIC DEVICES MARKETING DIVISION
http://www.epson.co.jp/device/
First issue October,1997 M
Printed April, 2001 in Japan C B
This manual was made with recycle papaer,
and printed using soy-based inks.

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Comparison table between new and previous number of Evaluation Boards
S5U 13705 P00C
Specification
Corresponding model number (13705: for S1D13705)
Product classification (S5U: development tool for semiconductor)
S1 D 13706 F 00A0 00
The information of the product number change
Starting April 1, 2001, the product number will be changed as listed below. To order from April 1,
2001 please use the new product number. For further information, please contact Epson sales
representative.
Devices
Configuration of product number
Comparison table between new and previous number
Packing specification
Specification
Package (B: CSP, F: QFP)
Corresponding model number
Model name (D: driver, digital products)
Product classification (S1: semiconductor)
Evaluation Board
Previous No.
SED1335 Series
SED1335D0A
SED1335F0A
SED1335F0B
S1D13305 Series
S1D13305D00A
S1D13305F00A
S1D13305F00B
New No.
Previous No.
SED135x Series
SED1353D0A
SED1353F0A
SED1353F1A
SED1354F0A
SED1354F1A
SED1354F2A
SED1355F0A
SED1356F0A
S1D1350x Series
S1D13503D00A
S1D13503F00A
S1D13503F01A
S1D13504F00A
S1D13504F01A
S1D13504F02A
S1D13505F00A
S1D13506F00A
New No.
Previous No.
SED137x Series
SED1374F0A
SED1375F0A
SED1376B0A
SED1376F0A
SED1378 Series
S1D1370x Series
S1D13704F00A
S1D13705F00A
S1D13706B00A
S1D13706F00A
S1D13708 Series
New No.
Previous No.
SED13Ax Series
SED13A3F0A
SED13A3B0B
SED13A4B0B
S1D13A0x Series
S1D13A03F00A
S1D13A03B00B
S1D13A04B00B
New No.
Previous No.
SED138x Series
SED1386F0A S1D1380x Series S1D13806F00A
New No.
• S1D1350x Series
• S1D13305 Series • S1D1370x Series
• S1D13A0x Series
• S1D1380x Series
• S1D1350x Series
• S1D1370x Series • S1D1380x Series
• S1D13A0x Series
Previous No.
SDU1353#0C
SDU1354#0C
SDU1355#0C
SDU1356#0C
S5U13503P00C
S5U13504P00C
S5U13505P00C
S5U13506P00C
New No. Previous No.
SDU1374#0C
SDU1375#0C
SDU1376#0C
SDU1376BVR
SDU1378#0C
S5U13704P00C
S5U13705P00C
S5U13706P00C
S5U13706B32R
S5U13708P00C
New No. Previous No.
SDU1386#0C S5U13806P00C
New No.
Previous No.
SDU13A3#0C
SDU13A4#0C S5U13A03P00C S5U13A04P00C
New No.

S1D13503F00ATechnical Manual
HARDWARE FUNCTIONAL SPECIFICATION
PROGRAMMING NOTES AND EXAMPLES
UTILITIES
S5U13503P00C PCI BUS EVALUATION
BOARD USER’S MANUAL
APPLICATION NOTES
TOBIRA.fm Page 1 Monday, April 16, 2001 4:23 PM

S1D13503 Series
Dot Matrix Graphic LCD Controller
Hardware Functional
Specification

HARDWARE FUNCTIONAL SPECIFICATION
Table of Contents
1I NTRODUCTION .........................................................................................................................1-1
1.1 Scope ............................................................................................................................................1-1
1.2 Overview Description ....................................................................................................................1-1
2F
EATURES
...............................................................................................................................1-2
2.1 Technology....................................................................................................................................1-2
2.2 System ..........................................................................................................................................1-2
2.3 Display Modes...............................................................................................................................1-2
2.4 Display Support.............................................................................................................................1-3
2.5 Power Management ......................................................................................................................1-3
3T
YPICAL
S
YSTEM
B
LOCK
D
IAGRAMS
..........................................................................................1-4
16-Bit MC68000 MPU................................................................................................................1-4
MPU with READY (or WAIT#) Signal.........................................................................................1-5
ISA Bus .....................................................................................................................................1-6
3.1 Internal Block Diagram..................................................................................................................1-7
3.2 Functional Block Descriptions .......................................................................................................1-7
Bus Signal Translation...............................................................................................................1-7
Control Registers .......................................................................................................................1-7
Sequence Controller ..................................................................................................................1-7
LCD Panel Interface...................................................................................................................1-7
Look-Up Table ...........................................................................................................................1-7
Port Decoder..............................................................................................................................1-7
Memory Decoder .......................................................................................................................1-7
Data Bus Conversion.................................................................................................................1-8
Address Generator.....................................................................................................................1-8
MPU / CRT Selector ..................................................................................................................1-8
Display Data Formatter..............................................................................................................1-8
Clock Inputs / Timing .................................................................................................................1-8
SRAM Interface..........................................................................................................................1-8
4P
INOUT
D
IAGRAM
.....................................................................................................................1-9
5P
IN
D
ESCRIPTION
...................................................................................................................1-13
5.1 Description ..................................................................................................................................1-13
5.2 Summary of Configuration Options .............................................................................................1-15
6 D.C. C HARACTERISTICS .........................................................................................................1-16
7 A.C. C HARACTERISTICS .........................................................................................................1-18
7.1 Bus Interface Timing ...................................................................................................................1-18
MC68000 Interface Timing.......................................................................................................1-18
IOW# Timing ......................................................................................................................1-18
IOR# Timing.......................................................................................................................1-19
MEMW# Timing..................................................................................................................1-19
MEMR# Timing...................................................................................................................1-20
Non-MC68000, MPU/Bus with READY (or WAIT#) Signal......................................................1-21
IOW# Timing ......................................................................................................................1-21
IOR# Timing.......................................................................................................................1-21
MEMW# Timing..................................................................................................................1-22
MEMR# Timing...................................................................................................................1-22
7.2 Clock Input Requirements...........................................................................................................1-23
Recommended Clock Input......................................................................................................1-23
7.3 Display Memory Interface Timing................................................................................................1-24
Write Data to Display Memory .................................................................................................1-24
Read Data from Display Memory.............................................................................................1-24
7.4 LCD Interface ..............................................................................................................................1-25

LCD Interface Timing - 4-Bit Single, 8-Bit Single/Dual Monochrome Panels ..........................1-25
LCD Interface Timing - 4-Bit Single Color Panel .....................................................................1-27
LCD Interface Timing - 8-Bit Single Color Panels Format 2 / 8-Bit Dual Color Panels............1-28
LCD Interface Timing - 16-Bit Single/Dual Color Panels.........................................................1-29
LCD Interface Timing - 8-Bit Single Color Panels Format 1....................................................1-30
LCD Interface Options.............................................................................................................1-31
8H
ARDWARE
R
EGISTER
I
NTERFACE
...........................................................................................1-38
8.1 Register Descriptions .................................................................................................................1-38
8.2 Look-Up Table Architecture ........................................................................................................1-48
Gray Shade Display Modes.....................................................................................................1-48
4-Level Gray Shade Mode.................................................................................................1-48
16-Level Gray Shade Mode...............................................................................................1-48
Color Display Modes................................................................................................................1-49
4-Level Color Mode............................................................................................................1-49
16-Level Color Mode..........................................................................................................1-50
256-Level Color Mode........................................................................................................1-51
8.3 Power Save Modes.....................................................................................................................1-52
Power Save Mode 1 ................................................................................................................1-52
Power Save Mode 2 ................................................................................................................1-52
Power Save Mode Function Summary....................................................................................1-52
Pin States in Power Save Modes ............................................................................................1-53
9D ISPLAY M EMORY I NTERFACE .................................................................................................1-54
9.1 SRAM Configurations Supported................................................................................................1-54
8-Bit Mode ...............................................................................................................................1-54
16-Bit Mode .............................................................................................................................1-55
9.2 SRAM Access Time....................................................................................................................1-57
8-Bit Display Memory Interface................................................................................................1-57
16-Bit Display Memory Interface..............................................................................................1-57
9.3 Frame Rate Calculation ..............................................................................................................1-57
For Single Panel......................................................................................................................1-57
For Dual Panel.........................................................................................................................1-57
9.4 Memory Size Calculation ............................................................................................................1-58
9.5 Memory Size Requirement..........................................................................................................1-58
10 M
ECHANICAL
D
ATA
................................................................................................................1-60

List of Figures
Figure 3-1 16-Bit 68000 Series (example implementation only - actual may vary) ...............................1-4
Figure 3-2 8-Bit Mode, Example: Z80 (example implementation only - actual may vary) .....................1-5
Figure 3-3 16-Bit Mode, Example: i8086 (maximum mode) (example implementation only - actual may
vary)1-5
Figure 3-4 8-Bit Mode (ISA) (example implementation only - actual may vary) ....................................1-6
Figure 3-5 16-Bit Mode (ISA) (example implementation only - actual may vary) ..................................1-6
Figure 3-6 Internal Block Diagram.........................................................................................................1-7
Figure 4-1 S1D13503F00A Pinout Diagram..........................................................................................1-9
Figure 4-2 S1D13503F01A Pinout Diagram........................................................................................1-10
Figure 4-3 S1D13503D00A Pad Diagram ...........................................................................................1-11
Figure 7-1 IOW# Timing (MC68000) ...................................................................................................1-18
Figure 7-2 IOR# Timing (MC68000)....................................................................................................1-19
Figure 7-3 MEMW# Timing (MC68000)...............................................................................................1-19
Figure 7-4 MEMR# Timing (MC68000)................................................................................................1-20
Figure 7-5 IOW# Timing (Non-MC68000) ...........................................................................................1-21
Figure 7-6 IOR# Timing (Non-MC68000) ............................................................................................1-21
Figure 7-7 MEMW# Timing (Non-MC68000).......................................................................................1-22
Figure 7-8 MEMR# Timing (Non-MC68000)........................................................................................1-22
Figure 7-9 Clock Input Requirements..................................................................................................1-23
Figure 7-10 Recommended Clock Interface..........................................................................................1-23
Figure 7-11 Write Data to Display Memory............................................................................................1-24
Figure 7-12 Read Data from Display Memory.......................................................................................1-24
Figure 7-13 LCD Interface Timing - Monochrome Panel.......................................................................1-25
Figure 7-14 LCD Interface Timing - 4-Bit Single Color Panel................................................................1-27
Figure 7-15 LCD Interface Timing - 8-Bit Single Color Panels Format 2 / 8-Bit Dual Color Panels ......1-28
Figure 7-16 LCD Interface Timing - 16-Bit Single/Dual Color Panels....................................................1-29
Figure 7-17 LCD Interface Timing - 8-Bit Single Color Panels Format 1...............................................1-30
Figure 7-18 4-Bit Single Monochrome Panel Timing.............................................................................1-31
Figure 7-19 8-Bit Single Monochrome Panel Timing.............................................................................1-31
Figure 7-20 8-Bit Dual Monochrome Panel Timing................................................................................1-32
Figure 7-21 4-Bit Single Color Panel Timing .........................................................................................1-32
Figure 7-22 8-Bit Single Color Panel Timing - Format 1: AUX[03] Bit 3 = 0 and AUX[01] Bit 2 = 1 ......1-33
Figure 7-23 8-Bit Single Color Panel Timing - Format 2: AUX[03] Bit 3 = 1 and AUX[01] Bit 2 = 1 ......1-34
Figure 7-24 8-Bit Dual Color Panel Timing............................................................................................1-35
Figure 7-25 External Circuit Required for 16-Bit Panel..........................................................................1-35
Figure 7-26 16-Bit Single Color Panel Timing with External Circuit.......................................................1-36
Figure 7-27 16-Bit Dual Color Panel Timing with External Circuit .........................................................1-37
Figure 8-1 4-Level Gray-Shade Mode Look-Up Table Architecture ....................................................1-48
Figure 8-2 16-Level Gray-Shade Mode Look-Up Table Architecture ..................................................1-48
Figure 8-3 4-Level Color Mode Look-Up Table Architecture...............................................................1-49
Figure 8-4 16-Level Color Mode Look-Up Table Architecture.............................................................1-50
Figure 8-5 256-Level Color Mode Look-Up Table Architecture...........................................................1-51
Figure 9-1 8-Bit Mode - 8K bytes SRAM (Requires AUX[01] bit 0 = 0) ...............................................1-54
Figure 9-2 8-Bit Mode - 16K bytes SRAM (Requires AUX[01] bit 0 = 0) .............................................1-54
Figure 9-3 8-Bit Mode - 32K bytes SRAM (Requires AUX[01] bit 0 = 1) .............................................1-54
Figure 9-4 8-Bit Mode - 40K bytes SRAM
[Either (8K × 8 + 32K × 8) requiring AUX[01] bit 0 = 0 or (32K × 8 + 8K × 8) requiring AUX[01]
bit 0 = 1]..............................................................................................................................1-54
Figure 9-5 8-Bit Mode - 64K bytes SRAM (Requires AUX[01] bit 0 = 1) .............................................1-55

Figure 9-6 16-Bit Mode - 16K bytes SRAM.........................................................................................1-55
Figure 9-7 16-Bit Mode - 64K bytes SRAM.........................................................................................1-55
Figure 9-8 16-Bit Mode - 128K bytes SRAM.......................................................................................1-56
Figure 10-1 Mechanical Drawing QFP5-100-S2 ...................................................................................1-60
Figure 10-2 Mechanical Drawing QFP15-100-STD...............................................................................1-61

List ofTables
Table 5-1 Bus Interface....................................................................................................................1-13
Table 5-2 Display Memory Interface.................................................................................................1-14
Table 5-3 LCD Interface...................................................................................................................1-14
Table 5-4 Clock Inputs......................................................................................................................1-14
Table 5-5 Power Supply...................................................................................................................1-14
Table 5-6 Summary of Power On / Reset Options...........................................................................1-15
Table 5-7 I/O and Memory Addressing Example..............................................................................1-15
Table 6-1 Absolute Maximum Ratings..............................................................................................1-16
Table 6-2 Recommended Operating Conditions..............................................................................1-16
Table 6-3 Input Specifications..........................................................................................................1-16
Table 6-4 Output Specifications .......................................................................................................1-17
Table 7-1 IOW# Timing (MC68000) .................................................................................................1-18
Table 7-2 IOR# Timing (MC68000)..................................................................................................1-19
Table 7-3 MEMW# Timing (MC68000).............................................................................................1-19
Table 7-4 MEMR# Timing (MC68000)..............................................................................................1-20
Table 7-5 IOW# Timing (Non-MC68000)..........................................................................................1-21
Table 7-6 IOR# Timing (Non-MC68000) ..........................................................................................1-21
Table 7-7 MEMW# Timing (Non-MC68000).....................................................................................1-22
Table 7-8 MEMR# Timing (Non-MC68000)......................................................................................1-22
Table 7-9 Clock Input Requirements................................................................................................1-23
Table 7-10 Write Data to Display Memory..........................................................................................1-24
Table 7-11 Read Data from Display Memory.....................................................................................1-24
Table 7-12 LCD Interface Timing - 4-Bit Single and 8-Bit Single/Dual Monochrome Panel...............1-26
Table 7-13 LCD Interface Timing - 4-Bit Single Color Panel..............................................................1-27
Table 7-14 LCD Interface Timing - 8-Bit Single Color Panels Format 2 / 8-Bit Dual Color Panels ....1-28
Table 7-15 LCD Interface Timing - 16-Bit Single/Dual Color Panels..................................................1-29
Table 7-16 LCD Interface Timing - 8-Bit Single Color Panels Format 1.............................................1-30
Table 8-1 Gray Shade/Color Mode Selection...................................................................................1-39
Table 8-2 LCD Data Width ...............................................................................................................1-40
Table 8-3 Maximum Value of Line Byte Count Register - 8-Bit Display Memory Interface..............1-41
Table 8-4 Maximum Value of Line Byte Count Register - 16-Bit Display Memory Interface............1-41
Table 8-5 Power Save Mode Selection............................................................................................1-41
Table 8-6 ID Bit Usage.....................................................................................................................1-46
Table 8-7 Look-Up Table Access.....................................................................................................1-46
Table 8-8 Look-Up Table Configurations..........................................................................................1-48
Table 8-9 Power Save Mode Selection............................................................................................1-52
Table 8-10 Power Save Mode Function Summary.............................................................................1-52
Table 8-11 Pin States in Power Save Modes.....................................................................................1-53
Table 9-1 8-Bit Display Memory Interface SRAM Access Time.......................................................1-57
Table 9-2 16-Bit Display Memory Interface SRAM Access Time.....................................................1-57
Table 9-3 Memory Size Requirement: Number of Horizontal Pixels = 640......................................1-58
Table 9-4 Memory Size Requirement: Number of Horizontal Pixels = 480......................................1-59
Table 9-5 Memory Size Requirement: Number of Horizontal Pixels = 320......................................1-59

S1D13503 Series Hardware Functional Specification
S18A-A-011-01 1-1
1I
NTRODUCTION
1.1 Scope
This is the Functional Specification for the S1D13503 Dot Matrix Graphic Color LCD Controller.
Included in this document are timing diagrams,AC and DC characteristics, register descriptions, and
power management descriptions. This document is intended for two audiences, Video Subsystem
Designers and Software Developers.
1.2 Overview Description
This device is designed for products where low cost, low power consumption, and low component
count are the major design considerations. This chip operates from 2.7Volts to 5.5 Volts and up to 25
MHz to suit different power consumption, speed and cost requirements. The S1D13503 offers a flex-
ible microprocessor interface and is pin compatible with the SED1352.
The S1D13503 is capable of displaying a maximum of 16 levels of gray shade or 256 simultaneous
colors. In gray shade modes, a 16 × 4 Look-Up Table is provided to allow remapping of the 16 pos-
sible gray shades displayed on the LCD panel. In color modes, three 16 × 4 Look-Up Tables are pro-
vided to allow remapping of the 4096 possible colors displayed on the LCD panel. The S1D13503
can interface to an MC68000 family microprocessor or an 8/16-bit MPU/Bus with minimum exter-
nal “glue” logic. This device can directly control up to 128K bytes of static RAM with a 16-bit data
path, or up to 64K bytes with an 8-bit data path.

EPSON
1-2 S18A-A-011-01
2F
EATURES
2.1 Technology
• low power CMOS
• 2.7 to 5.5 volt operation
• S1D13503F00A is 100 pin QFP5-S2 surface mount package
• S1D13503F01A is 100 pin QFP15-STD surface mount package
• S1D13503D00A is Die form
2.2 System
• maximum 25 MHz input clock (or pixel clock)
• 2-terminal crystal input for internal oscillator or direct connection to external clock source
• maximum 16 MHz, 16-bit MC68000 MPU interface
• 8-bit or 16-bit MPU/Bus interface with memory accesses controlled by a READY (or WAIT#) sig-
nal
• option to use built-in index register or direct-mapping to access one of sixteen internal registers
• 8-bit or 16-bit SRAM data bus interface configurations
• display memory configurations:
– 128K bytes using one 64K × 16 SRAM
– 128K bytes using two 64K × 8 SRAMs
– 64K bytes using two 32K × 8 SRAMs
– 40K bytes using one 8K × 8 and one 32K × 8 SRAM
– 32K bytes using one 32K × 8 SRAM
– 16K bytes using two 8K × 8 SRAMs
– 8K bytes using one 8K × 8 SRAM
2.3 Display Modes
• 1 bit-per-pixel, black-and-white display mode
• 2/4 bits-per-pixel, 4/16 level gray shade display modes
• 2/4/8 bits-per-pixel, 4/16/256 level color display modes
• one 16 × 4 Look-Up Table provided for gray shade display modes
• three 16 × 4 Look-Up Tables provided for color display modes
• maximum 16 shades of gray
• maximum 256 simultaneous colors from a possible 4096 colors
• split screen display mode (see AUX[0A])
• virtual display mode (see AUX[0D])
Note: 256 color display mode support requires a 16-bit display memory interface.

S1D13503 Series Hardware Functional Specification
S18A-A-011-01 1-3
2.4 Display Support
• example resolutions:
– 1024 × 768 black-and-white
– 640 × 480 with 4 colors/grays
– 640 × 400 with 16 colors/grays
– 320 × 240 with 256 colors
• passive monochrome LCD panels:
– 4-bit single (4-bit data transfer)
– 8-bit single (8-bit data transfer)
– 8-bit dual (4-bit data transfer for each half panel)
• passive color LCD panels:
– 4-bit single (4-bit data transfer)
– 8-bit single (8-bit data transfer)
– 8-bit dual (4-bit data transfer for each half panel)
– 16-bit single (8-bit data transfer with external circuit)
– 16-bit dual (8-bit data transfer with external circuit)
See Section 9.5 on page 58 for complete details.
2.5 Power Management
• two software power-save modes
• low power consumption
• panel power control switch (see AUX[01] bit 4)

EPSON
1-4 S18A-A-011-01
3T
YPICAL
S
YSTEM
B
LOCK
D
IAGRAMS
The following figures show typical system implementations of the S1D13503.All of the following
block diagrams are shown without SRAM or LCD display. Refer to the interface specific Applica-
tion Notes for complete details.
16-Bit MC68000 MPU
Figure 3-1 16-Bit 68000 Series
(example implementation only - actual may vary)
Decoder
Decoder
A20 to A23
FC0 to FC1
A1 to A19
D0 to D15
DTACK#
UDS#
LDS#
AS#
R/W#
MEMCS#
IOCS#
AB1 to AB19
DB0 to DB15
READY
AB0
BHE#
IOR#
IOW#
A14 to A16
A10 to A19
MC68000 S1D13503

S1D13503 Series Hardware Functional Specification
S18A-A-011-01 1-5
MPU with READY (orWAIT#) Signal
Figure 3-2 8-Bit Mode, Example: Z80
(example implementation only - actual may vary)
Figure 3-3 16-Bit Mode, Example: i8086 (maximum mode)
(example implementation only - actual may vary)
Decoder
Decoder
MREQ#
MI#
IORQ#
A0 to A15
D0 to D7
WAIT#
WR#
RD#
RESET#
MEMCS#
IOCS#
AB0 to AB15
DB0 to DB7
READY
MEMW#
MEMR#
IOR#
IOW#
RESET
A10 to A15
Z80 S1D13503
S2#
S1#
S0#
A16 to A19
BHE#
AD0 to AD15
MEMR#
MEMW#
IOR#
IOW#
AB16 to AB19
AB0 to AB15
BHE#
MEMCS#
IOCS#
DB0 to DB15
RESET
READY
8086
(Maximum mode) 8288 S1D13503
CLK
S2#
S1#
S0#
DEN
DT/R
ALE
CLK
READY
RESET#
MRDC#
AMWC#
IORC#
AIOWC#
Decoder
A16
M/IO#
BHE#
A0 to A16
STB
Transceiver
D0 to D15
T
OE
8284A
CLK
RDY
READY
RESET#

EPSON
1-6 S18A-A-011-01
ISA Bus
Figure 3-4 8-Bit Mode (ISA)
(example implementation only - actual may vary)
Figure 3-5 16-Bit Mode (ISA)
(example implementation only - actual may vary)
REFRESH
SMEMW#
SMEMR#
IOCHRDY
SD0 to SD7
SA0 to SA19
AEN
IOW#
IOR#
RESET#
0WS#
MEMCS#
MEMW#
MEMR#
READY
DB0 to DB7
AB0 to AB19
IOCS#
IOW#
IOR#
RESET
SA13 to SA16
SA10 to SA15
SA(1 or 4) through SA9Optional
8-Bit ISA Bus S1D13503
Decoder
Decoder
Decoder
Decoder
Decoder
REFRESH
SMEMW#
SMEMR#
IOCHRDY
SD0 to SD15
SA0 to SA19
AEN
IOW#
IOR#
SBHE#
RESET#
IOCS16#
LA17 to LA23
MEMCS16#
MEMCS#
MEMW#
MEMR#
READY
DB0 to DB15
AB0 to AB19
IOCS#
IOW#
IOR#
BHE#
RESET
SA14 to SA16
SA10 to SA15
SA(1 or 4) through SA9
16-Bit ISA Bus S1D13503
Decoder
Decoder

S1D13503 Series Hardware Functional Specification
S18A-A-011-01 1-7
3.1 Internal Block Diagram
Figure 3-6 Internal Block Diagram
3.2 Functional Block Descriptions
Bus Signal Translation
According to configuration setting VD2, the Bus Signal Translation block translates either
MC68000 type MPU signals or MPU controlled by a READY type signals to internal bus interface
signals.
Control Registers
The register block contains the 16 internal control and configuration registers. These registers can be
accessed by either direct-mapping or using the built-in internal index register.
Sequence Controller
The Sequence Controller block generates horizontal and vertical display timings according to the
configuration registers settings.
LCD Panel Interface
The LCD Interface block performs frame rate modulation and output data pattern formatting for
both passive monochrome and passive color LCD panels.
Look-Up Table
The Look-Up Table block contains three 16 ×4-bit wide palettes. In gray shade modes, the “green”
palette can be configured for the re-mapping of 16 possible shades of gray. In color modes, all three
palettes can be configured for the re-mapping of 4096 possible colors. See Section 8.2, Look-Up
Table Architecture for details.
Port Decoder
According to configuration settings VD1, VD12–VD4, IOCS# and address lines AB9–1, the Port
Decoder validates a given I/O cycle.
Memory Decoder
According to configuration settings VD15–VD13, MEMCS# and address lines AB19–17, the Mem-
ory Decoder validates a given memory cycle.
Bus Signal
Translation Sequence Controller
Port
Decoder
Memory
Decoder Look-Up Table
LCD
Panel
Interface
Display Data
Formatter
Data Bus
Conversion Address Generator
MPU/CRT
Selector
SRAM Interface
Control Registers
Timing Generator
Power Save
Oscillator
IOR#, IOW#,
IOCS#, MEMCS#,
MEMR#, MEMW#,
BHE#, AB[19:0]
READY
VWE# VOE# VD[15:0]VA[15:0],
VSC0#, VSC1#
OSC1 OSC2
LCDENB
UD[3:0],
LD[3:0],
LP, YD,
XSCL,
WF (XSCL2)
DB[15:0]

EPSON
1-8 S18A-A-011-01
Data Bus Conversion
According to configuration settingVD0, the Data Bus Conversion Block maps the external data bus,
either 8-bit or 16-bit, into the internal odd and even data bus.
Address Generator
The Address Generator generates display refresh addresses to be used to access display memory.
MPU / CRT Selector
This block grants access to the display memory from either the MPU or the display refresh circuitry.
Display Data Formatter
The Display Data Formatter reads in the display data from the display memory and outputs the cor-
rect format for all supported gray shade and color selections.
Clock Inputs / Timing
The Timing block generates the internal master clock (MCLK) according to gray-level/color
selected and display memory interface. The master clock (MCLK) can be;
– MCLK = input clock
– MCLK = 1/2 input clock
– MCLK = 1/4 input clock
Refer to Section 9.2, “SRAM Access Time” for further details.
Pixel clock = input clock (fOSC)
SRAM Interface
This block generates the necessary signals to interface to the Display Memory (SRAM).

S1D13503 Series Hardware Functional Specification
S18A-A-011-01 1-9
4PINOUT DIAGRAM
Figure 4-1 S1D13503F00A Pinout Diagram
Note: Package type: 100 pin surface mount QFP5-S2
∗Pin 80 = WF in all display modes except format 1 for 8-bit single color panel.
∗Pin 80 = XSCL2 in format 1 for 8-bit single color panel.
INDEX
S1D13503F00A
DB7
VSS
VDD
DB8 DB9
DB10 DB11 DB12 DB13 DB14 DB15
AB0 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9
AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18
WF/XSCL2* LP YD LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 VCS1# VCS0# VWE# VA15 VA14 VA13 VA12 VA11 VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8 V
DD
V
SS
VD7
VD6
VD5
VD4
VD3
VD2
VD1
VD0
VA10
VA9
VA8
VA7
VA6
VA5
VA4
VA3
VA2
VA1
VA0
RESET
AB19
XSCL
LCDENB
VOE#
IOCS#
IOW#
IOR#
MEMCS#
MEMW#
MEMR#
READY
BHE#
OSC1
OSC2
DB0
DB1
DB2
DB3
DB4
DB5
DB6
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

EPSON
1-10 S18A-A-011-01
Figure 4-2 S1D13503F01A Pinout Diagram
Note: Package type: 100 pin surface mount QFP15-STD
∗Pin 77 = WF in all display modes except format 1 for 8-bit single color panel.
∗Pin 77 = XSCL2 in format 1 for 8-bit single color panel.
INDEX
S1D13503F01A
DB8 DB9
DB10 DB11 DB12 DB13 DB14 DB15
AB0 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9
AB10 AB11 AB12 AB13 AB14 AB15 AB16
YD LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 VCS1# VCS0# VWE# VA15 VA14 VA13 VA12 VA11 VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8
V DD
V SS
VD7
VD6
VD5
VD4
VD3
VD2
VD1
VD0
VA10
VA9
VA8
VA7
VA6
VA5
VA4
VA3
VA2
VA1
VA0
RESET
AB19
AB18
AB17
LP
WF/XSCL2*
XSCL
LCDENB
VOE#
IOCS#
IOW#
IOR#
MEMCS#
MEMW#
MEMR#
READY
BHE#
OSC1
OSC2
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VSS
VDD
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100