Epson S1R75801F00A User manual

MF1447-02
Technical Manual
S1R72803F00A
Technical Manual
IEEE1394 Controller
S1R75801F00A
Technical Manual
S1R72803F00A
EPSON Electronic Devices Website
ELECTRONIC DEVICES MARKETING DIVISION
First issue September,2001
Printed June, 2003 in Japan H A
4.5mm
Technical Manual
IEEE1394 Controller
S1R72803F00A
http://www.epsondevice.com/

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4.5mm
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All other product names mentioned herein are trademarks and/or registered trademarkes of their respective
companies.
This product uses SuperFlash®technology licensed from Silicon Storage Technology, Inc.
© SEIKO EPSON CORPORATION 2003, All rights reserved.

The information of the product number change
Starting April 1, 2001 the product number has been changed as listed below. Please use the new
product number when you place an order. For further information, please contact Epson sales
representative.
Configuration of product number
●DEVICES
S1 R 72803 F 00A1 00
Packing specification
Specifications
Shape (F:QFP)
Model number
Model name
(R:Exclusive use controller, Peripheral)
Product classification (S1:Semiconductors)

SPC7281F0A
– i –
Contents
1. DESCRIPTION .................................................................................................................................................. 1
2. FEATURES........................................................................................................................................................ 1
3. INTERNAL BLOCK DESCRIPTION .................................................................................................................. 3
3.1 BLOCK DIAGRAM ..................................................................................................................................... 3
3.2 BLOCK DIAGRAM DESCRIPTION............................................................................................................ 3
4. INTERNAL CONNECTION DIAGRAM .............................................................................................................. 4
5. PIN ASSIGNMENT DIAGRAM .......................................................................................................................... 5
6. PIN DESCRIPTION ........................................................................................................................................... 6
7. FUNCTIONAL DESCRIPTION ........................................................................................................................ 10
7.1 MEMORY MAP ........................................................................................................................................ 10
7.1.1 All Memory Space.......................................................................................................................... 10
7.1.2 IEEE1394LINK/Transaction Controller xCSBUF Area (SRAM)..................................................... 11
7.2 IEEE1394 PACKET FORMAT ................................................................................................................. 12
7.2.1 Transmit Packet Format ................................................................................................................ 12
7.2.2 Receive Packet Format.................................................................................................................. 14
7.3 IEEE1394 HARDWARE SBP-2 CONTROL ............................................................................................. 17
7.4 IDE INTERFACE CONTROL ................................................................................................................... 17
7.5 BUILT-IN CPU.......................................................................................................................................... 17
7.6 FLASH CONTROLLER ............................................................................................................................ 18
8. INTERNAL REGISTER.................................................................................................................................... 19
8.1 IEEE1394 LINK CONTROLLER REGISTER MAPPING ......................................................................... 19
8.1.1 Register Table ............................................................................................................................... 19
8.1.2 Register/Bit Table .......................................................................................................................... 22
8.1.3 Register Map ................................................................................................................................. 26
8.1.4 Detail Description of Register ........................................................................................................ 42
8.2 FLASH ROM CONTROL REGISTER ...................................................................................................... 88
9. ELECTRICAL CHARACTERISTICS................................................................................................................ 91
9.1 ABSOLUTE MAXIMUM RATINGS........................................................................................................... 91
9.2 RECOMMENDED OPERATING CONDITION ......................................................................................... 91
9.3 DC CHARACTERISTICS (ACCORDING TO RECOMMENDED OPERATING CONDITION) ................ 92
9.4 AC CHARACTERISTICS ......................................................................................................................... 94
9.4.1 Clock Timing .................................................................................................................................. 94
9.4.2 PHY-LINK Interface Timing ........................................................................................................... 95
9.4.3 IDE Interface Timing...................................................................................................................... 96
9.4.4 CPU Interface Timing .................................................................................................................. 104
10. EXAMPLES OF EXTERNAL CONNECTION FOR REFERENCE PURPOSES ........................................... 105
11. SHAPE OF PACKAGE .................................................................................................................................. 108

S1R72803F00A
EPSON 1
1. DESCRIPTION
The S1R72801F00A is a LINK/Transaction controller
based on the IEEE Std. 1394-1955, P1394a Draft 2.0. It
integrates a built-in CPU and Flash ROM, and also
integrates a part of transaction functions into hardware.
If you set a PageTable address and its size, it can
automatically fetch subsequent PageTables and transmit
data. It can offer a 1394 interface optimum to computer
peripherals in combination with the Cable PHY
Transceiver Arbiter based on the above standard.
The IDE interface complies with Ultra DMA mode 4
(ATA 66), offering a high transfer rate.
2. FEATURES
●LINK/Transaction Controller
LINK Layer
Ready for all two-way data transfer in Asynchronous
and Isochronous modes.
The built-in SRAM realized stable two-way data
transfer up to max. payload of 100Mbps, 200Mbps,
and 400Mbps.
Can automatically detect the Isochronous Resource
Manager by hardware.
Transaction Layer
Integratesa partoftransactionfunctionsinto hardware
to prevent deterioration of actual data transmission
rate due to the overhead of firmware (assure a special
area).
A header area is distinguished from a data area to
simplify communications with a higher rank layer.
Furthermore, it segments a data area to a stream area
and ORB area.
Adopts a ring buffer to the receive header area,
receive data area (receive stream area, receive ORB
area) and transmit data area (transmit stream area).
Can arbitrarily set the size of each area.
Automatically controls the Busy when hardware
receives data.
●SBP-2 Support
Can set an PageTable address and its size for the
SBP-2 to automatically perform subsequent Page
Table fetches and data transfers.
●PHY/LINK Interface
Ready for the P1394a.
Ready for the data transfer rate of 100/200/400Mbps.
Ready for isolation (bus holder integrated)
●IDE Interface
Ready for the PIO mode 0/1/2/3/4, multi-word DMA
mode 0/1/2, Ultra-DMA mode 0/1/2/3/4.
Voltage level is 3.3V (TTL) level.
5V level input can be possible (5V Tolerant)

S1R72803F00A
2EPSON
●Built-in CPU
Integration of a CPU eliminated the necessity of an
external CPU to control this IC.
CPU core: 32-bit RISC CPU S1C33000
Harvard architecture (Concurrency
of a fetch and load/store)
High speed/high performance:
Ready for operation with 25MHz
Command set: 16-bit fixed length, 105 types of basic
commands
Execution cycle:
Execution at one cycle/command
regarding a main command
AND/OR (MAC) operation:
16 bits ×16 bits + 64 bits, 2 clocks/
MAC
CPU Register: 16 32-bit general registers and 5 32-
bit special registers
Memory space:Linear space where 256-Mbyte (28-
bit) code, data, and I/O can be
mapped.
External bus interface:
Directly connects the external
memory of the memory area.
Programmable wait cycle (7 cycles,
Max.)
Enables handshake through the
XWAIT terminal.
Interrupt: Ready for reset, NMI, max. 128
external interrupts, 4 software
interrupts, and 2 exceptions
Reset, boot: Cold reset, hot reset
Built-in RAM: 8Kbytes for work
●Flash ROM
Integration of a Flash ROM eliminated the necessity
of a ROM to externally store programs.
• Memory structure:
Memory size 512K (32K × 16) bits
• Sector size: 512 words/sector
• Unit of erase: Per chip or sector
• Unit of write: Writing with words
• Erase/write time:
Chip erase time 100ms (Standard)
Sector erase time 20ms (Standard)
Write time: 15µs (Standard)
• Access time: 90nsec. (Max.)
• Reliability: No. of erase/write 1,000 times
Data retention: 10 years
●Others
A Boot ROM (4MBbytes, Max.) is connectable to
outside of this IC.
Supply voltage, 5.0V ±10% and 3.3V ±0.3V
184PinQFP (0.4mm pitch)
Not radiation resistant.
The CPU core built into this IC is an original 32-bit
RISC CPU from SEIKO EPSON. Regarding the CPU
core, refer to the S1C33208/204/202 Technical Manual
and S1C33 Family ASIC Macro Manual. The built-in
RAM is 8Kbytes.
Note: In the built-in CPU core, a DMA controller and
A/D converter are not integrated; this part is
different from the description on the DMA
controller and A/D converter given in Technical
Manual (and Macro Manual). A low speed
oscillation circuit (OSC1) is not available.

S1R72803F00A
EPSON 3
Fig. 3.1 Block diagram
3. INTERNAL BLOCK DESCRIPTION
3.1 BLOCK DIAGRAM
Intenal Packet Memory (8KByte)
Buffer I/F Maneger
IDE
FIFO
DMA
for ATF
DMA
for ITF
DMA
for RF
Rx
FIFO
IsoTx
FIFO
AsyncTx
FIFO
IDE
DMA
Register
for IDE
FLASH ROM
64KByte
(32KWord
X 16bit)
Internal
RAM
(8KByte)
C33_CORE
(CPU, BCU, ITC, CLG, DBG)
C33_PERI
(Prescaaler, 8-bit timer, 16bit timer, Clock timer,
Serial interface, Ports)
C33_SBUS C33 Core Block
C33 peripheral Block
C33 Macro Block
IDE
I/F TRAN &
SBP2
Control
Register
for TRAN&SBP2 Register
for 1394Tx/Rx
1394
LINK & TRAN
Core
1394
PHY/LINK
I/F
D [7:0]
CTL [1:0]
LREQ
LPS
LINKON
BHEN
XISO
SCLK
Register for
LINK&TRAN
AD [23:0]
DT [15:0]
XCE10_EX
XCE [9:4]
EA10MD [1:0]
XWAIT
EXT_MD
XRD
XWR
XWRH
BCLK
P[14:04]
SRDY
SCLK
SOUT
SIN
HDD [15:0]
HDMARQ
XHIOR
XHIOW
XHDMACK
HIORDY
HINTRQ
XHPDIAG
HDA [2:0]
XCS [1:0]
XHDASP
XHRST
EXCLK_EN
OSC3
PLLS1
PLLS0
ICEMD
DSIO
X2SPD
XNMI
XREST
TVEP
C33 Internal Memory Block
CORE PADPERI PAD
3.2 BLOCK DIAGRAM DESCRIPTION
●C33 CORE Block
The C33 CORE Block consists of the function block-
C33_CORE-thatincludestheCPU, BCU(bus control
unit), ITC (interrupt controller), CLG (clock
generator), and DBG (debug unit), the external
interface I/O pad block-PAD_CORE,
PAD_CORE_OPTION-, and the block to interface
with the peripheral circuits on the chip -SBUS-.
●C33_PERI Block (C33 peripheral circuit block)
The C33_PERI Block consists of the PSC (prescaler),
6-channel T8 (8-bit programmable timer), WDT
(watch dog timer), 6-channel T16 with an event
counter (16-bit programmable timer), 4-channel SIO
(serial interface), input and I/O ports, and CTM
(clock timer).
●Internal RAM Block
SRAM for the built-in memory area (Area 0).
●Internal Flash Block
Flash for the built-in memory area (Area 10).

S1R72803F00A
4EPSON
Fig. 4.1 Internal connection diagram
4. INTERNAL CONNECTION DIAGRAM
U_AD<23:0>
XRESET
AD<23:00>
DT<15:00>
XCE10EX
XCE9
XCE8
XCE6
XRD
XWRL
XWRH
EA10MD2
EA10MD1
EA10MD0
BCLK C33 Core
XNMI
X2SPDX
ICEMD
DSIO
OSC3
EXCLK_EN
PLLC
PLLS1
PLLS0
U_DT<15:0>
xCSREG<XCE4>
xCSBUF<XCE7>
xCSFREG<XCE5>
LPS(P35) PD(P34) CNA(K64) K66 K67 P20 P21 P22 P23
xCSFLS<XCE10>
xWRL
xRD
xWait
xRST
xINT(K65)
SLEEP(P33)
U_AD<12:0>
U_DT<7:0>
xCSREG
xCSBUF
xWRL
xRD
xWait
xRST
xINT
SLEEP
U_AD<14:0>
U_DT<15:0>
xCSFREG
xWRL
U_AD<14:0>
U_DT<15:0>
Flash ROM (64KB)
FLASH Controller
1394LINK Core
xCS
xRD
xRD
HDD<15:0>
HDA<2:0>
XHCS<1:0>
XHRST
XHIOW
BHEN MonxWait MonxInt XISO LINKON LPS LREQ CTL<1:0> D<7:0> SCLK
XHIOR
HDMARQ
XHDMACK
HIORDY
XHPDIAG
XHDASP
HINTRQ
P10 P11 P12 P13 P14 P00 P01 P02 P03 P04 P05 P06 P07

S1R72803F00A
EPSON 5
5. PIN ASSIGNMENT DIAGRAM
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
LV
DD
N.C.
DT0 DT1
HV
DD
DT2 DT3 DT4 DT5 DT6 DT7 DT8
V
SS
DT9
DT10 DT11 DT12 DT13 DT14 DT15
HV
DD
XWRH
XWRL
XRD
AD0 AD1 AD2 AD3
V
SS
AD4 AD5 AD6 AD7 AD8 AD9
AD10
HV
DD
AD11 AD12 AD13 AD14 AD15 AD16 AD17
N.C.
V
SS
138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100
99 98 97 96 95 94 93
V
SS
N.C. P21 P20 XCE10EX XCE9 MonxWait XCE6 HV
DD
TO0 TO1 TO2 TO3 TO4 TO5 TO6 TO7 TI8 MonxInt V
SS
V
SS
V
SS
EXCLK_EN LREQ LV
DD
SCLK V
SS
CNA XISO BHEN CTL0 CTL1 D0 D1 D2 LV
DD
D3 D4 D5 D6 D7 PD LPS LINKON N.C. LV
DD
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
V
SS
N.C.
XHRST
HDD7
HDD8
HDD6
HDD9
HDD5
HDD10
HV
DD
HDD4
HDD11
HDD3
HDD12
HDD2
HDD13
HDD1
V
SS
HDD14
HDD0
HDD15
HDMARQ
XHIOW
XHIOR
HIORDY
HV
DD
XHDMACK
HINTRQ
HDA1
XHPDIAG
HDA0
HDA2
XHCS0
XHCS1
TVEP
V
SS
XHDASP
FLSTST
AD23
AD22
AD21
AD20
AD19
AD18
N.C.
LV
DD
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
LV
DD
N.C.
P22
P23
K66
K67
XWAIT
P00
P01
V
SS
P02
P03
P04
P05
P06
P07
X2SPDX
RAMTST
V
SS
PLLC
V
SS
PLLS0
PLLS1
EA10MD0
EA10MD1
EA10MD2
HV
DD
P14
P13
P12
P11
V
SS
OSC3
NC
V
SS
P10
DSIO
HV
DD
XNMI
XRESET
ICEMD
V
SS
HCLK
BCLK
N.C.
V
SS
INDEX
EPSON
S1R72803F00A
TOP View

S1R72803F00A
6EPSON
6. PIN DESCRIPTION
Control signals with an “X” as the first character of a pin name are low active. (Excluding X2SPD)
Pin Name PIN I/O Reset Pin Function Remarks
1394PHY interface (LVDD )
D7 98 B Hi-Z (MSB)
D6 99 B Hi-Z
D5 100 B Hi-Z
D4 101 B Hi-Z Data Bus with PHY Drive Ability 6mA
D3 102 B Hi-Z
D2 104 B Hi-Z Schmitt Input (Bus Holder)
D1 105 B Hi-Z
D0 106 B Hi-Z (LSB)
CTL1 107 B Hi-Z Control Signal with PHY Drive Ability 6mA
CTL0 108 B Hi-Z Schmitt Input (Bus Holder)
LREQ 115 O Lo LINK Request Signal to PHY Drive Ability 6mA
LPS 96 O Hi LINK Power Status Signal to PHY Drive Ability 6mA
LINKON 95 I – LINK ON Signal from PHY Schmitt Input (Bus Holder)
XISO 110 I – Setting should be made according to CMOS Input
the construction of isolation buffer
between PAY and LINK
Set to H level in case of DC
connection and Single capacitor AC
connection. And Annex-J Isolation
connection cannot be used.
BHEN 109 I – Bus Holder Enable Signal
H: Single capacitor AC connection
L: DC connection
CNA 111 I – Cabele Not Active Schmitt Input (Bus Holder)
PD 97 O Power Down Enable Drive Ability 6mA
SCLK 113 I – Clock Signal from PHY (49.576MHz) Schmitt Input (Bus Holder)
IDE Interface (LVDD)
HDD15 72 B Hi-Z (MSB)
HDD14 74 B Hi-Z
HDD13 77 B Hi-Z
HDD12 79 B Hi-Z
HDD11 81 B Hi-Z
HDD10 84 B Hi-Z
HDD9 86 B Hi-Z 5V Tolerant
HDD8 88 B Hi-Z IDE Data Bus Drive Ability 2mA
HDD7 89 B Hi-Z Pull Down HDD7 at 10kΩ
HDD6 87 B Hi-Z
HDD5 85 B Hi-Z
HDD4 82 B Hi-Z
HDD3 80 B Hi-Z
HDD2 78 B Hi-Z
HDD1 76 B Hi-Z
HDD0 73 B Hi-Z (LSB)
HDMARQ 71 B Hi-Z IDE DMA Request Signal 5V Tolerant, Drive Ability
2mA, Schmitt Input
XHIOW 70 B Hi-Z IDE Write Signal 5V Tolerant, Drive Ability
2mA, Schmitt Input
XHIOR 69 B Hi-Z IDE Read Signal 5V Tolerant, Drive Ability
2mA, Schmitt Input
HIORDY 68 I – IDE IORDY Signal 5V Tolerant, Drive Ability
2mA, Schmitt Input
XHDMACK 66 B Hi-Z IDE DMA Acknowledge Signal 5V Tolerant, Drive Ability
2mA, Schmitt Input
HINTRQ 65 I – IDE Interrupt Signal 5V Tolerant, Schmitt Input
XHPDIAG 63 I – IDE PDIAG Signal 5V Tolerant, Schmitt Input

S1R72803F00A
EPSON 7
Pin Name PIN I/O Reset Pin Function Remarks
IDE Interface (LVDD)
HDA2 61 Otr Hi-Z (MSB) Drive Ability 2mA, Tristate
HDA1 64 Otr Hi-Z IDE Address Signal Drive Ability 2mA, Tristate
HDA0 62 Otr Hi-Z (LSB) Drive Ability 2mA, Tristate
XHCS1 59 Otr Hi-Z IDE Chip Select Signal Drive Ability 2mA, Tristate
XHCS0 60 Otr Hi-Z IDE Chip Select Signal Drive Ability 2mA, Tristate
XHDASP 56 I – IDE DASP Signal 5V Tolerant, Schmitt Input
XHRST 90 Otr Hi-Z IDE Reset Signal Drive Ability 2mA, Tristate
C33 External Interface (HVDD)
AD23 54 O (MSB)
AD22 53 O
AD21 52 O
AD20 51 O
AD19 50 O
AD18 49 O
AD17 44 O
AD16 43 O
AD15 42 O CPU Address Bus
AD14 41 O
AD13 40 O
AD12 39 O
AD11 38 O
AD10 36 O
AD9 35 O
AD8 34 O
AD7 33 O
AD6 32 O
AD5 31 O
AD4 30 O
AD3 28 O
AD2 27 O
AD1 26 O
AD0 25 O (LSB)
DT15 20 B Hi-Z (MSB)
DT14 19 B Hi-Z
DT13 18 B Hi-Z
DT12 17 B Hi-Z
DT11 16 B Hi-Z
DT10 15 B Hi-Z
DT9 14 B Hi-Z
DT8 12 B Hi-Z
DT7 11 B Hi-Z CPU Data Buss Pull Up Resistor Intgrated
DT6 10 B Hi-Z
DT5 9 B Hi-Z
DT4 8 B Hi-Z
DT3 7 B Hi-Z
DT2 6 B Hi-Z
DT1 4 B Hi-Z
DT0 3 B Hi-Z (LSB)

S1R72803F00A
8EPSON
Pin Name PIN I/O Reset Pin Function Remarks
C33 External Interface (HVDD)
P07 154 B General I/O Port 07 Pull Up Resistor Integrated
P06 153 B General I/O Port 06 Pull Up Resistor Integrated
P05 152 B General I/O Port 05 Pull Up Resistor Integrated
P04 151 B General I/O Port 04 Pull Up Resistor Integrated
SRDY(P03) 150 B Serial I/F Ready Signal Input Pull Up Resistor Integrated
Pin-cum-General I/O Port 03
SCLK(P02) 149 B Serial I/F Clock Input Pull Up Resistor Integrated
Pin-cum-General I/O Port 02
SOUT(P01) 147 B Serial I/F Data Output Pull Up Resistor Integrated
Pin-cum-General I/O Port 01
SIN(P00) 146 B Serial I/F Data Input Pull Up Resistor Integrated
Pin-cum-General I/O Port 00
K67 144 I Generall Inut Port 67 Pull Up Resistor Integrated
K66 143 I Generall Inut Port 66 Pull Up Resistor Integrated
P23 142 B Generall I/O Port 23 Pull Up Resistor Integrated
P22 141 B Generall I/O Port 22 Pull Up Resistor Integrated
P21 136 B Generall I/O Port 21 Pull Up Resistor Integrated
P20 135 B Generall I/O Port 20 Pull Up Resistor Integrated
XCE10_EX 134 O Hi External Memory Area 10 Chip Enable
XCE9 133 O Hi Area 9 Chip Enable
XCE6 131 O Hi Area 6 Chip Enable
EA10M2 164 I Area 10 Boot Mode Select 2
EA10M1 163 I Area 10 Boot Mode Select 1 Pull Up Resistor Integrated
EA10M0 162 I Area 10 Boot Mode Select 0 Pull Up Resistor Integrated
XWAIT 145 I Wait Cycle Input
XRD 24 O Hi Read Signal
XWRH 22 O Hi Higher Order Byte Write Signal
XWRL 23 O Hi Lower Order Byte Write Signal
BCLK 182 O Bus Clock Signal
C33 External Interface (LVDD)
P14 166 B General I/O Port 14 (For ICD)
P13 167 B General I/O Port 13 (For ICD)
P12 168 B General I/O Port 12 (For ICD)
P11 169 B General I/O Port 11 (For ICD)
P10 174 B General I/O Port 10 (For ICD)
DSIO 175 B Serial I/O Pin for Debug: Pull Up Resister Integrated
Use for communication with ICD33.
Clock Generator Pin
OSC3 171 I MCU Clock Input LVDD Input
Crystal Oscillator
PLLS1 161 I PLL Set Pin 1 HVDD Input
PLLS0 160 I PLL Set Pin 0 HVDD Input
PLLC 158 – Capacitor Connection Pin for PLL

S1R72803F00A
EPSON 9
Pin Name PIN I/O Reset Pin Function Remarks
Other Pins
ICEMD 179 I Hi-Impedance Control: Set Hi-Z
Pull Down Resistor Integrated
for all outputs.
X2PSDX 155 I Double-speed mode setting pin HVDD Input
HIGH : BCLK = CPU Clock
LOW : BCLK = Half CPU Clock
XNMI 177 I NMIInput Pin HV DD Input, Pull Up Resistor Integrated
XRESET 178 I Initial Reset HV DD Input, Pull Up Resistor Integrated
HCLK 181 O Half SCLK Frequency Division Output LVDD Output
EXCLK_EN 116 I MCU clock switch pin LVDD Input
HIGH:Internal CLK
LOW:OSC3 Input
TVEP 58 – Flash Test Pin Connect to HV DD when it is mounted.
Test Pin
TI8 121 I Schmitt Input (Bus Holder)
TO7 122 O – (MSB)
TO6 123 O –
TO5 124 O –
TO4 125 O – Test Output Pin Drive Ability 1mA
TO3 126 O –
TO2 127 O –
TO1 128 O –
TO0 129 O – (LSB)
FLSTST 55 I – Built-in Flash Test Pin Pull Down Resistor Integrated
RAMTST 156 I – Built-in SRAM Test Pin Pull Down Resistor Integrated
MonxWait 132 O – Internal Logic xWait Monitor Pin
MonxInt 120 O – Internal Logic xINT Monitor Pin
Power Pin
HVDD – P HIGH Power (5V)
5,21,37,67,83,130,165,176 (8 Pins)
LVDD – P LOW Power (3.3V)
1,47,93,103,114,139 (6 Pins)
VSS – P GND
13,29,46,57,75,92,112,117,118,119,138,
148,157,159,170,173,180,184 (18 Pins)
N.C. Pin
N.C. – – 2,45,48,91,94,137,140,172,183 (9 Pins)
Table 6.1 Settings of EA10M2, EA10M1, and EA10M0 (Area 10 Boot Mode)
P_EA10M2 P_EA10M1 P_EA10M0 Function
1 1 1 Built-in Flash Boot Mode
0 1 1 External ROM Mode
Note) Other settings are not available on this IC.

S1R72803F00A
10 EPSON
7. FUNCTIONAL DESCRIPTION
7.1 MEMORY MAP
7.1.1 All Memory Space
Area Address
Area 0 0x000000 CPU-integrated RAM (8KB)
0x002000 (Mirror of CPU-integrated RAM)
Area 1 0x030000 (Mirror of CPU-integrated Peripheral Circuit Control Register)
0x040000 CPU-integrated Peripheral Circuit Control Register
0x050000 (Mirror of CPU-integrated Peripheral Circuit Control Register)
Area 2 0x060000 Reserved
Area 3 0x080000 Reserved
Area 4 0x100000 IEEE1394LINK/Transaction Controller
x CSREG Area (Control Register)
0x100080 Reserved
Area 5 0x200000 Flash ROM Control Register
0x200008 Reserved
Area 6 0x300000 Reserved
Area 7 0x400000 IEEE1394LINK/Transaction Controller
xCSBUF Area (SRAM: 8KB)
0x402000 Reserved
Area 8 0x600000 Reserved
Area 9 0x800000 Reserved
Area 10 0xC00000 Internal Flash ROM (64KB)
0xC10000 External ROM
Reserved (4MB)
0xFFFFFF

S1R72803F00A
EPSON 11
• All RAM areas are accessible from the CPU by direct
addressing.
• Hardware DMA is possible to the IDE I/F for the
RxStreamArea and TXStreamArea.
• HW_PageTableArea (the equivalent of 24 pages)
and HW_RxHeaderArea and HW_TXHeaderArea
(the equivalent of 1 header, respectively) are assured.
TheRxORBandTxORBareas areusable byfirmware
alone.
• The RxHeaderArea, RxORBArea, TxORB,
TXStreamArea and RxStreamArea are RingBuffers.
Even at the time of execution of data transmission/
reception according to 1394 or IDE DMA, data
among the areas are guaranteed by hardware . (The
size of each RingBuffer is variable by settings on the
TxStreamAreaStart, TxStreamAreaEnd, and
RxStreamAreaStart.)
• The TxStreamArea and RxStreamArea is usable as
one StreamArea by overlaying them.
• The Post**Ptr and Used**Ptr of the RxHeaderArea,
RxORBArea, TxStreamArea, and RxStreamArea
monitor the used condition in each Area.
(In the case of the Rx of 1394, the free space of the
above two is monitored and the busy_A, B, X is
controlled by hardware.)
• By controlling the above functions from the TRAN &
SBP2 Control Block, a PageTable fetch and data
transfer according to SBP-2 are executable by
hardware.
7.1.2 IEEE1394LINK/Transaction Controller xCSBUF Area (SRAM)
TxHeaderArea
8KBytes
0x400000
0x4000C0
0x4000E0
0x400100

(RxHeaderAreaStart)
RxORBAreaStart
TxHeaderAreaStart
(TxHeaderAreaStart + 0x0040)
TxStreamAreaStart
TxStreamAreaEnd 
RxStreamAreaStart

HW_RxHeaderArea
HW_PageTableArea
HW_TxHeaderArea
RxHeaderArea
(RingBuffer)

RxORBArea
(RingBuffer)
TxHeaderArea (2 Headers)
TxORBArea
(RingBuffer)
NotUsed
RxStreamArea
(RingBuffer)
0x401FFF

IDE –>1394 DMA Area
1394 –>IDE DMA Area
used Asyncronouse only
TxAreaStart
+ 0x20
+ 0x40
AsyTxPktHdr 1
AsyTxPktHdr 0 AsyTxPktHdr 0
TxAreaStart

+ 0x20
+ 0x30
+ 0x40
used Isocronouse
IsoTxPktHdr 0
IsoTxPktHdr 1
TxStreamArea
(RingBuffer)

S1R72803F00A
12 EPSON
7.2 IEEE1394 PACKET FORMAT
7.2.1 Transmit Packet Format
(1) TxAsyncronousePacket <3> QuadReadReq, WriteResp
(2) TxAsyncronousePacket <4> QuadWriteReq, QuadReadResp, BlockReadReq
0
1
2
3
4
5
6
7
b.31 24 23 16 15 8 b.07
1
2
DestinationID
Sbid
speed
–
–– tl rt pri
ACK
tcode
(MSB)
(MSB)
(LSB)
(LSB)
PacketTypeSpecInfo
reserved
1QuadReadReq (tcode : 0x4)
DestinationID DestinationOffset
1
2rcode
2WriteResp (tcode : 0x2)
DestinationID reserved
0
1
2
3
4
5
6
7
b.31 24 23 16 15 8 b.07
1
2
3
DestinationID
Sbid
speed tl rt pri
ACK
tcode
(MSB)
(MSB)
(LSB)
(LSB)
PacketTypeSpecInfo
PacketTypeSpecQuadletData
reserved
1QuadWriteReq (tcode : 0x0)
DestinationID DestinationOffset
QuadletData
1
2
3
2QuadReadResp (tcode : 0x6)
DestinationID reserved
QuadletData
1
2
3
(MSB) (LSB)
3BlockReadReq (tcode : 0x5)
DestinationID DestinationOffset
DataLength ExtendedTcode
rcode
––
–

S1R72803F00A
EPSON 13
(3) TxAsyncronousePacket <5> BlockWriteReq, BlockReadResp, LockReq, LockResp
(4) TxAsyncronousePhyPacket (tcode : 0xE)
(5) TxIsocoronousePacket (tcode : 0xA)
Name Bit count Description
ACK 4 Received AckCode
4'h1 ask_complete
4'h2 ask_pending
4'h4 ask_busy_X
4'h5 ask_busy_A
4'h6 ask_busy_B
4'hB ask_tardy
4'hC ask_confilict_error
4'hD ask_data_error
4'hE ask_type_error
4'hF ask_address_error
All Other Value Reserved
Transmit Packet Common Format
Name Bit count Description
speed 3 Speed Code
3'b000 S100
3'b001 S200
3'b010 S400
All Other Value Reserved
Sbid 1 Souce Bus ID 0:3FFh, 1:Source ID
0
1
2
3
4
5
6
7
b.31 24 23 16 15 8 b.07
1
2
DestinationID
DataLength
speed tl rt pri
ACK
tcode
(MSB)
(MSB)
(LSB)
(LSB)
PacketTypeSpecInfo
*DataPointer
reserved
ExtendedTcode
1BlockWriteReq
LockReq (tcode : 0x1)
(tcode : 0x9)
DestinationID DestinationOffset
1
2rcode
2BlockReadResp
LockResp (tcode : 0x7)
(tcode : 0xB)
DestinationID reserved
––
–
Sbid
0
1
2
3
4
5
6
7
b.31 24 23 16 15 8 b.07
0x0 reserved reservedtcode (0xE)
PhyPacket
reserved
––
Sbid
0
1
2
3
b.31 24 23 16 15 8 b.07
DataLength speed tag channel sytcode (0xA)
*DataPointer
reserved
reserved
––
Sbid

S1R72803F00A
14 EPSON
7.2.2 Receive Packet Format
(1) RxAsyncronousePacket <4> QuadReadReq, WriteResp
(2) RxAsyncronousePacket <5> QuadWriteReq, QuadReadResp, BlockReadReq
0
1
2
3
4
5
6
7
b.31 24 23 16 15 8 b.07
2
3
DestinationID
SourceID
speed tl BT 0 BC 0AS rt ACK
pri
tcode
(MSB)
(MSB)
(LSB)
(LSB)
PacketTypeSpecInfo
reserved
1QuadReadReq (tcode : 0x4)
SourceID DestinationOffset
2
3rcode
2WriteResp (tcode : 0x2)
SourceID reserved
––
0
1
2
3
4
5
6
7
b.31 24 23 16 15 8 b.07
DestinationID
SourceID
speed tl BT 0 BC 0AS rt ACK
pri
tcode
(MSB) (LSB)
PacketTypeSpecInfo
PacketTypeSpecQuadData
reserved
2
3
4
(MSB) (LSB)
1QuadWriteReq (tcode : 0x0)
SourceID DestinationOffset
QuadletData
2
3
4
2QuadReadResp (tcode : 0x6)
SourceID reserved
QuadletData
2
3
4
(MSB) (LSB)
3BlockReadReq (tcode : 0x5)
SourceID DestinationOffset
DataLength ExtendedTcode
rcode
––

S1R72803F00A
EPSON 15
(3) RxAsyncronousePacket <6> BlockWriteReq, BlockReadResp, LockReq, LockResp
(4) RxAsyncronousePhyPacket Normal (tcode : 0xE)
(5) SelfIDPacket Received SelfID packets between BusReset and 1st-ArbRstGap (tcode : 0xE)
0
1
2
3
4
5
6
7
b.31 24 23 16 15 8 b.07
2
3
DestinationID
SourceID
DataLength
speed tl BT 0 BC 0AS rt ACK
pri
tcode
(MSB)
(MSB)
(LSB)
(LSB)
PacketTypeSpecInfo
*DataPointer ExtendedTcode
reserved
1BlockWriteReq
LockReq (tcode : 0x1)
(tcode : 0x9)
SourceID DestinationOffset
2
3rcode
2BlockReadResp
LockResp (tcode : 0x7)
(tcode : 0xB)
SourceID reserved
––
0
1
2
3
4
5
6
7
b.31 24 23 16 15 8 b.07
0 x 0 BT 0 1 0AS ACK
reserved
tcode (0xE)
PhyPacket
reserved
reserved
–––
0
1
2
3
4
5
6
7
b.31 24 23 16 15 8 b.07
BT 1 1 0AS ACK
reserved
tcode (0xE)
*DataPointer
reserved
reserved
DataLength ––

S1R72803F00A
16 EPSON
(6) RxIsocronousePacket (tcode : 0xA)
0
1
2
3
4
5
6
7
b.31 24 23 16 15 8 b.07
BT 0 1 0AS ACK
sy
tcode (0xA)tag channel
*DataPointer
reserved
speed
DataLength
0b.31 24 23 16 15 8 b.07
BT SI BCHCAS ACK
speed
–
–––
––
Receive Packet Common Format
Name Bit count Description
speed 3 Speed Code (Note 1)
AS 1 AreaStatus bit (1: StreamArea, 0: ORBArea)
BT 1 Bit which toggles during the BusReset period.
SI 1 Whether the received packet is a Self ID packet
BC 1 Whether the received packet is a Broadcast packet.
HC 1 Presence/absence of the Header CRC error (1: Packet disabled)
ACK 4 Transmitted AckCode (Note 2)
PSTS 4 AckCode which was scheduled to be transmitted (Note 2)
(Note 1) Refer to the Transmit Packet Common spd (speed code).
(Note 2) Refer to the Transmit Packet Common Ack (AckCode).