Epson S1D13505F00A User manual

MF1151-05
S1D13505F00A Technical Manual
Technicl Manual
S1D13505F00A
Technical Manual
Embedded RAMDAC LCD/CRT Controller
S1D13505F00A
EPSON Electronic Devices Website
ELECTRONIC DEVICES MARKETING DIVISION
http://www.epson.co.jp/device/
First issue February,1999 M Printed April, 2001 in Japan C B
This manual was made with recycle papaer, and printed using soy-based inks.
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NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written
permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material
or due to its application or use in any product or circuit and, further, there is no representation that this material
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©SEIKO EPSON CORPORATION 2001, All rights reserved.
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Comparison table between new and previous number of Evaluation Boards
S5U 13705 P00C
Specification
Corresponding model number (13705: for S1D13705)
Product classification (S5U: development tool for semiconductor)
S1 D 13706 F 00A0 00
The information of the product number change
Starting April 1, 2001, the product number will be changed as listed below. To order from April 1,
2001 please use the new product number. For further information, please contact Epson sales
representative.
Devices
Configuration of product number
Comparison table between new and previous number
Packing specification
Specification
Package (B: CSP, F: QFP)
Corresponding model number
Model name (D: driver, digital products)
Product classification (S1: semiconductor)
Evaluation Board
Previous No.
SED1335 Series
SED1335D0A
SED1335F0A
SED1335F0B
S1D13305 Series
S1D13305D00A
S1D13305F00A
S1D13305F00B
New No.
Previous No.
SED135x Series
SED1353D0A
SED1353F0A
SED1353F1A
SED1354F0A
SED1354F1A
SED1354F2A
SED1355F0A
SED1356F0A
S1D1350x Series
S1D13503D00A
S1D13503F00A
S1D13503F01A
S1D13504F00A
S1D13504F01A
S1D13504F02A
S1D13505F00A
S1D13506F00A
New No.
Previous No.
SED137x Series
SED1374F0A
SED1375F0A
SED1376B0A
SED1376F0A
SED1378 Series
S1D1370x Series
S1D13704F00A
S1D13705F00A
S1D13706B00A
S1D13706F00A
S1D13708 Series
New No.
Previous No.
SED13Ax Series
SED13A3F0A
SED13A3B0B
SED13A4B0B
S1D13A0x Series
S1D13A03F00A
S1D13A03B00B
S1D13A04B00B
New No.
Previous No.
SED138x Series
SED1386F0A S1D1380x Series S1D13806F00A
New No.
• S1D1350x Series
• S1D13305 Series • S1D1370x Series
• S1D13A0x Series
• S1D1380x Series
• S1D1350x Series
• S1D1370x Series • S1D1380x Series
• S1D13A0x Series
Previous No.
SDU1353#0C
SDU1354#0C
SDU1355#0C
SDU1356#0C
S5U13503P00C
S5U13504P00C
S5U13505P00C
S5U13506P00C
New No. Previous No.
SDU1374#0C
SDU1375#0C
SDU1376#0C
SDU1376BVR
SDU1378#0C
S5U13704P00C
S5U13705P00C
S5U13706P00C
S5U13706B32R
S5U13708P00C
New No. Previous No.
SDU1386#0C S5U13806P00C
New No.
Previous No.
SDU13A3#0C
SDU13A4#0C S5U13A03P00C S5U13A04P00C
New No.
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S1D13505F00ATechnical Manual
HARDWARE FUNCTIONAL SPECIFICATION
PROGRAMMING NOTES AND EXAMPLES
UTILITIES
S5U13505P00C ISA BUS EVALUATION
BOARD USER’S MANUAL
APPLICATION NOTES
WINDOWS
®
CE DISPLAY DRIVERS
TOBIRA.fm Page 1 Sunday, April 15, 2001 6:24 PM
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S1D13505F00A
Hardware Functional
Specification
Embedded RAMDAC LCD/CRT Controller
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CONTENTS
S1D13505F00A HARDWARE FUNCTIONAL
EPSON
1-i
SPECIFICATION (X23A-A-001-12)
Contents
Table of Contents
1I NTRODUCTION .........................................................................................................................1-1
1.1 Scope ............................................................................................................................................1-1
1.2 Overview Description ....................................................................................................................1-1
2F
EATURES
...............................................................................................................................1-2
2.1 Memory Interface ..........................................................................................................................1-2
2.2 CPU Interface................................................................................................................................1-2
2.3 Display Support.............................................................................................................................1-2
2.4 Display Modes...............................................................................................................................1-3
2.5 Display Features ...........................................................................................................................1-3
2.6 Clock Source.................................................................................................................................1-3
2.7 Miscellaneous................................................................................................................................1-3
3T YPICAL S YSTEM I MPLEMENTATION D IAGRAMS ...........................................................................1-4
4I NTERNAL D ESCRIPTION ............................................................................................................1-9
4.1 Block Diagram Showing Datapaths...............................................................................................1-9
4.2 Block Descriptions.........................................................................................................................1-9
Register......................................................................................................................................1-9
Host Interface.............................................................................................................................1-9
CPU R/W ...................................................................................................................................1-9
Memory Controller......................................................................................................................1-9
Display FIFO..............................................................................................................................1-9
Cursor FIFO.............................................................................................................................1-10
Look-Up Tables........................................................................................................................1-10
CRTC.......................................................................................................................................1-10
LCD Interface...........................................................................................................................1-10
DAC .........................................................................................................................................1-10
Power Save..............................................................................................................................1-10
Clocks ......................................................................................................................................1-10
5P INS .....................................................................................................................................1-11
5.1 Pinout Diagram............................................................................................................................1-11
5.2 Pin Description ............................................................................................................................1-12
Host Interface...........................................................................................................................1-13
Memory Interface.....................................................................................................................1-17
LCD Interface...........................................................................................................................1-18
CRT Interface...........................................................................................................................1-18
Miscellaneous ..........................................................................................................................1-19
5.3 Summary of Configuration Options .............................................................................................1-20
5.4 Multiple Function Pin Mapping ....................................................................................................1-20
5.5 CRT Interface..............................................................................................................................1-23
6 D.C. C HARACTERISTICS .........................................................................................................1-24
7 A.C. C HARACTERISTICS .........................................................................................................1-26
7.1 CPU Interface Timing..................................................................................................................1-26
SH-4 Interface Timing..............................................................................................................1-26
SH-3 Interface Timing..............................................................................................................1-28
MC68K Bus 1 Interface Timing (e.g. MC68000)......................................................................1-30
MC68K Bus 2 Interface Timing (e.g. MC68030)......................................................................1-32
PC Card Interface Timing ........................................................................................................1-34
Generic Interface Timing..........................................................................................................1-36
MIPS/ISA Interface Timing.......................................................................................................1-38
Philips Interface Timing (e.g. PR31500/PR31700) ..................................................................1-40
Toshiba Interface Timing (e.g. TX3912) ..................................................................................1-42
PowerPC Interface Timing (e.g. MPC8xx, MC68040, Coldfire)...............................................1-45
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CONTENTS
1-ii
EPSON
S1D13505F00AHARDWAREFUNCTIONAL
SPECIFICATION (X23A-A-001-12)
7.2 Clock Input Requirements...........................................................................................................1-46
7.3 Memory Interface Timing.............................................................................................................1-47
EDO-DRAM Read/Write/Read-Write Timing............................................................................1-47
EDO-DRAM CAS Before RAS Refresh Timing........................................................................1-49
EDO-DRAM Self-Refresh Timing.............................................................................................1-50
FPM-DRAM Read / Write / Read - Write Timing......................................................................1-51
FPM-DRAM CAS Before RAS Refresh Timing........................................................................1-53
FPM-DRAM Self-Refresh Timing.............................................................................................1-54
7.4 Power Sequencing ......................................................................................................................1-55
LCD Power Sequencing...........................................................................................................1-55
Power Save Status ..................................................................................................................1-56
7.5 Display Interface..........................................................................................................................1-57
4-Bit Single Monochrome Passive LCD Panel Timing.............................................................1-57
8-Bit Single Monochrome Passive LCD Panel Timing.............................................................1-59
4-Bit Single Color Passive LCD Panel Timing .........................................................................1-61
8-Bit Single Color Passive LCD Panel Timing (Format 1)........................................................1-63
8-Bit Single Color Passive LCD Panel Timing (Format 2)........................................................1-65
16-Bit Single Color Passive LCD Panel Timing .......................................................................1-67
8-Bit Dual Monochrome Passive LCD Panel Timing................................................................1-69
8-Bit Dual Color Passive LCD Panel Timing............................................................................1-71
16-Bit Dual Color Passive LCD Panel Timing..........................................................................1-73
16-Bit TFT/D-TFD Panel Timing ..............................................................................................1-75
CRT Timing..............................................................................................................................1-77
8R EGISTERS ............................................................................................................................1-79
8.1 Register Mapping ........................................................................................................................1-79
8.2 Register Descriptions ..................................................................................................................1-80
Revision Code Register ...........................................................................................................1-80
Memory Configuration Registers .............................................................................................1-80
Panel/Monitor Configuration Registers ....................................................................................1-81
Display Configuration Registers...............................................................................................1-86
Clock Configuration Register ...................................................................................................1-90
Power Save Configuration Registers.......................................................................................1-91
Miscellaneous Registers..........................................................................................................1-92
Look-Up Table Registers .........................................................................................................1-97
Ink/Cursor Registers ................................................................................................................1-98
9D ISPLAY B UFFER .................................................................................................................1-101
9.1 Image Buffer..............................................................................................................................1-102
9.2 Ink/Cursor Buffers .....................................................................................................................1-102
9.3 Half Frame Buffer......................................................................................................................1-102
10 D ISPLAY C ONFIGURATION .....................................................................................................1-103
10.1 Display Mode Data Format........................................................................................................1-103
10.2 Image Manipulation...................................................................................................................1-105
11 L OOK -U P T ABLE A RCHITECTURE ...........................................................................................1-106
11.1 Monochrome Modes..................................................................................................................1-106
1 Bit-Per-Pixel Monochrome Mode ..................................................................................1-106
2 Bit-Per-Pixel Monochrome Mode ..................................................................................1-106
4 Bit-Per-Pixel Monochrome Mode ..................................................................................1-107
11.2 Color Display Modes.................................................................................................................1-108
1 Bit-Per-Pixel Color Mode...............................................................................................1-108
2 Bit-Per-Pixel Color Mode...............................................................................................1-109
4 Bit-Per-Pixel Color Mode...............................................................................................1-110
8 Bit-Per-Pixel Color Mode...............................................................................................1-111
12 I NK /C URSOR A RCHITECTURE .................................................................................................1-113
12.1 Ink/Cursor Buffers .....................................................................................................................1-113
12.2 Ink/Cursor Data Format.............................................................................................................1-113
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CONTENTS
S1D13505F00A HARDWARE FUNCTIONAL
EPSON
1-iii
SPECIFICATION (X23A-A-001-12)
12.3 Ink/Cursor Image Manipulation .................................................................................................1-114
Ink Image ...............................................................................................................................1-114
Cursor Image .........................................................................................................................1-114
13 S WIVEL V IEWTM ....................................................................................................................1-115
13.1 Concept.....................................................................................................................................1-115
13.2 Image Manipulation in SwivelView
TM
........................................................................................1-116
13.3 Physical Memory Requirement..................................................................................................1-117
13.4 Limitations .................................................................................................................................1-118
14 C LOCKING ...........................................................................................................................1-119
14.1 Maximum MCLK: PCLK Ratios.................................................................................................1-119
14.2 Frame Rate Calculation.............................................................................................................1-120
14.3 Bandwidth Calculation...............................................................................................................1-122
15 P OWER S AVE M ODES ...........................................................................................................1-125
16 M ECHANICAL D ATA ..............................................................................................................1-126
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CONTENTS
1-iv
EPSON
S1D13505F00AHARDWAREFUNCTIONAL
SPECIFICATION (X23A-A-001-12)
List of Figures
Figure 3-1 Typical System Diagram (SH-4 Bus, 256Kx16 FPM/EDO-DRAM)......................................1-4
Figure 3-2 Typical System Diagram (SH-3 Bus, 256Kx16 FPM/EDO-DRAM)......................................1-4
Figure 3-3 Typical System Diagram (MC68K Bus 1, 16-Bit 68000, 256Kx16 FPM/EDO-DRAM).........1-5
Figure 3-4 Typical System Diagram (MC68K Bus 2, 32-Bit 68030, 256Kx16 FPM/EDO-DRAM).........1-5
Figure 3-5 Typical System Diagram (Generic Bus, 1Mx16 FPM/EDO-DRAM).....................................1-6
Figure 3-6 Typical System Diagram (NEC V
R
41xx (MIPS) Bus, 1Mx16 FPM/EDO-DRAM).................1-6
Figure 3-7 Typical System Diagram (Philips PR31500/PR31700 Bus, 1Mx16 FPM/EDO-DRAM).......1-7
Figure 3-8 Typical System Diagram (Toshiba TX3912 Bus, 1Mx16 FPM/EDO-DRAM).......................1-7
Figure 3-9 Typical System Diagram (Power PC Bus, 256Kx16 FPM/EDO-DRAM)..............................1-8
Figure 3-10 Typical System Diagram (PC Card (PCMCIA) Bus, 1Mx16 FPM/EDO-DRAM) ..................1-8
Figure 4-1 System Block Diagram Showing Datapaths ........................................................................1-9
Figure 5-1 Pinout Diagram ..................................................................................................................1-11
Figure 5-2 External Circuitry for CRT Interface...................................................................................1-23
Figure 7-1 SH-4 Timing.......................................................................................................................1-26
Figure 7-2 SH-3 Timing.......................................................................................................................1-28
Figure 7-3 MC68000 Timing................................................................................................................1-30
Figure 7-4 MC68030 Timing................................................................................................................1-32
Figure 7-5 PC Card Interface Timing ..................................................................................................1-34
Figure 7-6 Generic Timing...................................................................................................................1-36
Figure 7-7 MIPS/ISA Timing................................................................................................................1-38
Figure 7-8 Philips Timing.....................................................................................................................1-40
Figure 7-9 Clock Input Requirements for BUSCLK Using Philips Local Bus ......................................1-41
Figure 7-10 Toshiba Timing ..................................................................................................................1-42
Figure 7-11 Clock Input Requirements..................................................................................................1-44
Figure 7-12 PowerPC Timing................................................................................................................1-45
Figure 7-13 Clock Input Requirements..................................................................................................1-46
Figure 7-14 EDO-DRAM Read/Write Timing.........................................................................................1-47
Figure 7-15 EDO-DRAM Read-Write Timing.........................................................................................1-47
Figure 7-16 EDO-DRAM CAS Before RAS Refresh Write Timing ........................................................1-49
Figure 7-17 EDO-DRAM Self-Refresh Timing.......................................................................................1-50
Figure 7-18 FPM-DRAM Read/Write Timing.........................................................................................1-51
Figure 7-19 FPM-DRAM Read-Write Timing.........................................................................................1-51
Figure 7-20 FPM-DRAM CAS before RAS Refresh Timing ..................................................................1-53
Figure 7-21 FPM-DRAM Self-Refresh Timing.......................................................................................1-54
Figure 7-22 LCD Panel Power Off / Power On Timing. Drawn with LCDPWR Set to Active High Polarity1-
55
Figure 7-23 Power Save Status and Local Bus Memory Access Relative to Power Save Mode..........1-56
Figure 7-24 4-Bit Single Monochrome Passive LCD Panel Timing.......................................................1-57
Figure 7-25 4-Bit Single Monochrome Passive LCD Panel A.C. Timing...............................................1-58
Figure 7-26 8-Bit Single Monochrome Passive LCD Panel Timing.......................................................1-59
Figure 7-27 8-Bit Single Monochrome Passive LCD Panel A.C. Timing...............................................1-60
Figure 7-28 4-Bit Single Color Passive LCD Panel Timing ...................................................................1-61
Figure 7-29 4-Bit Single Color Passive LCD Panel A.C.Timing ............................................................1-62
Figure 7-30 8-Bit Single Color Passive LCD Panel Timing (Format 1)..................................................1-63
Figure 7-31 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 1)..........................................1-64
Figure 7-32 8-Bit Single Color Passive LCD Panel Timing (Format 2)..................................................1-65
Figure 7-33 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 2)..........................................1-66
Figure 7-34 16-Bit Single Color Passive LCD Panel Timing .................................................................1-67
Figure 7-35 16-Bit Single Color Passive LCD Panel A.C. Timing .........................................................1-68
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CONTENTS
S1D13505F00A HARDWARE FUNCTIONAL
EPSON
1-v
SPECIFICATION (X23A-A-001-12)
Figure 7-36 8-Bit Dual Monochrome Passive LCD Panel Timing..........................................................1-69
Figure 7-37 8-Bit Dual Monochrome Passive LCD Panel A.C. Timing..................................................1-70
Figure 7-38 8-Bit Dual Color Passive LCD Panel Timing......................................................................1-71
Figure 7-39 8-Bit Dual Color Passive LCD Panel A.C. Timing..............................................................1-72
Figure 7-40 16-Bit Dual Color Passive LCD Panel Timing....................................................................1-73
Figure 7-41 16-Bit Dual Color Passive LCD Panel A.C. Timing............................................................1-74
Figure 7-42 16-Bit TFT/D-TFD Panel Timing.........................................................................................1-75
Figure 7-43 16-Bit TFT/D-TFD A.C. Timing...........................................................................................1-76
Figure 7-44 CRT Timing........................................................................................................................1-77
Figure 7-45 CRT A.C. Timing................................................................................................................1-78
Figure 9-1 Display Buffer Addressing................................................................................................1-101
Figure 10-1 1/2/4/8 Bit-Per-Pixel Format Memory Organization..........................................................1-103
Figure 10-2 15/16 Bit-Per-Pixel Format Memory Organization............................................................1-104
Figure 10-3 Image Manipulation..........................................................................................................1-105
Figure 11-1 1 Bit-per-pixel Monochrome Mode Data Output Path ......................................................1-106
Figure 11-2 2 Bit-per-pixel Monochrome Mode Data Output Path ......................................................1-106
Figure 11-3 4 Bit-per-pixel Monochrome Mode Data Output Path ......................................................1-107
Figure 11-4 1 Bit-per-pixel Color Mode Data Output Path...................................................................1-108
Figure 11-5 2 Bit-per-pixel Color Mode Data Output Path...................................................................1-109
Figure 11-6 4 Bit-per-pixel Color Mode Data Output Path...................................................................1-110
Figure 11-7 8 Bit-per-pixel Color Mode Data Output Path...................................................................1-111
Figure 12-1 Ink/Cursor Data Format....................................................................................................1-113
Figure 12-2 Cursor Positioning............................................................................................................1-114
Figure 13-1 Relationship Between the Screen Image and the Image Residing in the Display Buffer.1-115
Figure 16-1 Mechanical Drawing QFP15.............................................................................................1-126
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