Epson S1D13505F00A User manual

MF1151-05
S1D13505F00A Technical Manual
Technicl Manual
S1D13505F00A
Technical Manual
Embedded RAMDAC LCD/CRT Controller
S1D13505F00A
EPSON Electronic Devices Website
ELECTRONIC DEVICES MARKETING DIVISION
http://www.epson.co.jp/device/
First issue February,1999 M Printed April, 2001 in Japan C B
This manual was made with recycle papaer, and printed using soy-based inks.
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NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written
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Comparison table between new and previous number of Evaluation Boards
S5U 13705 P00C
Specification
Corresponding model number (13705: for S1D13705)
Product classification (S5U: development tool for semiconductor)
S1 D 13706 F 00A0 00
The information of the product number change
Starting April 1, 2001, the product number will be changed as listed below. To order from April 1,
2001 please use the new product number. For further information, please contact Epson sales
representative.
Devices
Configuration of product number
Comparison table between new and previous number
Packing specification
Specification
Package (B: CSP, F: QFP)
Corresponding model number
Model name (D: driver, digital products)
Product classification (S1: semiconductor)
Evaluation Board
Previous No.
SED1335 Series
SED1335D0A
SED1335F0A
SED1335F0B
S1D13305 Series
S1D13305D00A
S1D13305F00A
S1D13305F00B
New No.
Previous No.
SED135x Series
SED1353D0A
SED1353F0A
SED1353F1A
SED1354F0A
SED1354F1A
SED1354F2A
SED1355F0A
SED1356F0A
S1D1350x Series
S1D13503D00A
S1D13503F00A
S1D13503F01A
S1D13504F00A
S1D13504F01A
S1D13504F02A
S1D13505F00A
S1D13506F00A
New No.
Previous No.
SED137x Series
SED1374F0A
SED1375F0A
SED1376B0A
SED1376F0A
SED1378 Series
S1D1370x Series
S1D13704F00A
S1D13705F00A
S1D13706B00A
S1D13706F00A
S1D13708 Series
New No.
Previous No.
SED13Ax Series
SED13A3F0A
SED13A3B0B
SED13A4B0B
S1D13A0x Series
S1D13A03F00A
S1D13A03B00B
S1D13A04B00B
New No.
Previous No.
SED138x Series
SED1386F0A S1D1380x Series S1D13806F00A
New No.
• S1D1350x Series
• S1D13305 Series • S1D1370x Series
• S1D13A0x Series
• S1D1380x Series
• S1D1350x Series
• S1D1370x Series • S1D1380x Series
• S1D13A0x Series
Previous No.
SDU1353#0C
SDU1354#0C
SDU1355#0C
SDU1356#0C
S5U13503P00C
S5U13504P00C
S5U13505P00C
S5U13506P00C
New No. Previous No.
SDU1374#0C
SDU1375#0C
SDU1376#0C
SDU1376BVR
SDU1378#0C
S5U13704P00C
S5U13705P00C
S5U13706P00C
S5U13706B32R
S5U13708P00C
New No. Previous No.
SDU1386#0C S5U13806P00C
New No.
Previous No.
SDU13A3#0C
SDU13A4#0C S5U13A03P00C S5U13A04P00C
New No.
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S1D13505F00ATechnical Manual
HARDWARE FUNCTIONAL SPECIFICATION
PROGRAMMING NOTES AND EXAMPLES
UTILITIES
S5U13505P00C ISA BUS EVALUATION
BOARD USER’S MANUAL
APPLICATION NOTES
WINDOWS
®
CE DISPLAY DRIVERS
TOBIRA.fm Page 1 Sunday, April 15, 2001 6:24 PM
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S1D13505F00A
Hardware Functional
Specification
Embedded RAMDAC LCD/CRT Controller
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CONTENTS
S1D13505F00A HARDWARE FUNCTIONAL
EPSON
1-i
SPECIFICATION (X23A-A-001-12)
Contents
Table of Contents
1I NTRODUCTION .........................................................................................................................1-1
1.1 Scope ............................................................................................................................................1-1
1.2 Overview Description ....................................................................................................................1-1
2F
EATURES
...............................................................................................................................1-2
2.1 Memory Interface ..........................................................................................................................1-2
2.2 CPU Interface................................................................................................................................1-2
2.3 Display Support.............................................................................................................................1-2
2.4 Display Modes...............................................................................................................................1-3
2.5 Display Features ...........................................................................................................................1-3
2.6 Clock Source.................................................................................................................................1-3
2.7 Miscellaneous................................................................................................................................1-3
3T YPICAL S YSTEM I MPLEMENTATION D IAGRAMS ...........................................................................1-4
4I NTERNAL D ESCRIPTION ............................................................................................................1-9
4.1 Block Diagram Showing Datapaths...............................................................................................1-9
4.2 Block Descriptions.........................................................................................................................1-9
Register......................................................................................................................................1-9
Host Interface.............................................................................................................................1-9
CPU R/W ...................................................................................................................................1-9
Memory Controller......................................................................................................................1-9
Display FIFO..............................................................................................................................1-9
Cursor FIFO.............................................................................................................................1-10
Look-Up Tables........................................................................................................................1-10
CRTC.......................................................................................................................................1-10
LCD Interface...........................................................................................................................1-10
DAC .........................................................................................................................................1-10
Power Save..............................................................................................................................1-10
Clocks ......................................................................................................................................1-10
5P INS .....................................................................................................................................1-11
5.1 Pinout Diagram............................................................................................................................1-11
5.2 Pin Description ............................................................................................................................1-12
Host Interface...........................................................................................................................1-13
Memory Interface.....................................................................................................................1-17
LCD Interface...........................................................................................................................1-18
CRT Interface...........................................................................................................................1-18
Miscellaneous ..........................................................................................................................1-19
5.3 Summary of Configuration Options .............................................................................................1-20
5.4 Multiple Function Pin Mapping ....................................................................................................1-20
5.5 CRT Interface..............................................................................................................................1-23
6 D.C. C HARACTERISTICS .........................................................................................................1-24
7 A.C. C HARACTERISTICS .........................................................................................................1-26
7.1 CPU Interface Timing..................................................................................................................1-26
SH-4 Interface Timing..............................................................................................................1-26
SH-3 Interface Timing..............................................................................................................1-28
MC68K Bus 1 Interface Timing (e.g. MC68000)......................................................................1-30
MC68K Bus 2 Interface Timing (e.g. MC68030)......................................................................1-32
PC Card Interface Timing ........................................................................................................1-34
Generic Interface Timing..........................................................................................................1-36
MIPS/ISA Interface Timing.......................................................................................................1-38
Philips Interface Timing (e.g. PR31500/PR31700) ..................................................................1-40
Toshiba Interface Timing (e.g. TX3912) ..................................................................................1-42
PowerPC Interface Timing (e.g. MPC8xx, MC68040, Coldfire)...............................................1-45
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CONTENTS
1-ii
EPSON
S1D13505F00AHARDWAREFUNCTIONAL
SPECIFICATION (X23A-A-001-12)
7.2 Clock Input Requirements...........................................................................................................1-46
7.3 Memory Interface Timing.............................................................................................................1-47
EDO-DRAM Read/Write/Read-Write Timing............................................................................1-47
EDO-DRAM CAS Before RAS Refresh Timing........................................................................1-49
EDO-DRAM Self-Refresh Timing.............................................................................................1-50
FPM-DRAM Read / Write / Read - Write Timing......................................................................1-51
FPM-DRAM CAS Before RAS Refresh Timing........................................................................1-53
FPM-DRAM Self-Refresh Timing.............................................................................................1-54
7.4 Power Sequencing ......................................................................................................................1-55
LCD Power Sequencing...........................................................................................................1-55
Power Save Status ..................................................................................................................1-56
7.5 Display Interface..........................................................................................................................1-57
4-Bit Single Monochrome Passive LCD Panel Timing.............................................................1-57
8-Bit Single Monochrome Passive LCD Panel Timing.............................................................1-59
4-Bit Single Color Passive LCD Panel Timing .........................................................................1-61
8-Bit Single Color Passive LCD Panel Timing (Format 1)........................................................1-63
8-Bit Single Color Passive LCD Panel Timing (Format 2)........................................................1-65
16-Bit Single Color Passive LCD Panel Timing .......................................................................1-67
8-Bit Dual Monochrome Passive LCD Panel Timing................................................................1-69
8-Bit Dual Color Passive LCD Panel Timing............................................................................1-71
16-Bit Dual Color Passive LCD Panel Timing..........................................................................1-73
16-Bit TFT/D-TFD Panel Timing ..............................................................................................1-75
CRT Timing..............................................................................................................................1-77
8R EGISTERS ............................................................................................................................1-79
8.1 Register Mapping ........................................................................................................................1-79
8.2 Register Descriptions ..................................................................................................................1-80
Revision Code Register ...........................................................................................................1-80
Memory Configuration Registers .............................................................................................1-80
Panel/Monitor Configuration Registers ....................................................................................1-81
Display Configuration Registers...............................................................................................1-86
Clock Configuration Register ...................................................................................................1-90
Power Save Configuration Registers.......................................................................................1-91
Miscellaneous Registers..........................................................................................................1-92
Look-Up Table Registers .........................................................................................................1-97
Ink/Cursor Registers ................................................................................................................1-98
9D ISPLAY B UFFER .................................................................................................................1-101
9.1 Image Buffer..............................................................................................................................1-102
9.2 Ink/Cursor Buffers .....................................................................................................................1-102
9.3 Half Frame Buffer......................................................................................................................1-102
10 D ISPLAY C ONFIGURATION .....................................................................................................1-103
10.1 Display Mode Data Format........................................................................................................1-103
10.2 Image Manipulation...................................................................................................................1-105
11 L OOK -U P T ABLE A RCHITECTURE ...........................................................................................1-106
11.1 Monochrome Modes..................................................................................................................1-106
1 Bit-Per-Pixel Monochrome Mode ..................................................................................1-106
2 Bit-Per-Pixel Monochrome Mode ..................................................................................1-106
4 Bit-Per-Pixel Monochrome Mode ..................................................................................1-107
11.2 Color Display Modes.................................................................................................................1-108
1 Bit-Per-Pixel Color Mode...............................................................................................1-108
2 Bit-Per-Pixel Color Mode...............................................................................................1-109
4 Bit-Per-Pixel Color Mode...............................................................................................1-110
8 Bit-Per-Pixel Color Mode...............................................................................................1-111
12 I NK /C URSOR A RCHITECTURE .................................................................................................1-113
12.1 Ink/Cursor Buffers .....................................................................................................................1-113
12.2 Ink/Cursor Data Format.............................................................................................................1-113
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CONTENTS
S1D13505F00A HARDWARE FUNCTIONAL
EPSON
1-iii
SPECIFICATION (X23A-A-001-12)
12.3 Ink/Cursor Image Manipulation .................................................................................................1-114
Ink Image ...............................................................................................................................1-114
Cursor Image .........................................................................................................................1-114
13 S WIVEL V IEWTM ....................................................................................................................1-115
13.1 Concept.....................................................................................................................................1-115
13.2 Image Manipulation in SwivelView
TM
........................................................................................1-116
13.3 Physical Memory Requirement..................................................................................................1-117
13.4 Limitations .................................................................................................................................1-118
14 C LOCKING ...........................................................................................................................1-119
14.1 Maximum MCLK: PCLK Ratios.................................................................................................1-119
14.2 Frame Rate Calculation.............................................................................................................1-120
14.3 Bandwidth Calculation...............................................................................................................1-122
15 P OWER S AVE M ODES ...........................................................................................................1-125
16 M ECHANICAL D ATA ..............................................................................................................1-126
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CONTENTS
1-iv
EPSON
S1D13505F00AHARDWAREFUNCTIONAL
SPECIFICATION (X23A-A-001-12)
List of Figures
Figure 3-1 Typical System Diagram (SH-4 Bus, 256Kx16 FPM/EDO-DRAM)......................................1-4
Figure 3-2 Typical System Diagram (SH-3 Bus, 256Kx16 FPM/EDO-DRAM)......................................1-4
Figure 3-3 Typical System Diagram (MC68K Bus 1, 16-Bit 68000, 256Kx16 FPM/EDO-DRAM).........1-5
Figure 3-4 Typical System Diagram (MC68K Bus 2, 32-Bit 68030, 256Kx16 FPM/EDO-DRAM).........1-5
Figure 3-5 Typical System Diagram (Generic Bus, 1Mx16 FPM/EDO-DRAM).....................................1-6
Figure 3-6 Typical System Diagram (NEC V
R
41xx (MIPS) Bus, 1Mx16 FPM/EDO-DRAM).................1-6
Figure 3-7 Typical System Diagram (Philips PR31500/PR31700 Bus, 1Mx16 FPM/EDO-DRAM).......1-7
Figure 3-8 Typical System Diagram (Toshiba TX3912 Bus, 1Mx16 FPM/EDO-DRAM).......................1-7
Figure 3-9 Typical System Diagram (Power PC Bus, 256Kx16 FPM/EDO-DRAM)..............................1-8
Figure 3-10 Typical System Diagram (PC Card (PCMCIA) Bus, 1Mx16 FPM/EDO-DRAM) ..................1-8
Figure 4-1 System Block Diagram Showing Datapaths ........................................................................1-9
Figure 5-1 Pinout Diagram ..................................................................................................................1-11
Figure 5-2 External Circuitry for CRT Interface...................................................................................1-23
Figure 7-1 SH-4 Timing.......................................................................................................................1-26
Figure 7-2 SH-3 Timing.......................................................................................................................1-28
Figure 7-3 MC68000 Timing................................................................................................................1-30
Figure 7-4 MC68030 Timing................................................................................................................1-32
Figure 7-5 PC Card Interface Timing ..................................................................................................1-34
Figure 7-6 Generic Timing...................................................................................................................1-36
Figure 7-7 MIPS/ISA Timing................................................................................................................1-38
Figure 7-8 Philips Timing.....................................................................................................................1-40
Figure 7-9 Clock Input Requirements for BUSCLK Using Philips Local Bus ......................................1-41
Figure 7-10 Toshiba Timing ..................................................................................................................1-42
Figure 7-11 Clock Input Requirements..................................................................................................1-44
Figure 7-12 PowerPC Timing................................................................................................................1-45
Figure 7-13 Clock Input Requirements..................................................................................................1-46
Figure 7-14 EDO-DRAM Read/Write Timing.........................................................................................1-47
Figure 7-15 EDO-DRAM Read-Write Timing.........................................................................................1-47
Figure 7-16 EDO-DRAM CAS Before RAS Refresh Write Timing ........................................................1-49
Figure 7-17 EDO-DRAM Self-Refresh Timing.......................................................................................1-50
Figure 7-18 FPM-DRAM Read/Write Timing.........................................................................................1-51
Figure 7-19 FPM-DRAM Read-Write Timing.........................................................................................1-51
Figure 7-20 FPM-DRAM CAS before RAS Refresh Timing ..................................................................1-53
Figure 7-21 FPM-DRAM Self-Refresh Timing.......................................................................................1-54
Figure 7-22 LCD Panel Power Off / Power On Timing. Drawn with LCDPWR Set to Active High Polarity1-
55
Figure 7-23 Power Save Status and Local Bus Memory Access Relative to Power Save Mode..........1-56
Figure 7-24 4-Bit Single Monochrome Passive LCD Panel Timing.......................................................1-57
Figure 7-25 4-Bit Single Monochrome Passive LCD Panel A.C. Timing...............................................1-58
Figure 7-26 8-Bit Single Monochrome Passive LCD Panel Timing.......................................................1-59
Figure 7-27 8-Bit Single Monochrome Passive LCD Panel A.C. Timing...............................................1-60
Figure 7-28 4-Bit Single Color Passive LCD Panel Timing ...................................................................1-61
Figure 7-29 4-Bit Single Color Passive LCD Panel A.C.Timing ............................................................1-62
Figure 7-30 8-Bit Single Color Passive LCD Panel Timing (Format 1)..................................................1-63
Figure 7-31 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 1)..........................................1-64
Figure 7-32 8-Bit Single Color Passive LCD Panel Timing (Format 2)..................................................1-65
Figure 7-33 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 2)..........................................1-66
Figure 7-34 16-Bit Single Color Passive LCD Panel Timing .................................................................1-67
Figure 7-35 16-Bit Single Color Passive LCD Panel A.C. Timing .........................................................1-68
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CONTENTS
S1D13505F00A HARDWARE FUNCTIONAL
EPSON
1-v
SPECIFICATION (X23A-A-001-12)
Figure 7-36 8-Bit Dual Monochrome Passive LCD Panel Timing..........................................................1-69
Figure 7-37 8-Bit Dual Monochrome Passive LCD Panel A.C. Timing..................................................1-70
Figure 7-38 8-Bit Dual Color Passive LCD Panel Timing......................................................................1-71
Figure 7-39 8-Bit Dual Color Passive LCD Panel A.C. Timing..............................................................1-72
Figure 7-40 16-Bit Dual Color Passive LCD Panel Timing....................................................................1-73
Figure 7-41 16-Bit Dual Color Passive LCD Panel A.C. Timing............................................................1-74
Figure 7-42 16-Bit TFT/D-TFD Panel Timing.........................................................................................1-75
Figure 7-43 16-Bit TFT/D-TFD A.C. Timing...........................................................................................1-76
Figure 7-44 CRT Timing........................................................................................................................1-77
Figure 7-45 CRT A.C. Timing................................................................................................................1-78
Figure 9-1 Display Buffer Addressing................................................................................................1-101
Figure 10-1 1/2/4/8 Bit-Per-Pixel Format Memory Organization..........................................................1-103
Figure 10-2 15/16 Bit-Per-Pixel Format Memory Organization............................................................1-104
Figure 10-3 Image Manipulation..........................................................................................................1-105
Figure 11-1 1 Bit-per-pixel Monochrome Mode Data Output Path ......................................................1-106
Figure 11-2 2 Bit-per-pixel Monochrome Mode Data Output Path ......................................................1-106
Figure 11-3 4 Bit-per-pixel Monochrome Mode Data Output Path ......................................................1-107
Figure 11-4 1 Bit-per-pixel Color Mode Data Output Path...................................................................1-108
Figure 11-5 2 Bit-per-pixel Color Mode Data Output Path...................................................................1-109
Figure 11-6 4 Bit-per-pixel Color Mode Data Output Path...................................................................1-110
Figure 11-7 8 Bit-per-pixel Color Mode Data Output Path...................................................................1-111
Figure 12-1 Ink/Cursor Data Format....................................................................................................1-113
Figure 12-2 Cursor Positioning............................................................................................................1-114
Figure 13-1 Relationship Between the Screen Image and the Image Residing in the Display Buffer.1-115
Figure 16-1 Mechanical Drawing QFP15.............................................................................................1-126
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CONTENTS
1-vi
EPSON
S1D13505F00AHARDWAREFUNCTIONAL
SPECIFICATION (X23A-A-001-12)
List ofTables
Table 5-1 Host Interface Pin Descriptions..........................................................................................1-13
Table 5-2 Memory Interface Pin Descriptions....................................................................................1-17
Table 5-3 LCD Interface Pin Descriptions..........................................................................................1-18
Table 5-4 Clock Input Pin Description................................................................................................1-18
Table 5-5 Miscellaneous Interface Pin Descriptions ..........................................................................1-19
Table 5-6 Summary of Power On / Reset Options.............................................................................1-20
Table 5-7 CPU Interface Pin Mapping ...............................................................................................1-20
Table 5-8 Memory Interface Pin Mapping..........................................................................................1-21
Table 5-9 LCD Interface Pin Mapping................................................................................................1-22
Table 6-1 Absolute Maximum Ratings ...............................................................................................1-24
Table 6-2 Recommended Operating Conditions................................................................................1-24
Table 6-3 Electrical Characteristics for V
DD
= 5.0V Typical ...............................................................1-24
Table 6-4 Electrical Characteristics for V
DD
= 3.3V Typical ...............................................................1-24
Table 6-5 Electrical Characteristics for V
DD
= 3.0V Typical ...............................................................1-25
Table 7-1 SH-4 Timing.......................................................................................................................1-27
Table 7-2 SH-3 Timing.......................................................................................................................1-29
Table 7-3 MC68000 Timing................................................................................................................1-31
Table 7-4 MC68030 Timing................................................................................................................1-33
Table 7-5 PC Card Interface Timing ..................................................................................................1-35
Table 7-6 Generic Timing...................................................................................................................1-37
Table 7-7 MIPS/ISA Timing................................................................................................................1-39
Table 7-8 Philips Timing.....................................................................................................................1-41
Table 7-9 Clock Input Requirements for BUSCLK Using Philips Local Bus ......................................1-41
Table 7-10 Toshiba Timing ..................................................................................................................1-43
Table 7-11 Clock Input Requirements for BUSCLK Using Toshiba Local Bus ....................................1-44
Table 7-12 PowerPC Timing................................................................................................................1-45
Table 7-13 Clock Input Requirements for CLKI Divided Down Internally (MCLK = CLKI/2)................1-46
Table 7-14 Clock Input Requirements for CLKI ...................................................................................1-46
Table 7-15 EDO DRAM Read Timing ..................................................................................................1-48
Table 7-16 EDO DRAM CAS Before RAS Refresh Write Timing.........................................................1-49
Table 7-17 EDO-DRAM Self-Refresh Timing.......................................................................................1-50
Table 7-18 FPM-DRAM Read/Write/Read-Write Timing......................................................................1-52
Table 7-19 FPM-DRAM CAS before RAS Refresh Timing ..................................................................1-53
Table 7-20 FPM DRAM Self-Refresh Timing.......................................................................................1-54
Table 7-21 LCD Panel Power Off/ Power On.......................................................................................1-55
Table 7-22 Power Save Status and Local Bus Memory Access Relative to Power Save Mode..........1-56
Table 7-23 4-Bit Single Monochrome Passive LCD Panel A.C. Timing...............................................1-58
Table 7-24 8-Bit Single Monochrome Passive LCD Panel A.C. Timing...............................................1-60
Table 7-25 4-Bit Single Color Passive LCD Panel A.C.Timing ............................................................1-62
Table 7-26 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 1)..........................................1-64
Table 7-27 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 2)..........................................1-66
Table 7-28 16-Bit Single Color Passive LCD Panel A.C. Timing .........................................................1-68
Table 7-29 8-Bit Dual Monochrome Passive LCD Panel A.C. Timing..................................................1-70
Table 7-30 8-Bit Dual Color Passive LCD Panel A.C. Timing..............................................................1-72
Table 7-31 16-Bit Dual Color Passive LCD Panel A.C. Timing............................................................1-74
Table 7-32 16-Bit TFT/D-TFD A.C. Timing...........................................................................................1-76
Table 7-33 CRT A.C. Timing................................................................................................................1-78
Table 8-1 S1D13505 Addressing.......................................................................................................1-79
Table 8-2 DRAM Refresh Rate Selection ..........................................................................................1-80
Table 8-3 Panel Data Width Selection ...............................................................................................1-81
Table 8-4 FPLINE Polarity Selection..................................................................................................1-83
Table 8-5 FPFRAME Polarity Selection.............................................................................................1-85
Table 8-6 Simultaneous Display Option Selection.............................................................................1-86
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CONTENTS
S1D13505F00A HARDWARE FUNCTIONAL
EPSON
1-vii
SPECIFICATION (X23A-A-001-12)
Table 8-7 Bits-Per-Pixel Selection......................................................................................................1-87
Table 8-8 Pixel Panning Selection......................................................................................................1-89
Table 8-9 PCLK Divide Selection.......................................................................................................1-90
Table 8-10 Suspend Refresh Selection................................................................................................1-91
Table 8-11 MA/GPIO Pin Functionality.................................................................................................1-93
Table 8-12 Minimum Memory Timing Selection...................................................................................1-95
Table 8-13 RAS#-to-CAS# Delay Timing Select..................................................................................1-95
Table 8-14 RAS# Precharge Timing Select..........................................................................................1-95
Table 8-15 Optimal N
RC , N RP , and N RCD Values at Maximum MCLK Frequency................................1-96
Table 8-16 Minimum Memory Timing Selection...................................................................................1-96
Table 8-17 Ink/Cursor Selection...........................................................................................................1-98
Table 8-18 Ink/Cursor Start Address Encoding..................................................................................1-100
Table 8-19 Recommended Alternate FRM Scheme...........................................................................1-100
Table 9-1 S1D13505 Addressing .....................................................................................................1-101
Table 12-1 Ink/Cursor Data Format....................................................................................................1-113
Table 12-2 Ink/Cursor Color Select....................................................................................................1-113
Table 13-1 Minimum DRAM Size Required for SwivleView
TM..................................................................................1-118
Table 14-1 Maximum PCLK Frequency with EDO-DRAM .................................................................1-119
Table 14-2 Maximum PCLK Frequency with FPM-DRAM..................................................................1-120
Table 14-3 Example Frame Rates with Ink Disabled .........................................................................1-121
Table 14-4 Number of MCLKs Required for Various Memory Access...............................................1-122
Table 14-5 Total # MCLKs Taken for Display Refresh.......................................................................1-123
Table 14-6 Theoretical Maximum Bandwidth M byte/sec, Cursor/Ink Disabled.................................1-124
Table 15-1 Power Save Mode Function Summary.............................................................................1-125
Table 15-2 Pin States in Power-Save Modes.....................................................................................1-125
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1: INTRODUCTION
S1D13505F00A HARDWARE FUNCTIONAL
EPSON
1-1
SPECIFICATION (X23A-A-001-12)
1I NTRODUCTION
1.1 Scope
This is the Hardware Functional Specification for the S1D13505 Embedded RAMDAC LCD/CRT
Controller. Included in this document are timing diagrams, AC and DC characteristics, register
descriptions, and power management descriptions. This document is intended for two audiences:
Video Subsystem Designers and Software Developers.
1.2 Overview Description
The S1D13505 is a color/monochrome LCD/CRT graphics controller interfacing to a wide range of
CPUs and display devices. The S1D13505 architecture is designed to meet the low cost, low power
requirements of the embedded markets, such as Mobile Communications, Hand-Held PCs, and
Office Automation.
The S1D13505 supports multiple CPUs, all LCD panel types, CRT, and additionally provides a
number of differentiating features. Products requiring a “Portrait” mode display can take advantage
of the SwivelView
TM
feature. Simultaneous, Virtual and Split Screen Display are just some of the
display modes supported, while the Hardware Cursor, Ink Layer, and the Memory Enhancement
Registers offer substantial performance benefits. These features, combined with the S1D13505’s
Operating System independence, make it an ideal display solution for a wide variety of applications.
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2: FEATURES
1-2
EPSON
S1D13505F00AHARDWAREFUNCTIONAL
SPECIFICATION (X23A-A-001-12)
2F EATURES
2.1 Memory Interface
• 16-bit DRAM interface:
- EDO-DRAM up to 40MHz data rate (80M bytes per second).
- FPM-DRAM up to 25MHz data rate (50M bytes per second).
• Memory size options:
- 512K bytes using one 256K × 16 device.
- 2M bytes using one 1M × 16 device.
• Performance Enhancement Register to tailor the memory control output timing for the DRAM
device.
2.2 CPU Interface
• Supports the following interfaces:
- 8/16-bit SH-4 bus interface.
- 8/16-bit SH-3 bus interface.
- 8/16-bit interface to 8/16/32-bit MC68000 microprocessors/microcontrollers.
- 8/16-bit interface to 8/16/32-bit MC68030 microprocessors/microcontrollers.
- Philips PR31500/PR31700 (MIPS).
- Toshiba TX3912 (MIPS).
- Philips PR31500/PR31700.
- 16-bit Power PC (MPC821) microprocessor.
- 16-bit Epson E0C33 microprocessor.
- PC Card (PCMCIA).
- StrongARM (PC Card).
- NEC VR41xx (MIPS).
- ISA bus.
• Supports the following interface with external logic:
- GX486 microprocessor.
• One-stage write buffer for minimum wait-state CPU writes.
• Registers are memory-mapped – the M/R# pin selects between the display buffer and register
address space.
• The complete 2M byte display buffer address space is addressable as a single linear address space
through the 21-bit address bus.
2.3 Display Support
• 4/8-bit monochrome passive LCD interface.
• 4/8/16-bit color passive LCD interface.
• Single-panel, single-drive displays.
• Dual-panel, dual-drive displays.
• Direct support for 9/12-bit TFT/D-TFD; 18-bit TFT/D-TFD is supported up to 64K color depth
(16-bit data).
• Embedded RAMDAC (DAC)with direct analog CRT drive.
• Simultaneous display of CRT and passive or TFT/D-TFD panels.
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2: FEATURES
S1D13505F00A HARDWARE FUNCTIONAL
EPSON
1-3
SPECIFICATION (X23A-A-001-12)
2.4 Display Modes
• 1/2/4/8/15/16 bit-per-pixel (bpp) support on LCD/CRT.
• Up to 16 shades of gray using FRM on monochrome passive LCD panels.
• Up to 4096 colors on passive LCD panels; three 256x4 Look-Up Tables (LUT) are used to map 1/
2/4/8 bpp modes into these colors, 15/16 bpp modes are mapped directly using the 4 most signifi-
cant bits of the red, green and blue colors.
• Up to 64K colors on TFT/D-TFD LCD panels and CRT; three 256x4 Look-Up Tables are used to
map 1/2/4/8 bpp modes into 4096 colors, 15/16 bpp modes are mapped directly.
2.5 Display Features
• SwivelView
TM
: direct hardware 90˚ rotation of display image for “portrait” mode display.
• Split Screen Display: allows two different images to be simultaneously viewed on the same dis-
play.
• Virtual Display Support: displays images larger than the display size through the use of panning.
• Double Buffering/multi-pages: provides smooth animation and instantaneous screen update.
• Acceleration of screen updates by allocating full display memory bandwidth to CPU (see
REG[23h] bit 7).
• Hardware 64x64 pixel 2-bit cursor or full screen 2-bit ink layer.
• Simultaneous display of CRT and passive panel or TFT/D-TFD panel.
• Normal mode for cases where LCD and CRT screen sizes are identical.
• Line-doubling for simultaneous display of 240-line images on 240-line LCD and 480-line CRT.
• Even-scan or interlace modes for simultaneous display of 480-line images on 240-line LCD and
480-line CRT.
2.6 Clock Source
• Single clock input for both the pixel and memory clocks.
• Memory clock can be input clock or (input clock/2), providing flexibility to use CPU bus clock as
input.
• Pixel clock can be the memory clock, (memory clock/2), (memory clock/3) or (memory clock/4).
2.7 Miscellaneous
• The memory data bus, MD[15:0], is used to configure the chip at power-on.
• Three General Purpose Input/Output pins, GPIO[3:1], are available if the upper Memory Address
pins are not required for asymmetric DRAM support.
• Suspend power save mode can be initiated by either hardware or software.
• The SUSPEND# pin is used either as an input to initiate Suspend mode, or as a General Purpose
Output that can be used to control the LCD backlight. Power-on polarity is selected by an MD
configuration pin.
• Operating voltages from 2.7 volts to 5.5 volts are supported
• 128-pin QFP15 surface mount package
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3: TYPICAL SYSTEM IMPLEMENTATION DIAGRAMS
1-4 EPSON S1D13505F00AHARDWAREFUNCTIONAL
SPECIFICATION (X23A-A-001-12)
3T YPICAL S YSTEM I MPLEMENTATION D IAGRAMS
Figure 3-1 Typical System Diagram (SH-4 Bus, 256Kx16 FPM/EDO-DRAM)
Figure 3-2 Typical System Diagram (SH-3 Bus, 256Kx16 FPM/EDO-DRAM)
Power
Management
S1D13505F00A
CLKI
Oscillator
SH-4
BUS
RESET#
WE0#
D[15:0]
BS#
RD/WR#
RD#
WAIT#
A[20:0]
CKIO
WE0#
RD/WR#
AB[20:0]
DB[15:0]
WE1#
BS#
RD#
M/R#
CS#
BUSCLK
SUSPEND#
WAIT#
RESET#
A[21]
CSn#
WE1#
WE#
A[11:0]
D[15:0]
RAS#
256Kx16
LCAS#
UCAS#
MA[8:0]
MD[15:0]
WE#
RAS#
LCAS#
UCAS#
FPM/EDO-DRAM
FPFRAME
FPSHIFT
FPLINE
DRDY
FPDAT[15:8]
FPDAT[7:0]
FPFRAME
FPSHIFT
FPLINE
MOD
UD[7:0]
LD[7:0] 4/8/16-bit
LCD
Display
LCDPWR
RED,GREEN,BLUE
HRTC
VRTC
CRT
Display
IREF IREF
Power
Management
S1D13505F00A
CLKI
Oscillator
SUSPEND#
WE#
A[8:0]
D[15:0]
RAS#
256Kx16
LCAS#
UCAS#
MA[8:0]
MD[15:0]
WE#
RAS#
LCAS#
UCAS#
FPM/EDO-DRAM
FPFRAME
FPSHIFT
FPLINE
DRDY
FPDAT[15:8]
FPDAT[7:0]
FPFRAME
FPSHIFT
FPLINE
MOD
UD[7:0]
LD[7:0] 4/8/16-bit
LCD
Display
LCDPWR
RED,GREEN,BLUE
HRTC
VRTC
CRT
Display
IREF IREF
SH-3
BUS
RESET#
WE0#
D[15:0]
BS#
RD/WR#
RD#
WAIT#
A[20:0]
CKIO
WE0#
RD/WR#
AB[20:0]
DB[15:0]
WE1#
BS#
RD#
M/R#
CS#
BUSCLK
WAIT#
RESET#
A[21]
CSn#
WE1#
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3: TYPICAL SYSTEM IMPLEMENTATION DIAGRAMS
S1D13505F00A HARDWARE FUNCTIONAL EPSON 1-5
SPECIFICATION (X23A-A-001-12)
Figure 3-3 Typical System Diagram (MC68K Bus 1, 16-Bit 68000, 256Kx16 FPM/EDO-DRAM)
Figure 3-4 Typical System Diagram (MC68K Bus 2, 32-Bit 68030, 256Kx16 FPM/EDO-DRAM)
S1D13505F00A
FPFRAME
FPSHIFT
FPLINE
DRDY
FPDAT[15:8]
FPDAT[7:0]
CLKI
Oscillator
FPFRAME
FPSHIFT
FPLINE
MOD
UD[7:0]
LD[7:0] 4/8/16-bit
LCD
Display
MC68000
BUS
RESET#
LDS#
D[15:0]
AS#
R/W#
DTACK#
A[20:1]
BCLK
AB0#
RD/WR#
AB[20:1]
DB[15:0]
WE1#
BS#
M/R#
CS#
BUSCLK
WAIT#
RESET#
A[23:21]
FC0, FC1 Decoder
Decoder
UDS# LCDPWR
LCAS# UCAS# MA[8:0] MD[15:0] WE# RAS#
Power
Management
SUSPEND#
RED,GREEN,BLUE
HRTC
VRTC
CRT
Display
IREF IREF
WE#
A[8:0]
D[15:0]
RAS#
256Kx16
LCAS#
UCAS#
FPM/EDO-DRAM
S1D13505F00A
FPFRAME
FPSHIFT
FPLINE
DRDY
FPDAT[15:8]
FPDAT[7:0]
CLKI
Oscillator
FPFRAME
FPSHIFT
FPLINE
MOD
UD[7:0]
LD[7:0] 4/8/16-bit
LCD
Display
MC68030
BUS
RESET#
SIZ0
D[31:16]
AS#
R/W#
SIZ1
DSACK1#
A[20:0]
BCLK
WE0#
RD/WR#
AB[20:0]
DB[15:0]
WE1#
BS#
RD#
M/R#
CS#
BUSCLK
WAIT#
RESET#
A[31:21]
FC0, FC1 Decoder
Decoder
DS#
LCDPWR
WE#
A[8:0]
D[15:0]
RAS#
256Kx16
LCAS#
UCAS#
MA[8:0]
MD[15:0]
WE#
RAS#
LCAS#
UCAS#
FPM/EDO-DRAM
Power
Management
SUSPEND#
RED,GREEN,BLUE
HRTC
VRTC
CRT
Display
IREF IREF
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3: TYPICAL SYSTEM IMPLEMENTATION DIAGRAMS
1-6 EPSON S1D13505F00AHARDWAREFUNCTIONAL
SPECIFICATION (X23A-A-001-12)
Figure 3-5 Typical System Diagram (Generic Bus, 1Mx16 FPM/EDO-DRAM)
Figure 3-6 Typical System Diagram (NEC VR41xx (MIPS) Bus, 1Mx16 FPM/EDO-DRAM)
S1D13505F00A
FPFRAME
FPSHIFT
FPLINE
DRDY
FPDAT[15:8]
FPDAT[7:0]
CLKI
Oscillator
FPFRAME
FPSHIFT
FPLINE
MOD
UD[7:0]
LD[7:0] 4/8/16-bit
LCD
Display
Generic
BUS
RESET#
D[15:0]
RD#
WAIT#
A[20:0]
BCLK
RD/WR#
AB[20:0]
DB[15:0]
WE1#
RD#
M/R#
CS#
BUSCLK
WAIT#
RESET#
A[27:21]
CSn#
WE1# LCDPWR
WE#
A[11:0]
D[15:0]
RAS#
1Mx16
LCAS#
UCAS#
MA[11:0]
MD[15:0]
WE#
RAS#
LCAS#
UCAS#
FPM/EDO-DRAM
Decoder
WE0#
WE0#
Power
Management
SUSPEND#
RED,GREEN,BLUE
HRTC
VRTC
CRT
Display
IREF IREF
S1D13505F00A
FPFRAME
FPSHIFT
FPLINE
DRDY
FPDAT[15:8]
FPDAT[7:0]
CLKI
Oscillator
FPFRAME
FPSHIFT
FPLINE
MOD
UD[7:0]
LD[7:0] 4/8/16-bit
LCD
Display
MIPS
BUS
RESET
D[15:0]
MEMR#
RDY
A[20:0]
BCLK
RD/WR#
AB[20:0]
DB[15:0]
WE1#
RD#
M/R#
CS#
BUSCLK
WAIT#
RESET#
A[25:21]
CSn#
SBHE# LCDPWR
WE#
A[11:0]
D[15:0]
RAS#
1Mx16
LCAS#
UCAS#
MA[11:0]
MD[15:0]
WE#
RAS#
LCAS#
UCAS#
FPM/EDO-DRAM
Decoder
WE0#
MEMW#
Power
Management
SUSPEND#
RED,GREEN,BLUE
HRTC
VRTC
CRT
Display
IREF IREF
VDD
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3: TYPICAL SYSTEM IMPLEMENTATION DIAGRAMS
S1D13505F00A HARDWARE FUNCTIONAL EPSON 1-7
SPECIFICATION (X23A-A-001-12)
.
Figure 3-7 Typical System Diagram (Philips PR31500/PR31700 Bus, 1Mx16 FPM/EDO-DRAM)
.
Figure 3-8 Typical System Diagram (Toshiba TX3912 Bus, 1Mx16 FPM/EDO-DRAM)
S1D13505F00A
FPFRAME
FPSHIFT
FPLINE
DRDY
FPDAT[15:8]
FPDAT[7:0]
CLKI
Oscillator
FPFRAME
FPSHIFT
FPLINE
MOD
UD[7:0]
LD[7:0] 4/8/16-bit
LCD
Display
LCDPWR
WE#
A[11:0]
D[15:0]
RAS#
1Mx16
LCAS#
UCAS#
MA[11:0]
MD[15:0]
WE#
RAS#
LCAS#
UCAS#
FPM/EDO-DRAM
Power
Management
SUSPEND#
RED,GREEN,BLUE
HRTC
VRTC
CRT
Display
IREF IREF
PR31500 BUS
RESET#
/WE
D[31:16]
/CARDxCSL
/RD
/CARDxWAIT
A[12:0]
DCLKOUT
WE0#
RD/WR#
AB[12:0]
DB[15:0]
WE1#
BS#
RD#
M/R#
CS#
BUSCLK
WAIT#
RESET#
/CARDxCSH
AB[16:13]
ALE
/CARDREG
/CARDIORD
AB20
AB19
AB18
AB17
/CARDIOWR
/PR31700
Philips
S1D13505F00A
FPFRAME
FPSHIFT
FPLINE
DRDY
FPDAT[15:8]
FPDAT[7:0]
CLKI
Oscillator
FPFRAME
FPSHIFT
FPLINE
MOD
UD[7:0]
LD[7:0] 4/8/16-bit
LCD
Display
LCDPWR
WE#
A[11:0]
D[15:0]
RAS#
1Mx16
LCAS#
UCAS#
MA[11:0]
MD[15:0]
WE#
RAS#
LCAS#
UCAS#
FPM/EDO-DRAM
Power
Management
SUSPEND#
RED,GREEN,BLUE
HRTC
VRTC
CRT
Display
IREF IREF
BUS
RESET#
WE*
D[23:16]
CARDxCSL*
RD*
CARDxWAIT*
A[12:0]
DCLKOUT
WE0#
RD/WR#
AB[12:0]
DB[15:8]
WE1#
BS#
RD#
M/R#
CS#
BUSCLK
WAIT#
RESET#
CARDxCSH*
AB[16:13]
ALE
CARDREG*
CARDIORD*
AB20
AB19
AB18
AB17
CARDIOWR*
Toshiba
TX3912
DB[7:0]
D[31:24]
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3: TYPICAL SYSTEM IMPLEMENTATION DIAGRAMS
1-8 EPSON S1D13505F00AHARDWAREFUNCTIONAL
SPECIFICATION (X23A-A-001-12)
Figure 3-9 Typical System Diagram (Power PC Bus, 256Kx16 FPM/EDO-DRAM)
Figure 3-10 Typical System Diagram (PC Card (PCMCIA) Bus, 1Mx16 FPM/EDO-DRAM)
S1D13505F00A
FPFRAME
FPSHIFT
FPLINE
DRDY
FPDAT[15:8]
FPDAT[7:0]
CLKI
Oscillator
FPFRAME
FPSHIFT
FPLINE
MOD
UD[7:0]
LD[7:0] 4/8/16-bit
LCD
Display
PowerPC
BUS
RESET#
TSIZ1
D[0:15]
TS#
RD/WR#
TSIZ0
TA#
A[11:31]
CLKOUT
WE0#
RD/WR#
AB[20:0]
DB[15:0]
WE1#
BS#
RD#
M/R#
CS#
BUSCLK
WAIT#
RESET#
A[0:10] Decoder
Decoder
BI#
LCDPWR
WE#
A[8:0]
D[15:0]
RAS#
256Kx16
LCAS#
UCAS#
MA[8:0]
MD[15:0]
WE#
RAS#
LCAS#
UCAS#
FPM/EDO-DRAM
Power
Management
SUSPEND#
RED,GREEN,BLUE
HRTC
VRTC
CRT
Display
IREF IREF
S1D13505F00A
FPFRAME
FPSHIFT
FPLINE
DRDY
FPDAT[15:8]
FPDAT[7:0]
CLKI
Oscillator
FPFRAME
FPSHIFT
FPLINE
MOD
UD[7:0]
LD[7:0] 4/8/16-bit
LCD
Display
PC Card
BUS
RESET#
D[15:0]
OE#
WAIT#
A[20:0]
BCLK
RD/WR#
AB[20:0]
DB[15:0]
WE1#
RD#
M/R#
CS#
BUSCLK
WAIT#
RESET#
A[25:21]
CE2# LCDPWR
WE#
A[11:0]
D[15:0]
RAS#
1Mx16
LCAS#
UCAS#
MA[11:0]
MD[15:0]
WE#
RAS#
LCAS#
UCAS#
FPM/EDO-DRAM
WE0#
WE#
Power
Management
SUSPEND#
RED,GREEN,BLUE
HRTC
VRTC
CRT
Display
IREF IREF
Decoder
Decoder
CE1#
(PCMCIA)
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