FLY E185 User manual

FLYE185Service Manual
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SERVICE MANUAL
FLY E185
MOBILE TERMINAL
(V1.0)
COMPANY CONFIDENTIAL
All Rights Reserved

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CONTENT
CHAPTER 1: SUMMARY....................................................................................................................4
CHAPTER 2: PCBAOVERVIEW.......................................................................................................5
2.1 TOP SIDE..........................................................................................................................................5
2.2 BOTTOM SIDE ..................................................................................................................................6
CHAPTER 3: EXPLANATION OF SCHEMATIC.............................................................................7
3.1 TYPICAL APPLICATION OF MT6236..................................................................................................7
3.2 PRINCIPLE OF RF CIRCUIT ...............................................................................................................8
3.2.1 GSM RF AD6548 application .................................................................................................8
3.2.2 Analog Front-end& Analog Blocks.........................................................................................9
3.3 PRINCIPLE OF POWER MANAGEMENT CIRCUIT ..............................................................................16
3.3.1 Charger and protection logic .................................................................................................16
3.3.2 Power-on/off Sequence .........................................................................................................16
3.3.3 Battery Charging Circuit .......................................................................................................17
3.4 PRINCIPLE OF BASEBAND CIRCUIT.................................................................................................21
3.4.1 Whole introduction of baseband circuit ................................................................................21
3.4.2 Memory Management ...........................................................................................................21
3.4.3 SIM Card interface................................................................................................................22
3.4.4 Audio frequency circuit.........................................................................................................24
3.4.5 LCD display circuit ...............................................................................................................28
3.4.6 T-Flash card circuit................................................................................................................29
3.4.7 5Pin System interface............................................................................................................29
3.4.8 FM radio circuit.....................................................................................................................30
3.4.9 Camera circuit .......................................................................................................................30
3.4.10 Bluetooth Circuit.................................................................................................................32
3.4.11 Vibrator circuit and G sensor...............................................................................................32
CHAPTER 4: FAILUREANALYSIS.................................................................................................33
4.1 POWER ON PROBLEM .....................................................................................................................34
4.2 DISPLAY PROBLEM.........................................................................................................................35
4.3 CHARGING PROBLEM.....................................................................................................................35
4.4 VOICE CAN NOT BE SENT OR RECEIVED..........................................................................................35
4.5 NO VOICE IN SPEAKER...................................................................................................................36
4.6 T-FLASH CARD FAILURE ................................................................................................................36
4.7 CAN NOT DOWNLOAD SOFTWARE ..................................................................................................36
4.8 FM RADIO FAILURE .......................................................................................................................37
4.9 SIGNAL PROBLEM ..........................................................................................................................37
CHAPTER 5: UPDATE MANUALAND FAQ..................................................................................37
5.1 PREPARATIONS BEFORE UPDATE ....................................................................................................37

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5.2 USB CABLE DRIVER INSTALL .......................................................................................................38
5.3 UPGRADE PROCEDURE ..................................................................................................................40
5.4 FAQ ..............................................................................................................................................45
6.1 DISASSEMBLING AND ASSEMBLING................................................................................................45

FLYE185Service Manual
Chapter 1: Summary
E185 is a GSM/GPRS bar phone (Touch screen). This streamline and comfortable handset is a
perfect combination of humanized design and excellent craft. E185 provides you not only the
basic cell phone function, but also a collection of practical functions including Dual SIM, Dual
Online, One Talk, 3.2’’Color Screen, Polyphonic Melody, File manager (T-Flash card support),
MP3/MIDI/WAV/AMR/AAC, MP4/3GP, FM, one Camera, Bluetooth, PC Sync, 3D G-sensor, BT,
etc. E185 can support GSM 900/1800MHz, also GPRS.
In order to support technicians to be familiar with E185 handset, please master the method of
servicing. In addition, we provide corresponding technical data, including MTK BB (Baseband),
RF and software. There are also many Baseband and RF test reference points and description of
circuit. You can refer to maintaining examples. We hope this manual can give you some help.
Main specification and technique standards of E185 are listed as below, for more information,
please refer to corresponding Technical Data Sheet.
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Chapter 2: PCBA Overview
2.1 Top side
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2.2 Bottom side
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Chapter 3: Explanation of Schematic
3.1 Typical application of MT6236
Based on a multi-processor architecture, MT6236 integrates an ARM926EJ-STMcore, the main
processor running high-level GSM/GPRS protocol software as well as multimedia applications,
two digital signal processor core, which manages the low-level MODEM as well as advanced
audio functions, and an ARM7EJ-STMcore, the dedicated processor running Bluetooth baseband
and link control protocol, as well as the Bluetooth radio control.
MT6236 consists of the following subsystems:
Microcontroller Unit (MCU) Subsystem: includes an ARM926EJ-STMRISC processor
and its accompanying memory management and interrupt handling logics;
Digital Signal Processor (DSP) Subsystem: includes a DSP and its accompanying
memory, memory controller, and interrupt controller;
MCU/DSP Interface: the junction at which the MCU and the DSP exchange hardware
and software information;
Microcontroller Peripherals: includes all user interface modules and RF control
interface modules;
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Microcontroller Coprocessors: runs computing-intensive processes in place of the
Microcontroller;
DSP Peripherals: hardware accelerators for GSM/GPRS channel codec;
Multimedia Subsystem: integrates several advanced accelerators to support
multimedia applications;
Voice Front End: the data path for converting analog speech to and from digital
speech;
Audio Front End: the data path for converting stereo audio from an audio source;
Baseband Front End: the data path for converting a digital signal to and from an
analog signal from the RF modules;
Timing Generator: generates the control signals related to the TDMA frame timing;
Power, Reset and Clock Subsystem: manages the power, reset, and clock distribution
inside MT6236.
Bluetooth subsystem: includes an ARM7EJ-STMRISC processor with embedded
ROM/RAM system, baseband processor, and a high-performance radio block.
Power management unit: a self-contained power supply source which also controls
the charging and system startup circuitry.
3.2 Principle of RF circuit
3.2.1 GSM RFAD6548 application
The AD6548 receiver section fully integrates all RF and baseband signal processing, and it
includes Low Noise Amplifiers, Down-converting Mixers, Baseband Amplifiers/Low Pass Filters,
Baseband Output D.C offset Correction, Receive Local Oscillator (LO) Generator.
The transmit section of the AD6548 radio implements a translation loop modulator. This consists
of a quadrature modulator, high speed phase-frequency detector (PFD) with charge pump output,
loop filter, TX VCO and a feedback down converting mixer. The VCO output (divided by 2 for
low band) is fed to the power amplifier with a portion internally fed back into the
down-converting feedback mixer to close the feedback loop. It includes Quadrature Modulator,
Phase Frequency Detector (PFD), Loop filter, TX VCO, Feedback Down-converting Mixer, and
Transmit Frequency Plan.
The below figure show the GSM RF circuit:

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Figure 3.2.1 GSM RF circuit
From the chart we can see that the RF part is mainly composed of a highly integrated
CMOS transceiver chip (AD6548), some RX Saw filters, reference crystal oscillator,
power amplifier/antenna switch module (2in1), antenna and the matching components
between each other.
3.2.2 Analog Front-end&Analog Blocks
3.2.2.1 Baseband Front End
Baseband Front End is a modem interface between TX/RX mixed-signal modules and digital
signal processor (DSP). We can divide this block into two parts (see Figure 138). The first is the
uplink (transmitting) path, which converts bit-stream from DSP into digital in-phase (I) and
quadrature (Q) signals for TX mixed-signal module. The second part is the downlink (receiving)
path, which receives digital in-phase (I) and quadrature (Q) signals from RX mixed-signal module,
performs FIR filtering and then sends results to DSP. Figure 138illustrates interconnection around
Baseband Front End. In the figure the shadowed blocks compose Baseband Front End.
To enhance the capability of data processing of mobile phone and base station, the Enhanced Data
for GSM Evolution (EDGE), which used 8PSK Modulationrather than GMSK Modulation in
GSM system may provide the triple data transmission rate of 384 kbps for system to supply the
solution of voice, data, Internet linkage, and other kinds of mutual linkage, while 3bits per
symbols in 8PSK Modulation and 1 bit per symbol in GMSK Modulation.
The uplink path is mainly composed of GMSK Modulator or 8PSK Modulator and uplink parts of
Baseband Serial Ports, and the downlink path is mainly composed of RX digital FIR filter and
downlink parts of Baseband Serial Ports. Baseband Serial Ports is a serial interface used to
communicate with DSP. In addition, there is a set of control registers in Baseband Front End that
is intended for control of TX/RX mixed-signal modules, inclusive of several compensation circuit:
calibration of I/Q DC offset, I/Q Quadrature Phase Compensation and I/Q Gain Mismatch of

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uplink analog-to-digital (D/A) converters as well as I/Q Gain Mismatch for downlink
digital-to-analog (A/D) converters in TX/RX mixed-signal modules. The timing of bit streaming
through Baseband Front End is completely under control of TDMA timer. Usually only either of
uplink and downlink paths is active at one moment. However, both of the uplink and downlink
paths will be active simultaneously when Baseband Front End is in loopback mode.
When either of TX windows in TDMA timer is opened, the uplink path in Baseband Front End
will be activated. Accordingly components on the uplink path such as GMSK Modulator or 8PSK
Modulator will be powered on, and then TX mixed-signal module is also powered on. The sub
block Baseband Serial Ports will sink TX data bits from DSP and then forward them to GMSK
Modulator or 8PSK Modulator. The outputs from GMSK Modulator or 8PSK Modulator are sent
to TX mixed-signal module in format of I/Q signals. Finally D/A conversions are performed in TX
mixed-signal module and the output analog signal is output to RF module. Additionally, 8PSK
Modulation intrinsically extends the bursts window and reports in 8MVD (8PSK Modulation
Valid) in BFE_STA status register. Similarly, while either of RX windows in TDMA timer is
opened, the downlink path in Baseband Front End will be activated. Accordingly components on
the downlink path such as RX mixed-signal module and RX digital FIR filter are then powered on.
First A/D conversions are performed in RX mixed-signal module, and then the results in format of
I/Q signals are sourced to Low Pass Filtering with different bandwidth (Narrow one about Fc = 90
kHz, Wide one about FC = 110khz), Interference Detection Circuit to determine which Filter to be
used by judging receiving power on current burst, Additionally, “I/Q Compensation Circuit” is an
option in data path for modifying Receiving I/Q pair gain mismatch.. Finally the results will be
sourced to DSP through Baseband Serial Ports.
Block Diagram of Baseband Front End:
Figure 3.2.2.1 Baseband Front End Structure
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3.2.2.2 Downlink Path (RX Path)
On the downlink path, the sub-block between RX mixed-signal module and Baseband Serial Ports
is RX Path. It mainly consists of two parallel digital FIR filter with programmable tap number,
two sets of multiplexing paths for loopback modes, interface for RX mixed-signal module,
Interference Detection Circuit, I/Q Gain Mismatch compensation circuit, and interface for
Baseband Serial Ports. The block diagram is shown in Figure 140.
While RX enable windows are open, RX Path will issue control signals to have RX mixed-signal
module proceed to make A/D conversion. As each conversion is finished, one set of I/Q signals
will be latched. There exists a digital FIR filter for these I/Q signals. The result of filtering will be
dumped to Baseband Serial Ports whenever RX dump windows are opened.
Block Diagram of RX Path:
Figure3.2.2.2 downlink diagram
In order to compensate I/Q Gain Mismatch , configure IGAINSEL(I Gain Selection) in RX_CON
control register, the I over Q ratio can be compensate for 0.3 dB/step, totally 11 steps resulted in
dynamic range up to +/-1.5dB. The I/Q swap functionality can be setting “1” for SWAP(I/Q
Swapping) in RX_CFG control register, which is used to swap I/Q channel signals from RX
mixed-signal module before they are latched into RX digital FIR filter. It is intended to provide
flexibility for I/Q connection with RF modules.
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3.2.2.3 Uplink Path (TX Path)
The purpose of the uplink path inside Baseband Front End is to sink TX symbols, from DSP, then
perform GMSK modulation or 8PSK Modulation on them, then perform offset cancellation on I/Q
digital signals, and finally control TX mixed-signal module to make D/A conversion on I/Q
signals out of GMSK Modulator or 8PSK Modulator with offset cancellation. Accordingly, the
uplink path is composed of uplink parts of Baseband Serial Ports, GSM Encryptor, GMSK
Modulator, 8PSK Modulator and several compensation circuits including I/Q DC offset, I/Q
Quadrature Phase Compensation, and I/Q Gain Mismatch. The block diagram of uplink path is
shown as followed.
Block Diagram of Uplink Path:
Figure3.2.4 uplink diagram
On uplink path, the content of a burst, including tail bits, data bits, and training sequence bits is
sent from DSP. DSP outputs will be translated by either GMSK Modulator or 8PSK Modulator.
The Modulation Mode Selection is controlled by MDSEL1 (Modulation Mode Select1) MDSEL2,
MDSEL3, MDSEL4 in TX_CFG control register, and these translated bits after modulation will
become I/Q digital signals with certain latency.
TDMA timer having a quarter-bit timing accuracy gives the timing windows for uplink operation.
Uplink operation is controlled by TX enable window and TX dump window of TDMA timer.
Usually, TX enable window is opened earlier than TX dump window. When TX enable window of
TDMA timer is opened, uplink path in Baseband Front End will power-on GSK TX mixed-signal
module and thus drive valid outputs to RF module. However, uplink parts of Baseband Serial
Ports still do not sink data from DSP through the serial interface between Baseband Serial Ports
and DSP until TX dump window of TDMA timer is opened.
Quadrature Phase:
For 8PSK Modulation, in order to improve the EVM performance, use PHSEL [3:0] (Phase Select)
in TX_CFG control register to compensate the quadrature phase. 10 steps, 1degree/step, up to +/5
degree dynamic range.
DC offset Cancellation:
Offset cancellation will be performed on these I/Q digital signals to compensate offset error of
D/A converters (DAC) in TX mixed-signal module. Finally the generated I/Q digital signals will
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be input to TX mixed-signal module that contains two DAC for I/Q signal respectively.
Auxiliary Calibration Circuit - 540 kHz Sine:
By setting “1” to SGEN (Sine Tone Generation) in TX_CFG control register, the BBTX output
will become 540 kHz single sine tone, which is used for Factory Calibration scheme for Mixed
Signal Low Pass Filter Cut-off Frequency Accuracy.
GSM Encryptor:
When uplink parts of Baseband Serial Ports pass a TX symbol to GSM Encryptor, GSM Encryptor
will perform encryption on the TX symbol if set “1” to BCIEN (Baseband Ciphering Encryption)
in BFE_CON register. Otherwise, the TX symbol will be directed to GMSK modulator directly.
GMSK Modulation:
GMSK Modulator is used to convert bit stream of GSM bursts into in-phase and quadrature-phase
outputs by means of GMSK modulation scheme. It consists of a ROM table, timing control logic
and some state registers for GMSK modulation scheme. GMSK Modulator is activated when TX
dump window is opened. There is latency between assertion of TX dump window and the first
valid output of GMSK Modulator. The reason is because the bit rate of TX symbols is 270.833
KHz and the output rate of GMSK Modulator is 4.333 MHz, and therefore timing synchronization
is necessary between the two rates. Additionally, in order to prevent phase discontinuity in
between the multiple-burst Mode, the GMSK modulator will output continuous 67.7khs sine tone
outside the burst once RX DAC Enable window is still asserted. Once RX DAC Enable window is
disserted, GMSK modulator will park at DC level.
8PSK Modulation:
8PSK Modulator is used to convert bit stream of EDGE bursts into basically 8 phase I/Q pair
output by means of 8PSK modulation scheme. It consists of a ROM table, timing control logic and
some state registers for 8PSK modulation scheme. The conversion is based on 5 sequential symbol
and performed moving average form the ROM table lookup. 8PSK Modulator is activated when
TX dump window is opened. There is one clock delay between assertion of TX dump window and
the first valid output of 8PSK Modulator. The reason is because the bit rate of TX symbols is
270.833 KHz and the output rate of 8PSK Modulator is 4.333 MHz, and therefore timing
synchronization is necessary between the two rates.

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I/Q Swap:
By setting “1” to IQSWP in TX_CFG control register, phase on I/Q plane will rotate in inverse
direction. This option is to meet the different requirement form RF chip regarding I/Q plane. This
control signal is for GMSK Modulation only.
Modulation Bypass Mode:
For DSP debug purpose, set both “1” for MDBYP (Modulator Bypass) in TX_CFG control
register and BYPFLR(Bypass RX Filter) in RX_CFG control register for directly loopback DSP
16-bits data (10bits valid data plus sign or zero extension) through DAC only.
Modulation Output Latency Adjustment:
For multiple bursts, there maybe are consecutive bursts with different modulation mode. However,
there are about 8 to 10 QB output latencies for either GMSK/8PSK modulation output. In order to
match the transition timing of power ramp control in the power amplifier outside the baseband
chip, we have to precisely control the SW_QBCNT (Modulation Switching Quarter Bit Count) in
TX_CFG control register. Which will program the mode switching timing in QB count, and the
default value to switch the modulation mode is 24 QB count. Additionally, by programming
GMSK_DTAP_SYM (GMSK Delay Tap) in TX_CFG and GMSK_DTAP_QB in TX_CON
control register, the output latency for GMSK modulation output can be adjust to compensate the
offset between GMSK/8PSK modulator. The GMSK_DTAP_SYM adjust the output latency in
symbol time, while GMSK_DTA_QB adjust in Quarter Bit (QB) Time. Default value is delay 1
symbol of GMSK modulator output.
Modulation Bypass Mode:
For DSP debug purpose, set both “1” for MDBYP (Modulator Bypass) in TX_CFG control
register and BYPFLR (Bypass RX Filter) in RX_CFG control register for directly loopback DSP
16-bits data through DAC only.
Force GMSK Modulator turn on:
By setting “1” to APNDEN (Append Enable) bit in TX CFG control register, GMSK modulator
and 8PSK modulator will park on constant DC level during the non-burst period, while the I/Q
pair output phase maybe discontinuous since both modulator will be reset at the beginning of the
burst. However, the reset of the modulator will be helpful for the debugging purpose.

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3.2.2.4 Timing Generator
Timing is the most critical issue in GSM/GPRS applications. The TDMA timer provides a simple
interface for the MCU to program all the timing-related events for receive event control, transmit
event control and the timing adjustment. Detailed descriptions are mentioned in below figure:
Figure: The block diagram of TDMA timer
The TDMA timer unit is composed of three major blocks: Quarter bit counter, Signal generator
and Event registers. By default, the quarter-bit counter continuously counts from 0 to the wrap
position. In order to apply to cell synchronization and neighboring cell monitoring, the wrap
position can be changed by the MCU to shorten or lengthen a TDMA frame. The wrap position is
held in the TDMA_WRAP register and the current value of the TDMA quarter-bit counter may be
read by the MCU via the TDMA_TQCNT register.
The signal generator handles the overall comparing and event-generating processes. When a match
has occurred between the quarter bit counter and the event register, a predefined control signal is
generated. These control signals may be used for on-chip and off-chip purposes. Signals that
change state more than once per frame make use of more than one event register.
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3.3 Principle of Power Management circuit
3.3.1 Charger and protection logic
Over-temperature Protection: If the die temperature of PMU exceeds 150°C, the PMU will
automatically disable all the LDOs except the Vrtc. Once the over-temperature state is resolved, a
new power on sequence is required to enable the LDOs.
Battery Charger: The battery charger is optimized for the Li-ion batteries. The typical charging
procedure can be divided into three phases: pre-charging mode, the constant current charging
mode, and the full voltage charging mode. Figure 173shows the flow chart of the charging
procedure. Most of the charger circuits are integrated in the PMU except for one PNP, NMOS and
one accurate resistor for current sensing. These components should be applied externally.
3.3.2 Power-on/off Sequence
The PMU handles the powering ON and OFF of the handset. There are three ways to power-on the
handset system:
1. Push PWRKEY (Pull the PWRKEY pin to the low level)
Pulling PWRKEY low is the typical way to turn on the handset. The Vcore buck converter will be
turned-on first, and then Va/Vio LDOs turn-on at the same time. After Va/Vio turn-on, Vmbuck and
then Vusb/Vmc LDOs, and finally Vrf/Vtcxo LDOs will be turn on. The supplies for the baseband are
ready and then the system reset ends at the moment when the Vcore/Va/Vio/Vm/Vusb/Vmc/Vrf/Vtcxoare
fully turned-on to ensure the correct timing and function. After that, baseband would send the
PWRBB signal back to PMU for acknowledgement. To successfully power-on the handset,
PWRKEY should be kept low until PMU receives the PWRBB from baseband.
2. RTC module generate PWRBB to wake up the system
If the RTC module is scheduled to wake up the handset at some time, the PWRBB signal will
directly send to the PMU. In this case, PWRBB becomes high at the specific moment and let PMU
power-on just like the sequence described above. This is the case named RTC alarm.
3. Valid charger plug-in (CHRIN voltage is within the valid range)
Charger plugging-in will also turn on the handset if the charger is valid (no OVP take place).
However, If the battery voltage is too low to power-on，the handset (UVLO state), the system
won’t be turned-on by any of these three ways. In this case, charger will charge the battery first
and the handset will be powered-on automatically as long as the battery voltage is high enough.
Figure: States of mobile handset and regulator
Under-voltage Lockout (UVLO)
The UVLO state in the PMU prevents startup if the initial voltage of the main battery is below the
3.2V threshold. It ensures that the handset is powered-on with the battery in good condition. The
UVLO function is performed by a hysteretic comparator which can ensure the smooth power-on

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sequence. In addition, when the battery voltage is getting lower and lower, it will enter UVLO
state and the PMU will be turned-off by itself, except for Vrtc LDO, to prevent further discharging.
Once the PMU enters UVLO state, it draws low quiescent current. The RTC LDO is still working
until the DDLO disables it.
Deep Discharge Lockout (DDLO)
PMU will enter to the deep discharge lockout (DDLO) state when the battery voltage drops below
2.5V. In this state, the Vrtc LDO will be shutdown. Otherwise, it draws very low quiescent current
to prevent further discharging or even damage to the cells.
Reset
The PMU contains a reset control circuit which takes effect at both power-up and power-down.
The RESETB pin is held at low in the beginning of power-up and returns to high after the
pre-determined delay time. The delay time is controlled by a large counter, which use clock from
internal ring-oscillator. At power-off, RESETB pin will return to low immediately without any
delay.
3.3.3 Battery Charging Circuit
Battery Charger Flow Chart:

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1. Charge Detection
The PMU charger block has a detection circuit that senses the charger plug-in/out and provides the
correct information to the baseband. If CHRIN is over 4.3V, charger detection will be report to
baseband and charger circuit will be enabled. If the CHRIN voltage is over 7V, charger will send
an invalid signal to baseband for further indication. The stop of charging when CHRIN is over 7V
could be achieved by external component.
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2. Pre-Charging mode
When the battery voltage is below the CC threshold, the charging status is in the pre-charging
mode. There are two steps in this mode. While the battery voltage is deeply discharged below 2.7V,
a 50mA trickle current is used for charging the battery. This is the pre-CC1 state. When the battery
voltage exceeds 2.7V, the self-calibrated pre-charge mode is enabled, which allows 20mV
(typically) voltage drop across the external current sense resistor. This is the pre-CC2 state. The
pre-charge current in this state can be calculated as:
Typically, ICONST=100mA with VSENSE=20mV and RSEN=0.2Ω.
3. Constant Current Charging Mode
Once the battery voltage has exceeded the CC threshold, a constant current is used for periodical
charging With periodical charging, charger circuit could detect CHRIN state and battery state in
non-charging period. This is called the constant current charging mode. An up-to-800mA constant
charging current could be programmed via the register setting. The relation between the voltage
drop across the external current sense resistor and the charging current is as follows:
Typically, ICONST=800mA with VSENSE=160mV and RSEN=0.2Ω.
Before the battery voltage reaches 4.1V, the charger will be in the constant current charging mode.
4. Full/Constant Voltage Charging Mode
While the batteryvoltagereaches4.1V, a constant current with much shorter period is used for
charging. It could allow more often full battery detection in non-charging period. This is called
full voltage charging mode or constant voltage charging mode in correspondence to a linear
charger. While the battery voltage reaches 4.2V more than the pre-setting times within the limited
charging cycles, the end-of-charging process starts. It may prolong the charging and detecting
period for getting the optimized the full charging volume. This end of charging process is fully
controlled by the baseband and could be easily optimized for different battery pack.
5. Over-Voltage Protection
Once the battery voltage exceeds 4.35V, a hardware over voltage protection (OV) should be
activated and turn off the charger immediately.
6. Watchdog Timer
An internal watchdog timer is used as a protection for charging period control. In the constant
current charging mode or the full voltage charging mode, the baseband must refresh the timer
periodically to keep the charging alive. Once, the watchdog timer out, charger will stop charging.
This provides the time domain protection for charging control.
7. CSDAC
CSDAC is an 8-bit current DAC for current sink. Typically, the step for 1 LSB current sink is
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55µA. Hence, the controlled charging current could be calculated as ICHR= βx 55 µAx
CSDAC_DATA\[7:0].
8. Current Sense
A current sense circuit measures the voltage difference between VSEN and VBAT, which could be
used as a feedback signal for CSDAC driving control.
Figure 3.3.3-1 Battery Connector
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