Freescale Semiconductor MPC8349E PowerQUICC II Pro User manual

© Freescale Semiconductor, Inc., 2005–2007. All rights reserved.
Freescale Semiconductor
Technical Data
The MPC8349E PowerQUICC™ II Pro is a next generation
PowerQUICC II integrated host processor. The MPC8349E
contains a PowerPC™ processor core built on Power
Architecture™ technology with system logic for
networking, storage, and general-purpose embedded
applications. For functional characteristics of the processor,
refer to the MPC8349E PowerQUICC™ II Pro Integrated
Host Processor Reference Manual.
To locate published errata or updates for this document,refer
to the MPC8349E product summary page on our website
listed on the back cover of this document or, contact your
local Freescale sales office.
NOTE
The information in this document is accurate for
revision 1.1 silicon and earlier. For information on
revision 3.0silicon and later versions(for orderable
part numbers ending in A or B), see the
MPC8349EA PowerQUICC™ II Pro Integrated
Host Processor Hardware Specifications.
See Section 23.1, “Part Numbers Fully Addressed
by This Document,” for silicon revision level
determination.
Document Number: MPC8349EEC
Rev. 10, 07/2007
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 7
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10
4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 13
6. DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8. Ethernet: Three-Speed Ethernet, MII Management . 21
9. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
11. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
13. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
14. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
15. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
16. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
17. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
18. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 54
19. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
20. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
21. System Design Information . . . . . . . . . . . . . . . . . . . 79
22. Document Revision History . . . . . . . . . . . . . . . . . . . 83
23. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 85
MPC8349E PowerQUICC™ II Pro
Integrated Host Processor Hardware
Specifications

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
2FreescaleSemiconductor
Overview
1Overview
This section provides a high-level overview of the MPC8349E features. Figure 1 shows the major
functional units within the MPC8349E.
Figure 1. MPC8349E Block Diagram
Major features of the MPC8349E are as follows:
• Embedded PowerPC e300 processor core; operates at up to 667 MHz
— High-performance, superscalar processor core
— Floating-point, integer, load/store, system register, and branch processing units
— 32-Kbyte instruction cache, 32-Kbyte data cache
— Lockable portion of L1 cache
— Dynamic power management
— Software-compatible with the other Freescale processor families that implement Power
Architecture technology
• Double data rate, DDR SDRAM memory controller
— Programmable timing for DDR-1 SDRAM
— 32- or 64-bit data interface, up to 333-MHz data rate
— Four banks of memory, each up to 1 Gbyte
— DRAM chip configurations from 64 Mbit to 1 Gbit with x8/x16 data ports
— Full error checking and correction (ECC) support
— Page mode support (up to 16 simultaneous open pages)
TSEC
Coherent System Bus
PCI1
10/100/1Gb MII, GMII, TBI,
RTBI, RGMII
SPI
Serial
IRQs
ROM
I2CI2C Interfaces TSEC
DDR
Memory Controller
Local Bus Controller
Programmable Interrupt
Controller
DUART
e300 Core
DMA Controller
Serial Peripheral
Interface
32-KbyteL1
Instruction
Cache
32-Kbyte
L1 Data
Cache
Sequencer
SEQ
64/32b PCI Controller
PCI2
0/32b PCI Controller
Security Engine
Arbiter Bus
Monitor
USB Hi-Speed
Host Device
General Purpose I/O
USB0
USB1
GPIO
SDRAM
DDR
SDRAM
DMA
MII, GMII, TBI,
RTBI, RGMII
10/100/1Gb

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 3
Overview
— Contiguous or discontiguous memory mapping
— Read-modify-write support
— Sleep mode for self-refresh SDRAM
— Auto refresh
— On-the-fly power management using CKE
— Registered DIMM support
— 2.5-V SSTL2 compatible I/O
• Dual three-speed (10/100/1000) Ethernet controllers (TSECs)
— Dual controllers designed to comply with IEEE 802.3®, 802.3u®, 820.3x®, 802.3z®,
802.3ac® standards
— Ethernet physical interfaces:
– 1000 Mbps IEEE Std. 802.3 GMII/RGMII, IEEE Std. 802.3z TBI/RTBI, full-duplex
– 10/100 Mbps IEEE Std. 802.3 MII full- and half-duplex
— Buffer descriptors are backward-compatible with MPC8260 and MPC860T 10/100
programming models
— 9.6-Kbyte jumbo frame support
— RMON statistics support
— Internal 2-Kbyte transmit and 2-Kbyte receive FIFOs per TSEC module
— MII management interface for control and status
— Programmable CRC generation and checking
• Dual PCI interfaces
— Designed to comply with PCI Specification Revision 2.2
— Data bus width options:
– Dual 32-bit data PCI interfaces operating at up to 66 MHz
– Single 64-bit data PCI interface operating at up to 66 MHz
— PCI 3.3-V compatible
— PCI host bridge capabilities on both interfaces
— PCI agent mode on PCI1 interface
— PCI-to-memory and memory-to-PCI streaming
— Memory prefetching of PCI read accesses and support for delayed read transactions
— Posting of processor-to-PCI and PCI-to-memory writes
— On-chip arbitration supporting five masters on PCI1, three masters on PCI2
— Accesses to all PCI address spaces
— Parity supported
— Selectable hardware-enforced coherency
— Address translation units for address mapping between host and peripheral
— Dual address cycle for target
— Internal configuration registers accessible from PCI

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
4FreescaleSemiconductor
Overview
• Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,
IEEE Std. 802.11i®, iSCSI, and IKE processing. The security engine contains four
crypto-channels, a controller, and a set of crypto execution units (EUs):
— Public key execution unit (PKEU) :
– RSA and Diffie-Hellman algorithms
– Programmable field size up to 2048 bits
– Elliptic curve cryptography
– F2m and F(p) modes
– Programmable field size up to 511 bits
— Data encryption standard (DES) execution unit (DEU)
– DES and 3DES algorithms
– Two key (K1, K2) or three key (K1, K2, K3) for 3DES
– ECB and CBC modes for both DES and 3DES
— Advanced encryption standard unit (AESU)
– Implements the Rijndael symmetric-key cipher
– Key lengths of 128, 192, and 256 bits
– ECB, CBC, CCM, and counter (CTR) modes
— ARC four execution unit (AFEU)
– Stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
— Message digest execution unit (MDEU)
– SHA with 160- or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
— Random number generator (RNG)
— Four crypto-channels, each supporting multi-command descriptor chains
– Staticand/or dynamic assignment of crypto-executionunits through anintegrated controller
– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
• Universal serial bus (USB) dual role controller
— USB on-the-go mode with both device and host functionality
— Complies with USB specification Rev. 2.0
— Can operate as a stand-alone USB device
– One upstream facing port
– Six programmable USB endpoints
— Can operate as a stand-alone USB host controller
– USB root hub with one downstream-facing port
– Enhanced host controller interface (EHCI) compatible
– High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 5
Overview
— External PHY with UTMI, serial and UTMI+ low-pin interface (ULPI)
• Universal serial bus (USB) multi-port host controller
— Can operate as a stand-alone USB host controller
– USB root hub with one or two downstream-facing ports
– Enhanced host controller interface (EHCI) compatible
– Complies with USB Specification Rev. 2.0
— High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations
— Direct connection to a high-speed device without an external hub
— External PHY with serial and low-pin count (ULPI) interfaces
• Local bus controller (LBC)
— Multiplexed 32-bit address and data operating at up to 133 MHz
— Four chip selects support four external slaves
— Up to eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes controlled by an on-chip memory controller
— Three protocol engines on a per chip select basis:
– General-purpose chip select machine (GPCM)
– Three user-programmable machines (UPMs)
– Dedicated single data rate SDRAM controller
— Parity support
— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)
• Programmable interrupt controller (PIC)
— Functional and programming compatibility with the MPC8260 interrupt controller
— Support for 8 external and 35 internal discrete interrupt sources
— Support for 1 external (optional) and 7 internal machine checkstop interrupt sources
— Programmable highest priority request
— Four groups of interrupts with programmable priority
— External and internal interrupts directed to host processor
— Redirects interrupts to external INTA pin in core disable mode.
— Unique vector number for each interrupt source
• Dual industry-standard I2C interfaces
— Two-wire interface
— Multiple master support
— Master or slave I2C mode support
— On-chip digital filtering rejects spikes on the bus
— System initialization data optionally loaded from I2C-1 EPROM by boot sequencer embedded
hardware
• DMA controller

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
6FreescaleSemiconductor
Overview
— Four independent virtual channels
— Concurrent execution across multiple channels with programmable bandwidth control
— All channels accessible to local core and remote PCI masters
— Misaligned transfer capability
— Data chaining and direct mode
— Interrupt on completed segment and chain
• DUART
— Two 4-wire interfaces (RxD, TxD, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
• Serial peripheral interface (SPI) for master or slave
• General-purpose parallel I/O (GPIO)
— 64 parallel I/O pins multiplexed on various chip interfaces
• System timers
— Periodic interrupt timer
— Real-time clock
— Software watchdog timer
— Eight general-purpose timers
• Designed to comply with IEEE Std. 1149.1™, JTAG boundary scan
• Integrated PCI bus and SDRAM clock generation

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 7
Electrical Characteristics
2 Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8349E. The MPC8349E is currently targeted to these specifications. Some of these specifications are
independent of theI/O cell, but areincluded for amore complete reference. These are not purely I/Obuffer
design specifications.
2.1 Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1 Absolute Maximum Ratings
Table 1 provides the absolute maximum ratings.
Table 1. Absolute Maximum Ratings1
Characteristic Symbol Max Value Unit Notes
Core supply voltage VDD –0.3 to 1.32 V
PLL supply voltage AVDD –0.3 to 1.32 V
DDR DRAM I/O voltage GVDD –0.3 to 3.63 V
Three-speed Ethernet I/O, MII management voltage LVDD –0.3 to 3.63 V
PCI, local bus, DUART, system control and power management, I2C,
and JTAG I/O voltage OVDD –0.3 to 3.63 V
Input voltage DDR DRAM signals MVIN –0.3 to (GVDD + 0.3) V 2, 5
DDR DRAM reference MVREF –0.3 to (GVDD + 0.3) V 2, 5
Three-speed Ethernet signals LVIN –0.3 to (LVDD + 0.3) V 4, 5
Localbus,DUART, CLKIN,systemcontroland
power management, I2C, and JTAG signals OVIN –0.3 to (OVDD + 0.3) V 3, 5
PCI OVIN –0.3 to (OVDD + 0.3) V 6
Storage temperature range TSTG –55 to 150 °C
Notes:
1Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
3Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
4Caution:LVIN must not exceed LVDD by more than 0.3 V. This limit can be exceededfor a maximum of20 msduring power-on
reset and power-down sequences.
5(M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
6OVIN on the PCI interface can overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as
shown in Figure 3.

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
8FreescaleSemiconductor
Electrical Characteristics
2.1.2 Power Supply Voltage Specification
Table 2 provides the recommended operating conditions for the MPC8349E. Note that the values in
Table 2 are the recommended and tested operating conditions. Proper device operation outside these
conditions is not guaranteed.
Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8349E.
Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD
Table 2. Recommended Operating Conditions
Characteristic Symbol Recommended
Value Unit Notes
Core supply voltage VDD 1.2 V ± 60 mV V 1
PLL supply voltage AVDD 1.2 V ± 60 mV V 1
DDR DRAM I/O supply voltage GVDD 2.5 V ± 125 mV V
Three-speed Ethernet I/O supply voltage LVDD1 3.3 V ± 330 mV
2.5 V ± 125 mV V
Three-speed Ethernet I/O supply voltage LVDD2 3.3 V ± 330 mV
2.5 V ± 125 mV V
PCI, local bus, DUART, system control and power
management, I2C, and JTAG I/O voltage OVDD 3.3 V ± 330 mV V
Note:
1GVDD, LVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or
negative direction.
GND
GND – 0.3 V
GND – 0.7 V Not to Exceed 10%
G/L/OVDD + 20%
G/L/OVDD
G/L/OVDD + 5%
of tinterface1
1. tinterface refers to the clock period associated with the bus clock interface.
VIH
VIL
Note:

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 9
Electrical Characteristics
Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the MPC8349E for the 3.3-V
signals, respectively.
Figure 3. Maximum AC Waveforms on PCI Interface for 3.3-V Signaling
2.1.3 Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
2.2 Power Sequencing
MPC8349E doesnot require the core supplyvoltage and I/O supplyvoltages to beapplied in anyparticular
order. Note that during the power ramp up, before the power supplies are stable, there may be a period of
time that I/O pins are actively driven. After the power is stable, as long as PORESET is asserted, most I/O
pins are three-stated. To minimize the time that I/O pins are actively driven, it is recommended to apply
core voltage before I/O voltage and assert PORESET before the power supplies fully ramp up.
Table 3. Output Drive Capability
Driver Type Output Impedance
(Ω)Supply Voltage
Local bus interface utilities signals 40 OVDD = 3.3 V
PCI signals (not including PCI output clocks) 25
PCI output clocks (including PCI_SYNC_OUT) 40
DDR signal 18 GVDD = 2.5 V
TSEC/10/100 signals 40 LVDD = 2.5/3.3 V
DUART, system control, I2C, JTAG, USB 40 OVDD = 3.3 V
GPIO signals 40 OVDD = 3.3 V,
LVDD = 2.5/3.3 V
Undervoltage
Waveform
Overvoltage
Waveform
11 ns
(Min) +7.1 V
7.1 V p-to-p
(Min)
4 ns
(Max)
–3.5 V
7.1 V p-to-p
(Min)
62.5 ns+3.6 V
0 V
4 ns
(Max)

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
10 FreescaleSemiconductor
Power Characteristics
3 Power Characteristics
The estimated typical power dissipation for the MPC8349E device is shown in Table 4.
Table 4. MPC8349E Power Dissipation1
1The values do not include I/O supply power (OVDD, LVDD, GVDD) or AVDD. For I/O power values, see Table 5.
Core
Frequency
(MHz)
CSB
Frequency
(MHz) Typical at TJ= 65 Typical2, 3
2Typical power is based on a voltage of VDD = 1.2 V, a junction temperature of TJ = 105°C, and a Dhrystone benchmark
application.
3Thermal solutions may need to design to a value higher than typical power based on the end application, TAtarget, and I/O
power.
Maximum4
4Maximum power isbasedon a voltageofVDD = 1.2 V, worst caseprocess, ajunctiontemperatureof TJ=105°C, and an artificial
smoke test.
Unit
TBGA 333 333 2.0 3.0 3.2 W
166 1.8 2.8 2.9 W
400 266 2.1 3.0 3.3 W
133 1.9 2.9 3.1 W
450 300 2.3 3.2 3.5 W
150 2.1 3.0 3.2 W
500 333 2.4 3.3 3.6 W
166 2.2 3.1 3.4 W
533 266 2.4 3.3 3.6 W
133 2.2 3.1 3.4 W

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 11
Power Characteristics
Table 5 shows the estimated typical I/O power dissipation for MPC8349E.
Table 5. MPC8349E Typical I/O Power Dissipation
Interface Parameter GVDD
(1.8 V) GVDD (2.5 V) OVDD (3.3 V) LVDD (3.3 V) LVDD (2.5 V) Unit Comments
DDR I/O
65% utilization
2.5 V
Rs = 20 Ω
Rt = 50 Ω
2 pair of clocks
200 MHz, 32 bits — 0.42 W
200 MHz, 64 bits — 0.55 W
266 MHz, 32 bits — 0.5 W
266 MHz, 64 bits — 0.66 W
300 MHz, 32 bits — 0.54 W
300 MHz, 64 bits — 0.7 W
333 MHz, 32 bits — 0.58 W
333 MHz, 64 bits — 0.76 W
400 MHz, 32 bits —
400 MHz, 64 bits —
PCI I/O
load = 30 pF 33 MHz, 64 bits 0.08 W
66 MHz, 64 bits 0.14 W
33 MHz, 32 bits 0.04 W Multiply by 2 if using 2 ports.
66 MHz, 32 bits 0.07 W
Local bus I/O
load = 25 pF 133 MHz, 32 bits 0.27 W
83 MHz, 32 bits 0.17 W
66 MHz, 32 bits 0.14 W
50 MHz, 32 bits 0.11 W
TSEC I/O
load = 25 pF MII 0.01 W Multiply by number of
interfaces used.
GMII or TBI 0.06 W
RGMII or RTBI 0.04 W
USB 12 MHz 0.01 W Multiply by 2 if using 2 ports.
480 MHz 0.2 W
Other I/O 0.01 W

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
12 FreescaleSemiconductor
Clock Input Timing
4 Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the MPC8349E.
4.1 DC Electrical Characteristics
Table 7 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the MPC8349E.
4.2 AC Electrical Characteristics
The primary clock source for the MPC8349E can be one of two inputs, CLKIN or PCI_CLK, depending
on whether the device is configured in PCI host or PCI agent mode. Table 7 provides the clock input
(CLKIN/PCI_CLK) AC timing specifications for the MPC8349E.
Table 6. CLKIN DC Timing Specifications
Parameter Condition Symbol Min Max Unit
Input high voltage — VIH 2.7 OVDD +0.3 V
Input low voltage — VIL –0.3 0.4 V
CLKIN input current 0 V ≤VIN ≤OVDD IIN — ±10 μA
PCI_SYNC_IN input current 0 V ≤VIN ≤0.5 V or
OVDD –0.5V≤VIN ≤OVDD
IIN — ±10 μA
PCI_SYNC_IN input current 0.5 V ≤VIN ≤ OVDD – 0.5 V IIN — ±50 μA
Table 7. CLKIN AC Timing Specifications
Parameter/Condition Symbol Min Typical Max Unit Notes
CLKIN/PCI_CLK frequency fCLKIN ——66MHz1
CLKIN/PCI_CLK cycle time tCLKIN 15 — — ns —
CLKIN/PCI_CLK rise and fall time tKH, tKL 0.6 1.0 2.3 ns 2
CLKIN/PCI_CLK duty cycle tKHK/tCLKIN 40 — 60 % 3
CLKIN/PCI_CLK jitter — — — ±150 ps 4, 5
Notes:
1. Caution: The system, core, USB, security, and TSEC must not exceed their respective maximum or minimum operating
frequencies.
2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 13
RESET Initialization
5 RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the MPC8349E.
5.1 RESET DC Electrical Characteristics
Table 8 provides the DC electrical characteristics for the RESET pins of the MPC8349E.
5.2 RESET AC Electrical Characteristics
Table 9 provides the reset initialization AC timing specifications of the MPC8349E.
Table 8. RESET Pins DC Electrical Characteristics1
Characteristic Symbol Condition Min Max Unit
Input high voltage VIH 2.0 OVDD +0.3 V
Input low voltage VIL –0.3 0.8 V
Input current IIN ±5 μA
Output high voltage2VOH IOH = –8.0 mA 2.4 — V
Output low voltage VOL IOL = 8.0 mA — 0.5 V
Output low voltage VOL IOL = 3.2 mA — 0.4 V
Notes:
1. This table applies for pins PORESET, HRESET, SRESET, and QUIESCE.
2. HRESET and SRESET are open drain pins, thus VOH is not relevant for those pins.
Table 9. RESET Initialization Timing Specifications
Parameter/Condition Min Max Unit Notes
Required assertion time of HRESET or SRESET (input) to
activate reset flow 32 — tPCI_SYNC_IN 1
Required assertion time of PORESET with stable clock applied
to CLKIN when the MPC8349E is in PCI host mode 32 — tCLKIN 2
Required assertion time of PORESET with stable clock applied
to PCI_SYNC_IN when the MPC8349E is in PCI agent mode 32 — tPCI_SYNC_IN 1
HRESET/SRESET assertion (output) 512 — tPCI_SYNC_IN 1
HRESET negation to SRESET negation (output) 16 — tPCI_SYNC_IN 1
Input setup time for POR configuration signals
(CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with
respect to negation of PORESET when the MPC8349Eis in PCI
host mode
4—t
CLKIN 2
Input setup time for POR configuration signals
(CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with
respect to negation of PORESET when the MPC8349Eis in PCI
agent mode
4—t
PCI_SYNC_IN 1

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
14 FreescaleSemiconductor
RESET Initialization
Table 10 lists the PLL and DLL lock times.
Input hold time for POR configuration signals with respect to
negation of HRESET 0—ns
Time for the MPC8349E to turn off POR configuration signals
with respect to the assertion of HRESET —4 ns3
Time for the MPC8349E to turn on POR configuration signals
with respect to the negation of HRESET 1—t
PCI_SYNC_IN 1, 3
Notes:
1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. In PCI host mode, the primary clock is applied
to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the
MPC8349E
PowerQUICC™ II Pro Integrated Host Processor Family Reference Manual
.
2. tCLKIN is the clock period of the input clock applied to CLKIN. It is valid only in PCI host mode. See the
MPC8349E
PowerQUICC™ II Pro Integrated Host Processor Family Reference Manual
.
3. POR configuration signals consist of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
Table 10. PLL and DLL Lock Times
Parameter/Condition Min Max Unit Notes
PLL lock times — 100 μs
DLL lock times 7680 122,880 csb_clk cycles 1, 2
Notes:
1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio
results in the minimum and an 8:1 ratio results in the maximum.
2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 19, “Clocking.”
Table 9. RESET Initialization Timing Specifications (continued)
Parameter/Condition Min Max Unit Notes

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 15
DDR SDRAM
6 DDR SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8349E.
NOTE
The information in this document is accurate for revision 1.1 silicon and
earlier. For information on revision 3.0 silicon and earlier versions see the
MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware
Specifications. See Section 23.1, “Part Numbers Fully Addressed by This
Document,” for silicon revision level determination.
6.1 DDR SDRAM DC Electrical Characteristics
Table 11 provides the recommended operating conditions for the DDR SDRAM component(s) of the
MPC8349E.
Table 12 provides the DDR capacitance.
Table 11. DDR SDRAM DC Electrical Characteristics
Parameter/Condition Symbol Min Max Unit Notes
I/O supply voltage GVDD 2.375 2.625 V 1
I/O reference voltage MVREF 0.49 ×GVDD 0.51 ×GVDD V2
I/O termination voltage VTT MVREF – 0.04 MVREF + 0.04 V 3
Input high voltage VIH MVREF + 0.18 GVDD + 0.3 V
Input low voltage VIL –0.3 MVREF – 0.18 V
Output leakage current IOZ –10 10 μA4
Output high current (VOUT = 1.95 V) IOH –15.2 — mA
Output low current (VOUT = 0.35 V) IOL 15.2 — mA
MVREF input leakage current IVREF —5μA
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5 ×GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V ≤VOUT ≤ GVDD.
Table 12. DDR SDRAM Capacitance
Parameter/Condition Symbol Min Max Unit Notes
Input/output capacitance: DQ, DQS CIO 68pF1
Delta input/output capacitance: DQ, DQS CDIO —0.5pF1
Note:
1. This parameter is sampled. GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA= 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
16 FreescaleSemiconductor
DDR SDRAM
6.2 DDR SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM interface.
6.2.1 DDR SDRAM Input AC Timing Specifications
Table 13 provides the input AC timing specifications for the DDR SDRAM interface.
6.2.2 DDR SDRAM Output AC Timing Specifications
Table 14 and Table 15 provide the output AC timing specifications and measurement conditions for the
DDR SDRAM interface.
Table 13. DDR SDRAM Input AC Timing Specifications
At recommended operating conditions with GVDD of 2.5 V ± 5%.
Parameter Symbol Min Max Unit Notes
AC input low voltage VIL —MV
REF – 0.31 V
AC input high voltage VIH MVREF + 0.31 GVDD + 0.3 V
MDQS—MDQ/MECC input skew per byte
333 MHz
266 MHz
tDISKEW —750
1125
ps 1
Note:
1. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if
0 <= n <= 7) or ECC (MECC[{0...7}] if n = 8).
Table 14. DDR SDRAM Output AC Timing Specifications for Source Synchronous Mode
At recommended operating conditions with GVDD of 2.5 V ± 5%.
Parameter Symbol1Min Max Unit Notes
MCK[n] cycle time, (MCK[n]/MCK[n] crossing) tMCK 610ns2
Skew between any MCK to ADDR/CMD
333 MHz
266 MHz
200 MHz
tAOSKEW –1000
–1100
–1200
200
300
400
ps 3
ADDR/CMD output setup with respect to MCK
333 MHz
266 MHz
200 MHz
tDDKHAS 2.8
3.45
4.6
—ns4
ADDR/CMD output hold with respect to MCK
333 MHz
266 MHz
200 MHz
tDDKHAX 2.0
2.65
3.8
—ns4
MCS(n) output setup with respect to MCK
333 MHz
266 MHz
200 MHz
tDDKHCS 2.8
3.45
4.6
—ns4

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 17
DDR SDRAM
MCS(n) output hold with respect to MCK
333 MHz
266 MHz
200 MHz
tDDKHCX 2.0
2.65
3.8
—ns4
MCK to MDQS 333 MHz
266 MHz
200 MHz
tDDKHMH –0.9
–1.1
–1.2
0.3
0.5
0.6
ns 5
MDQ/MECC/MDM output setup with respect to
MDQS 333 MHz
266 MHz
200 MHz
tDDKHDS,
tDDKLDS 900
900
1200
—ps6
MDQ/MECC/MDM output hold with respect to
MDQS 333 MHz
266 MHz
200 MHz
tDDKHDX,
tDDKLDX 900
900
1200
—ps6
MDQS preamble start tDDKHMP –0.25 ×tMCK – 0.9 –0.25 ×tMCK +0.3 ns 7
MDQS epilogue end tDDKLME -0.9 0.3 ns 7
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing(DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. In the source synchronous mode, MCK/MCK can be shifted in1/4 applied cycle increments through the clockcontrolregister.
For the skew measurements referenced for tAOSKEW it is assumed that the clock adjustment is set to align the
address/command valid with the rising edge of MCK.
4. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the
ADDR/CMD setup and hold specifications, it is assumed that the clock control register is set to adjust the memory clocks by
1/2 applied cycle.
5. Note that tDDKHMH followsthe symbolconventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)
from the rising edge of the MCK(n) clock (KH) until the MDQS signalis valid (MH). tDDKHMH can be modified through control
of the DQSS override bits in the TIMING_CFG_2 register. In source synchronous mode, this will typically be set to the same
delay as the clockadjustin the CLK_CNTL register. The timing parameters listed in the table assume that these 2parameters
have been set to the same adjustment value. See the
MPC8349E PowerQUICC™ II Pro Integrated Host Processor Family
Reference Manual
, for a description and understanding of the timing modifications enabled by use of these bits.
6. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the MPC8349E.
7. All outputs are referenced to the rising edge of MCK(n) at the pins of the MPC8349E. Note that tDDKHMP follows the symbol
conventions described in note 1.
Table 14. DDR SDRAM Output AC Timing Specifications for Source Synchronous Mode (continued)
At recommended operating conditions with GVDD of 2.5 V ± 5%.
Parameter Symbol1Min Max Unit Notes

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
18 FreescaleSemiconductor
DDR SDRAM
Figure 4 shows the DDR SDRAM output timing for address skew with respect to any MCK.
Figure 4. Timing Diagram for tAOSKEW Measurement
Figure 5 provides the AC test load for the DDR bus.
Figure 5. DDR AC Test Load
Table 15 shows the DDR SDRAM measurement conditions.
Table 15. DDR SDRAM Measurement Conditions
Symbol DDR Unit Notes
VTH MVREF ± 0.31 V V 1
VOUT 0.5 × GVDD V2
Notes:
1. Data input threshold measurement point.
2. Data output measurement point.
ADDR/CMD
MCK[n]
MCK[n] tMCK
CMD NOOP
ADDR/CMD CMD NOOP
tAOSKEWmax)
tAOSKEW(min)
Output Z0= 50 ΩOVDD/2
RL= 50 Ω

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 19
DDR SDRAM
Figure 6 shows the DDR SDRAM output timing diagram for source synchronous mode.
Figure 6. DDR SDRAM Output Timing Diagram for Source Synchronous Mode
Table 16 provides approximate delay information that can be expected for the address and command
signals of the DDR controller for various loadings, which can be useful for a system utilizing the DLL.
These numbers are the result of simulations for one topology. The delay numbers will strongly depend on
the topology used. These delay numbers show the total delay for the address and command to arrive at the
DRAM devices. The actual delay could be different than the delays seen in simulation, depending on the
system topology. If a heavily loaded system is used, the DLL loop may need to be adjusted to meet setup
requirements at the DRAM.
Table 16. Expected Delays for Address/Command
Load Delay Unit
4 devices (12 pF) 3.0 ns
9 devices (27 pF) 3.6 ns
36 devices (108 pF) + 40 pF compensation capacitor 5.0 ns
36 devices (108 pF) + 80 pF compensation capacitor 5.2 ns
ADDR/CMD
tDDKLDS
tDDKHDS
MDQ[x]
MDQS[n]
MCK[n]
MCK[n] tMCK
tDDKLDX
tDDKHDX
D1D0
tDDKHAX,tDDKHCX
Write A0 NOOP
tDDKHAS,tDDKHCS
tDDKHMH
tDDKHME
tDDKHMP

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
20 FreescaleSemiconductor
DUART
7DUART
This section describes the DC and AC electrical specifications for the DUART interface of the
MPC8349E.
7.1 DUART DC Electrical Characteristics
Table 17 provides the DC electrical characteristics for the DUART interface of the MPC8349E.
7.2 DUART AC Electrical Specifications
Table 18 provides the AC timing parameters for the DUART interface of the MPC8349E.
Table 17. DUART DC Electrical Characteristics
Parameter Symbol Min Max Unit
High-level input voltage VIH 2OV
DD + 0.3 V
Low-level input voltage VIL –0.3 0.8 V
Input current (0.8 V ≤ VIN ≤2 V) IIN —±5μA
High-level output voltage, IOH = –100 μAV
OH OVDD – 0.2 — V
Low-level output voltage, IOL = 100 μAV
OL —0.2V
Table 18. DUART AC Timing Specifications
Parameter Value Unit Notes
Minimum baud rate 256 baud
Maximum baud rate >1,000,000 baud 1
Oversample rate 16 — 2
Notes:
1. Actual attainable baud rate will be limited by the latency of interrupt processing.
2. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are
sampled each 16th sample.