MT5F33743
4. Operation Condition and Dead Time Setting
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Since principal characteristics of IGBT depend on driving conditions like VGE and RG, certain setting
according to target design is needed. Gate bias condition and dead time setting are described here.
4.1 Forward bias voltage : +VGE (on state)
Notes when +VGE is designed are shown as follows.
(1) Set +VGE so that is remains under the maximum rated G-E voltage, VGES =±20V.
(2) It is recommended that supply voltage fluctuations are kept to within ±10%.
(3) The on-state C-E saturation voltage VCE(sat) is inversely dependent on +VGE, so the greater the
+VGE the smaller the VCE(sat).
(4) Turn-on switching time and switching loss grow smaller as +VGE rises.
(5) At turn-on (at FWD reverse recovery), the higher the +VGE the greater the likelihood of surge
voltages in opposing arms.
(6) Even while the IGBT is in the off-state, there may be malfunctions caused by the dv/dtof the
FWD’s reverse recovery and a pulse collector current may cause unnecessary heat generation.
This phenomenon is called a dv/dtshoot through and becomes more likely to occur as +VGE
rises.
(7) The greater the +VGE the smaller the short circuit withstand capability.
4.2 Reverse bias voltage : -VGE (off state)
Notes when -VGE is designed are shown as follows.
(1) Set -VGE so that it remains under the maximum rated G-E voltage, VGES =±20V .
(2) It is recommended that supply voltage fluctuations are kept to within ±10%.
(3) IGBT turn-off characteristics are heavily dependent on -VGE, especially when the collector current
is just beginning to switch off. Consequently, the greater the -VGE the shorter, the switching time
and the switching loss become smaller.
(4) If the -VGE is too small, dv/dtshoot through currents may occur, so at least set it to a value
greater than -5V. If the gate wiring is long, then it is especially important to pay attention to this.
5-7
Fig. 5-9 Principle of unexpected turn-on
In this section, the way to avoid the unexpected
IGBT turn-on by dv/dtat the FWD’s reverse recovery
will be described.
Fig. 5-9 shows the principle of unexpected turn-on
caused by dv/dtat reverse recovery. In this figure, it
is assumed that IGBT1is turned off to on and gate to
emitter voltage VGE of IGBT2is negative biased. In
this condition, when IGBT1get turned on from
off-state, FWD on its opposite arm, that is, reverse
recovery of FWD2is occurred. At same time, voltage
of IGBT2and FWD2with off-state is raised. This
causes the dv/dtaccording to switching time of
IGBT1. Because IGBT1and IGBT2have the mirror
capacitance Cres, Current is generated by dv/dt
through Cres. This current is expressed by Cres x
dv/dt. This current is flowed through the gate resistance
RG, results in increasing the gate potential.
4.3 Avoid the unexpected turn-on by recovery dv/dt
IGBT1
IGBT2
FWD2
FWD1
RG
RG
Off state
i= Cres ×dv/dt
