Fujitsu F2MC-16LX Series User manual

FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
F2MCTM-16LX
16-bit Microcontroller
MB90330 series
HARDWARE MANUAL
CM44-10129-1E

FUJITSU LIMITED
F2MCTM-16LX
16-bit Microcontroller
MB90330 series
HARDWARE MANUAL

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Preface
■Purpose of this document and intended reader
We sincerely thank you for your continued use of Fujitsu semiconductor products.
MB90330 series is a 16-bit microcontroller designed for applications such as personal computer peripheral
device requiring USB communication. The USB function is not only function operation of 12M bps but
also simple HOST operation (Mini-HOST).
MB90330 series has functions which are suitable for controlling personal computer peripheral devices such
as display and audio and mobile devices supporting the USB communication.
This manual describes the functions and operations of the MB90330 Series for engineers who develop
products using the MB90330 Series. Please read through this manual.
For more information on various instructions, refer to "Instruction Manual".
■Trademarks
F2MC, an abbreviation for, FUJITSU Flexible Microcontroller and is a registered trademark of FUJITSU
LIMITED.
Embedded Algorithm is a registered trademark of Advanced Micro Devices, Inc.
Other system and product names used in this manual are trademarks of the related companies or
organizations.
The symbols TM and (R) are sometimes omitted in the text.
■License
Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these
components in an I2C system provided that the system conforms to the I2C Standard Specification as
defined by Philips.
■Organization of this document
This manual contains the following 26 chapters and appendix.
Chapter 1 OVERVIEW
This chapter describes basics to give the understanding of the MB90330 series as a whole such as the
features, block diagrams, and overviews of the functions.
Chapter 2 CPU
This chapter describes the basic knowledge on architecture, specifications, instructions, and others to
provide better understanding of the CPU core functions of the MB90330 Series.
Chapter 3 INTERRUPTS
This chapter describes the overview of interruptions, interrupt vector and interrupt cause, register
configuration/function, and interrupt processing operations.
Chapter 4 Reset
This chapter describes the overview of reset, reset cause and oscillation stabilization wait time, and
reset operation.
Chapter 5 Clock
This chapter describes the overview of the clock, register configuration/function, clock mode, and

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oscillation stability wait time.
Chapter 6 Low-Power Consumption Mode
This chapter describes the overview of the low-power consumption mode, register configuration/
function, and operation of the low-power consumption mode.
Chapter 7 Mode setting
This chapter describes the overview of mode settings, mode pin, mode data, and operation in each mode
of mode setting.
Chapter 8 I/O port
This chapter describes the overview of the I/O port and the register configuration/function used in the I/
O port.
Chapter 9 Timebase timer
This chapter describes the overview of the timebase time, register configuration/function, interrupt, and
operation of the timebase timer.
Chapter 10 Watchdog timer
This chapter describes the overview of the watchdog timer, register configuration/function, and
operation of the watchdog timer.
Chapter 11 Watch timer
This chapter describes a overview of the watch timer, functions and configurations of its registers, and
its operation.
Chapter 12 16-bit I/O timer
This chapter describes a overview of the 16-bit I/O timer, the functions and configurations of its
registers, and its operation.
Chapter 13 USB function
This chapter describes the overview, block diagram, register, and operation of the USB function.
Chapter 14 USB Mini-HOST
This chapter describes the features of the USB Mini-HOST, difference from the USB HOST, block
diagrams, registers and operations of USB Mini-HOST, and each token flowchart of USB Mini-HOST.
Chapter 15 PWC timer
This chapter describes an overview of PWC timer, the configuration and function of register, and the
PWC timer operation and precaution.
Chapter 16 16-bit reload timer
This chapter describes an overview of 16-bit reload timer, the configuration and functions of register
and the 16-bit reload timer operation.
Chapter 17 8/16-bit PPG timer
This chapter describes an overview of 8/16-bit PPG timer, the configuration and functions of register,
and the 8/16-bit PPG timer operation.
Chapter 18 DTP/External interrupt
This chapter describes an overview of DTP/external interrupt, the configuration and functions of
register, and the DTP/external interrupt operation.
Chapter 19 8/10-bit A/D converter
This chapter describes the overview of the 8/10-bit A/D converter, the configuration/functions of the

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register, and the operation of the 8/10-bit A/D converter.
Chapter 20 Extended I/O serial interface
This chapter describes an overview of the extended I/O serial interface, the configuration and function
of registers, and operations of extended I/O serial interface.
Chapter 21 UART
This chapter describes the overview of the UART, the configuration/functions of the register, the
operation of the UART, the usage note of the UART, and the example of UART program.
Chapter 22 I2C interface
This chapter gives an overview of I2C interface, the configuration and functions of registers, and
operations of I2C interface.
Chapter 23 ROM mirror function selection module
This chapter describes the functions of the ROM mirror function selection module and the
configuration/function of the register.
Chapter 24 Address match detection function
This chapter explains the address match detection function and its operation.
Chapter 25 3M-bit FLASH MEMORY
This chapter describes the functions and operation of 3M-bit flash memory, and the method for writing/
deleting data to the flash memory.
Chapter 26 Example of connecting serial writing
This chapter describes the serial on-board writing of the flash ROM (Fujitsu standard).
APPENDIX
Appendix includes detailed information on I/O map, interrupt vector, and instruction list, which are not
mentioned in this manual and information that is needed for programming.

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Copyright© 2005 FUJITSU LIMITED All rights reserved
• The contents of this document are subject to change without notice. Customers are advised to consult with
FUJITSU sales representatives before ordering.
• The information, such as descriptions of function and application circuit examples, in this document are presented
solely for the purpose of reference to show examples of operations and uses of FUJITSU semiconductor device;
FUJITSU does not warrant proper operation of the device with respect to use based on such information. When you
develop equipment incorporating the device based on such information, you must assume any responsibility arising
out of such use of the information. FUJITSU assumes no liability for any damages whatsoever arising out of the
use of the information.
• Any information in this document, including descriptions of function and schematic diagrams, shall not be
construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or
any other right of FUJITSU or any third party or does FUJITSU warrant non-infringement of any third-party's
intellectual property right or other right by using such information. FUJITSU assumes no liability for any
infringement of the intellectual property rights or other rights of third parties which would result from the use of
information contained herein.
• The products described in this document are designed, developed and manufactured as contemplated for general
use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but
are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers
that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to
death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control
in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial
satellite). Please note that FUJITSU will not be liable against you and/or any third party for any claims or damages
arising in connection with above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy,
fire protection, and prevention of over-current levels and other abnormal operating conditions.
• If any products described in this document represent goods or technologies subject to certain restrictions on export
under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will
be required for export of those products from Japan.

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CONTENTS
CHAPTER 1 OVERVIEW .....................................................................................................1
1.1 Feature of MB90330 Series.....................................................................................................................2
1.2 Block Diagram .........................................................................................................................................7
1.3 Package Dimension.................................................................................................................................8
1.4 Pin Assignment......................................................................................................................................10
1.5 Pin Function...........................................................................................................................................11
1.6 I/O Circuit Types....................................................................................................................................18
1.7 Handling of Device.................................................................................................................................21
CHAPTER 2 CPU...............................................................................................................25
2.1 Outline Specification of CPU .................................................................................................................26
2.2 Memory Space.......................................................................................................................................27
2.3 Register of CPU.....................................................................................................................................32
2.3.1 Accumulator (A)................................................................................................................................34
2.3.2 User Stack Pointer (USP) and System Stack Pointer (SSP)............................................................35
2.3.3 Processor Status (PS)......................................................................................................................36
2.3.4 Program Counter (PC)......................................................................................................................39
2.3.5 Program Bank Register (PCB) .........................................................................................................40
2.3.6 Direct Page Register (DPR) .............................................................................................................41
2.3.7 General-purpose Registers (Register Bank) ....................................................................................42
2.4 Prefix Code............................................................................................................................................43
CHAPTER 3 INTERRUPT..................................................................................................47
3.1 Outline of Interrupt.................................................................................................................................48
3.2 Interrupt Cause and Interrupt Vector.....................................................................................................51
3.3 Interrupt Control Register and Peripheral Function...............................................................................54
3.3.1 Interrupt Control Registers (ICR00 to ICR15)...................................................................................56
3.3.2 Interrupt Control Register Functions.................................................................................................58
3.4 Hardware Interrupt.................................................................................................................................61
3.4.1 Operation of Hardware Interrupt.......................................................................................................64
3.4.2 Operation Flow of Hardware Interrupt..............................................................................................66
3.4.3 Procedure for Using a Hardware Interrupt........................................................................................67
3.4.4 Multiple Interrupts.............................................................................................................................68
3.4.5 Hardware Interrupt Processing Time................................................................................................70
3.5 Software Interrupt..................................................................................................................................72
3.6 Interrupts by Extended Intelligent I/O Service (EI2OS)..........................................................................74
3.6.1 Extended Intelligent I/O Service (EI2OS) Descriptor (ISD)...............................................................76
3.6.2 Each Register of Extended Intelligent I/O Service (EI2OS) Descriptor (ISD) ...................................78
3.6.3 Operation of Extended Intelligent I/O Service (EI2OS).....................................................................81
3.6.4 Procedure for use of Extended Intelligent I/O Service (EI2OS)........................................................82
3.6.5 Extended Intelligent I/O Service (EI2OS) Processing Time..............................................................83
3.7 Exception Processing Interrupt..............................................................................................................86
3.8 Interruption by µDMAC..........................................................................................................................87
3.8.1 µDMAC Function..............................................................................................................................88

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3.8.2 Register of µDMAC.......................................................................................................................... 89
3.8.2.1 DMA Descriptor Channel Specification Register (DCSR) ............................................................ 90
3.8.2.2 DMA Status Register (DSRH/DSRL)............................................................................................ 92
3.8.2.3 DMA Stop Status Register (DSSR).............................................................................................. 93
3.8.2.4 DMA Permission Register (DERH/DERL)....................................................................................94
3.8.3 DMA Descriptor Window Register (DDWR)..................................................................................... 95
3.8.3.1 DMA Data Counter (DDCTH/DDCTL).......................................................................................... 96
3.8.3.2 DMA I/O Register Address Pointer (DIOAH/DIOAL).................................................................... 97
3.8.3.3 DMA Control Register (DMACS).................................................................................................. 98
3.8.3.4 DMA Buffer Address Pointer (DBAPH/DBAPM/DBAPL)............................................................ 100
3.8.4 Explanation of Operation of µDMAC.............................................................................................. 101
3.9 Exceptions .......................................................................................................................................... 103
3.10 Stack Operation of Interrupt Processing............................................................................................. 104
3.11 Program Example of Interrupt Processing.......................................................................................... 106
3.12 Delayed Interrupt Generation Module................................................................................................. 110
3.12.1 Operation of Delayed Interrupt Generation Module....................................................................... 111
CHAPTER 4 RESET ........................................................................................................113
4.1 Outline of Reset.................................................................................................................................. 114
4.2 Reset Factors and Oscillation Stabilization Wait Times...................................................................... 116
4.3 External Reset Pin.............................................................................................................................. 118
4.4 Reset Operation.................................................................................................................................. 119
4.5 Reset Factor Bit .................................................................................................................................. 121
4.6 State of Each Pin at Reset.................................................................................................................. 123
CHAPTER 5 CLOCK........................................................................................................125
5.1 Outline of Clock................................................................................................................................... 126
5.2 Block Diagram of Clock Generation Section....................................................................................... 129
5.3 Clock Select Register (CKSCR).......................................................................................................... 132
5.4 Clock Mode......................................................................................................................................... 135
5.5 Oscillation Stabilization Wait Time...................................................................................................... 138
5.6 Connection of Oscillator and External Clock.......................................................................................139
CHAPTER 6 LOW-POWER CONSUMPTION MODE......................................................141
6.1 Outline of Low-Power Consumption Mode ......................................................................................... 142
6.2 Block Diagram of Low-power Consumption Control Circuit................................................................ 145
6.3 Low-power Consumption Mode Control Register (LPMCR) ............................................................... 147
6.4 CPU Intermittent Operation Mode....................................................................................................... 150
6.5 Standby Mode..................................................................................................................................... 151
6.5.1 Sleep Mode.................................................................................................................................... 152
6.5.2 Timebase Timer Mode................................................................................................................... 154
6.5.3 Watch Mode...................................................................................................................................156
6.5.4 Stop Mode ..................................................................................................................................... 158
6.6 State Transition Diagram .................................................................................................................... 160
6.7 State of the Pin during Standby Mode, Hold, and Reset .................................................................... 162
6.8 Precautions when Using Low-power Consumption Mode .................................................................. 172
CHAPTER 7 MODE SETTING.........................................................................................175
7.1 Mode Setting....................................................................................................................................... 176
7.2 Mode Pins (MD2 to MD0) ................................................................................................................... 177