Fujitsu MB86R02 Installation and operating instructions

Application Note
MB86R02 ‘Jade-D’
EMI Optimization using SSCG
© Fujitsu Microelectronics Europe GmbH
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Table of Contents
1Document Revision History................................................................................................4
2Spread-Spectrum Clocking Introduction ............................................................................5
3Clock Tree Overview..........................................................................................................6
4Clock Signals that can be modulated.................................................................................7
5The SSCG unit in MB86R02 'Jade-D' ................................................................................8
5.1 Operating Frequency Ranges...................................................................................8
5.2 Modulation Parameters.............................................................................................8
5.2.1 Modulation Period .............................................................................................................. 8
5.2.2 Modulation Period Delta (Jitter) ......................................................................................... 9
5.2.3 Modulation Type ................................................................................................................ 9
5.2.4 Modulation Peak .............................................................................................................. 11
5.2.5 Modulation Shape ............................................................................................................ 12
5.3 Using Frequency Offset (SSCG_FOFFSET) ..........................................................13
6Selecting the SSCG Operating Frequency ......................................................................13
7How to configure the SSCG Unit .....................................................................................14
7.1 SSCG Unit Default Values......................................................................................14
7.2 Configuring the SSCG Registers ............................................................................14
7.3 Calculating SSCG_FSTEP .....................................................................................15
8Enabling the SSCG Unit ..................................................................................................16
9Checking the SSCG Unit is Operating .............................................................................16
10 Important Notes during operation ...............................................................................16
11 Disabling the SSCG Unit ............................................................................................17
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1 Document Revision History
Version Date Editor Comment
1.00 23.06.2009 Andy von Treuberg First draft version
1.10 15.01.2010 Andy von Treuberg Updated Figure 6 (Modulation Peak).
Section 5.2.5 Modulation Shape: text and diagrams updated.
SSCG_OFFSET: Should be left at default 0x0. Changes accordingly.
Section 7.2 Added: table for recommended 20 kHz (SSCG_PERIOD)
1.20 19.01.2010 Andy von Treuberg Rearranged chapters 3 & 4
Exchanged name SSCG_PERIOD_DELTA for correct
SSCG_PERIOD_JITTER
Added section on SSCG_FSTEP calculation
1.30 21.01.2010 Andy von Treuberg Removed text from section 5.2.3
Corrected table values in section 7.2, moved some parameters to table
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2 Spread-Spectrum Clocking Introduction
Spread-spectrum clocking has become more popular in portable electronics devices because of faster
clock speeds and the increasing integration of high-resolution LCD displays in smaller and smaller
devices. As these devices are designed to be lightweight and inexpensive, passive EMI reduction
measures such as capacitors or metal shielding are not a viable option. This document briefly
describes the functionality and use of the Spread-Spectrum Clock Generation (SSCG) unit of the
MB86R02 'Jade-D' display controller device.
A configurable spread-spectrum clock generator unit is integrated in MB86R02 'Jade-D' in order to be
able to provide a modulated clock signal (as an alternative, parallel to the output of the internal PLL
unit), for use by the GDC's internal units. Actually, this means that a modulated clock signal can be
generated seperately for:
the internal circuitry
the output display controllers (also seperately for each)
The purpose of the SSCG is to spread the electromagnetic energy generated in a particluar bandwidth
over a frequency domain, resulting in a wider bandwidth, reducing the spectral density of the EMI
produced by the device. The radiated energy itself is not reduced, but simply distributed in a frequency
domain.
Figure 1 Screenshot of EMI analysis using SSCG
Figure 2 EMI improvement using SSCG
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3 Clock Tree Overview
Figure 3-1 Overview of Clock Structure PLL's
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4 Clock Signals that can be modulated
The Hardware manual of MB86R02 'Jade-D' describes which clock signals can be modulated, some
depending on the settings in the CSEl register (which control the multiplexers SELM and SELMCCLK).
The table below serves as a reference, please refer to the latest Hardware Manual to be sure you
have the most current information.
Name Description Freq. Freq. Modulation Stoppable
min max possible
XCLK
Reference clock
generated by oscillator or
externally, used for PLLs
and CRG module, Note 1,
2
6.25 33.3 no no
APIXPLLCLK APIX PLL Clock 0 250 no yes
APIXCORECLK
APIX core clock, used for
APIX PHY, Ashell 62.5 125 no yes
PLLCLK
Main PLL Clock, used for
DISP, DPERI modules
500 666 yes
(SELM = 1) yes
CCLK
Chip clock, used within
CRG module to generate
bus clocks
250 333 yes
(SELMCCLK = 1) yes
ARMACLK
ARM A clock, used as
clock source for ARM
core and DDR2 IF
0 333 yes
(SELMCCLK = 1) yes
ARMBCLK
ARM B clock, used for
ARM ETM module, MLB 0 166 yes
(SELMCCLK = 1) yes
PACLK[x]
APB clock, used for all
APB peripherals 0 41.625 yes
(SELMCCLK = 1) yes
HBCLK
AHB (B) clock, used for
GDC,AXI, DDR2 IF, MLB
internal
0 166 yes
(SELMCCLK = 1) yes
HACLK[y]
AHB (A) clock, used for
MLB, SD, I2S module 0 83.3 yes
(SELMCCLK = 1) yes
HACLK[x]
AHB (A) clock, used for
the remaining AHB
modules
0 83.3 yes
(SELMCCLK = 1) yes
HACLKCRG
AHB (A) clock, used for
CRG 0 83.3 yes
(SELMCCLK = 1) yes
TCONBCLK TCON RSDS bit clock 0 166 yes
(SELM = 1) yes
DCLK Pixel dotclock 0 83.3 yes (SELM = 1) yes
XCLK
Reference clock
generated by oscillator or
externally, used for PLLs
and CRG module, Note 1,
2
6.25 33.3 no no
Table 4-1, Clock overview list
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5 The SSCG unit in MB86R02 'Jade-D'
The SSCG unit plays an essential role in the MB86R02 'Jade-D' GDC providing the 'heartbeat' of the
digital units in the device. Whereas the internal PLL provides a non-modulated clock to the internal
units via the Clock/Reset Distribution unit, the SSCG can be configured and then activated to provide a
modulated clock signal.
Figure 2 SSCG Location
5.1 Operating Frequency Ranges
Much the same as in an automobile, the SSCG unit can be operated in one of two 'gears', i.e. one of
the following input frequency ranges (delivered by the internal PLL):
400 MHz – 550 MHz
550 MHz – 700 MHz (Default)
5.2 Modulation Parameters
5.2.1 Modulation Period
The SSCG unit can produce a modulated clock signal whose period (or wavelength) is variable in the
range of:
1/1,048,320 to 1/256
of the (input) PLL clock.
Example
With a PLL input clock of 666 MHz, this means the period of the modulated signal can be theoretically
in a range between 636 Hz (666 MHz * [1/1,048,320]) and 2.6 MHz (666 MHz * [1/256])
Recommended period range 15 kHz - 35 kHz
( 0x4A <= SSCG_PERIOD <= 0xAD)
Recommended setting for 20 kHz: SSCG_PERIOD <= 0x82
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5.2.2 Modulation Period Delta (Jitter)
The 'Modulation Period Delta' is the amount by which the period of the modulated output signal is
intentionally 'jittered', i.e. alternately shifted up and down in the frequency spectrum.
Figure 3 Modulation Period Jitter
5.2.3 Modulation Type
The term 'Modulation Type' refers to the direction in which the frequency spectrum of the modulated
output signal is spread. The following modulation types can be selected:
(please note that there is a difference between ES1 and ES2 of the MB86R02 'Jade-D')
Modulation of internal chip
units and the memory clock
domain
Modulation of the display
clock domain
ES1 NO YES
ES2 YES YES
Non-modulated
i.e. the SSCG is bypassed and the PLL signal is used
Downspread
The frequency spread offset is shifted downwards (to the left) of the frequency spectrum.
This modulation applies to all internal bus clocks and the memory clock domains. It
could be used for the Display Clock signals, but then you must pay very careful
attention to the resulting video timing (whether this causes display driving problems).
Upspread (not useable with MB86R02 'Jade-D'!)
The frequency spread offset is shifted upwards (to the right) of the frequency spectrum
Centerspread (default). The frequency spread offset is centered on the PLL frequency (x-axis
of the frequency spectrum).
Note:
The upspread option is not used with MB86R02 'Jade-D'.
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Figure 4 Modulation Types
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5.2.4 Modulation Peak
The Modulation Peak (set using the SSCG_PEAK_FREQUENCY register) has two settings:
SSCG_PEAK_FREQUENCY = 0
Varies the Modulation Peak from 0 to ±1.56% (recommended value due to the latency of
internal calculations)
SSCG_PEAK_FREQUENCY = 1
Varies the Modulation Peak from 0 to ±(2x 1.56%)
Do not use this setting in a productive system, as it is primarily intended for testing and
validation purposes only!
For signal stability reasons, the 'Modulation Peak', i.e. maximum or minimum modulation frequency
value of the modulated output signal is restricted to a specific value range. The values are as follows:
Default: ±1.0%
Downspread: 0 to -1.56%
Centerspread: -1.56% to +1.56%
Figure 5 SSCG Modulation Peak
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5.2.5 Modulation Shape
The 'Modulation Shape' is the form of signal which is used to modulate the main output clock signal.
There are two shapes: 'Triangle' and 'Dual Triangle'. 'Triangle' provides a first-stage EMI improvement
(SSCG_PERIOD_JITTER = 0). The 'Dual Triangle' mode (SSCG_PERIOD_JITTER = any other value
than 0) provides second-stage EMI improvement.
Triangle (SSCG_PERIOD_JITTER = 0)
A single triangular shape with a constant period (SSCG_PERIOD value) is used for
modulation. Within the four phases of a single period, the internal SSCG_FSTEP unit
increments or decrements the modulation frequency.
'Dual Triangle' (SSCG_PERIOD_JITTER = any other value than 0)
This shape is used when the duty cycle of the working period of the modulated output signal is
intentionally 'jittered' or expanded (using the SSCG_PERIOD_JITTER register) to level out
small peaks in the frequency spectrum of the modulated clock signal. As a consequence, the
amplitude of the 'second triangle shape' is also slightly higher than that of the first, increasing
the average overall frequency (this could be corrected to avoid overstepping the 666 MHz
barrier by reducing the SSCG_FSTEP value). The SSCG_FOFFSET setting can shift the
transition phases, also modifying the average overall modulation frequency (if SSCG_FSTEP
is not changed). The final modulation shape is essentially the result of continuously alternating
between two different triangle shapes.
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5.3 Using Frequency Offset (SSCG_FOFFSET)
Although it is possible to modify the SSCG_FOFFSET value in the range -1.56% to +1.56%, it is
recommended that this setting is left at its default value of 0 (0x0).
6 Selecting the SSCG Operating Frequency
This depends on the physical application (your design).
We recommend an SSCG operating frequency of 20 kHz.
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7 How to configure the SSCG Unit
7.1 SSCG Unit Default Values
The SSCG unit has the following default settings:
SSCG_PERIOD = 35 kHz. Note the recommended value for use is 20 kHz!
SSCG_PERIOD_JITTER = 0x90. Note the recommended value for use is approx. 0x70!
SSCG_CTRL.SSCG_TYPE = 0x11 (Centerspread)
Modulation Peak = +/- 1.56%
SSCG_FOFFSET = 0x0
SSCG_IEN = 0
7.2 Configuring the SSCG Registers
Using the Hardware Manual, select one of the tables which list the settings of the various SSCG
registers.
Example
An operating frequency of 20 kHz is required for the SSCG and the PLL clock is running at 666 MHz.
The relevant table is shown below.
SSCG_PEAK_FREQUENCY = 0
SSCG_FOFFSET = 0x0
SSCG_TYPE SSCG_PERIOD SSCG_PERIOD_JITTER Modulation Peak % SSCG_FSTEP
0.50 0x9292
1.00 0x1 2525
3
Centerspread 0x82 0x68
1.56 0x1 C94F
0.50 0x4949
1.00 0x9292
2
Upspread
(unused)
0x82 0x68
1.56 0xE4A7
0.50 0x4949
1.00 0x9292
1
Downspread 0x82 0x68
1.56 0xE4A7
For a centerspread type and a Modulation Peak of 1.56%, use the following settings:
SSCG_PERIOD_JITTER = 0x68 (10 %) = 1101000 (bin)
Modulation Peak = +/- 1.56%
SSCG_PERIOD = 0x82 = 10000010 (bin)
SSCG_FSTEP = 0x1 C94F = 11100100101001111 (bin)
Please take note of the limitations listed in the Hardware Manual.
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7.3 Calculating SSCG_FSTEP
For informational purposes:
SSCG_FSTEP = )__2*_(**8
__*)12(
3
31
JITTERPERIODSSCGPERIODSSCGk
OFFSETFREQUENCYSSCG
B
A
+
+−
Where A = Absolute value of Modulation Peak (e.g. 1.56), i.e. no +/-
B = max_peak = 3.125 for SSCG_PEAK_FREQUENCY = 0
B = max_peak = 6.25 for SSCG_PEAK_FREQUENCY = 1 (do not use)
k = 1 if SSCG_TYPE =3 (Centerspread) otherwise k = 2
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8 Enabling the SSCG Unit
It is important to follow an specific scheme to enable the SSCG unit in order to avoid causing a spike
on the clock signal of the effected clock domains.
Note that the registers used in the following example description are in the CRG (Base Address:
FFFE_7000) and the SSCG (Base Address: FFFE_7080) units!
1. Switch the internal clock domains to the non-SSCG modulated clock domain, reset the SSCG
and switch the display clocks to the non-SSCG modulated clock domain:
CSEL <0xFFFE_7034> = 0x00000000
2. Set the SSCG to Bypass mode and power down the SSCG:
SSCG_CTRL <FFFE_70A0*> = 0x80010111
* FFFE_7080 + 20
3. Power up the SSCG and set to Bypass mode:
SSCG_CTRL <FFFE_70A0> = 0x00010111
4. Configure the SSCG and wait for 1000 clock cycles before starting the SSCG (Period 20 kHz)
SSCG_PERIOD <0xFFFE_7080> = 0x00000082
SSCG_PERIOD_JITTER <0xFFFE_7084> = 0x00000070
SSCG_FSTEP <0xFFFE_7088> = 0x000050A8
5. Disable the Bypass mode (enabling the SSCG unit):
SSCG_CTRL <0xFFFE_70A0> = 0x00000111
6. Switch the display clock domains to the SSCG modulated clock domain:
CSEL <0xFFFE_7034> = 0x00000004
7. Enable the SSCG:
SSCG_ENABLE <0xFFFE_70A4> = 0x00000001
8. Wait for 1 millisecond
9. Reset the 'Frequency Limit' Interrupt:
SSCG_IEN.IEn_Frequency_Limit <0xFFFE_70AC> = 0x00000001
10. Check that SSCG_STATUS.STS_FREQUENCY_LIMIT = 0
Note:
The SSCG parameter configuration can be done in steps 4 .. 7; otherwise the SSCG will run with the
default settings of <0xFFFE_7080> = content of address 0xFFFE_7080.
A more detailled flow is described in the Hardware Manual.
9 Checking the SSCG Unit is Operating
You can check that the SSCG unit is operating by reading the SSCG_CNTOUTFREQ register. It will
return a value that is not '0' if the SSCG is running.
10 Important Notes during operation
Note that not every receiver can handle a modulated output signal. If problems (screen artefacts etc.)
are experienced with a display, try reducing the degree of modulation to attain a range that the
receiver can accept.
Make sure that the SSCG configuration is a valid one (i.e. the constraints of the Hardware Manual are
taken into consideration). Failure to do this – i.e. an illegal configuration - may generate a flood of
interrupts from the SSCG unit.
Do not reconfigure the SSCG unit while it is being used!
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11 Disabling the SSCG Unit
It is important to follow an specific scheme to disable the SSCG unit in order to avoid causing a spike
on the clock signal of the effected clock domains. Use the following programming sequence:
(example).
Note that the registers used in the following description are in the CRG (Base Address: FFFE_7000)
and the SSCG (Base Address: FFFE_7080) units!
1. Switch the display clock domains to the non-SSCG modulated clock domain:
CSEL <0xFFFE_7034> = 0x00000000
2. Disable the SSCG:
SSCG_ENABLE <0xFFFE_70A4> = 0x00000000
3. Set the SSCG to Bypass mode:
SSCG_CTRL <0xFFFE_70A0*> = 0x00010111
* FFFE_7080 + 20
4. Set the SSCG to Bypass mode and power down the SSCG:
SSCG_CTRL <0xFFFE_70A0> = 0x80010111
A more detailled flow is described in the Hardware Manual.
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