Fujitsu F2MC-16LX Series User manual

FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
MB90470 Series
HARDWARE MANUAL
CM44-10115-3E

FUJITSU LIMITED
F2MC-16LX
16-BIT MICROCONTROLLER
MB90470 Series
HARDWARE MANUAL

i
PREFACE
■Purpose of This Manual and Intended Readers
Thank you very much for purchasing FUJITSU products.
MB90470 is a 16-bit microcontroller designed for applications such as consumer devices
requiring high-speed real-time processing. MB90470 functions are suitable for controlling PHS,
cellular phones, CD-ROMs, and VCRs.
This manual, intended for engineers developing products using the MB90470, explains the
MB90470 functions and operations. Read this manual first, before using the product.
For details on the instructions, refer to the "Instruction Manual".
■Trademark
F2MC is a trademark of FUJITSU Flexible Microcontroller.
Embedded Algorithm is a registered trademark of Advanced Micro Devices, Inc.
■License
Purchase of FUJITSU I2C components conveys a license under the Philips I2C Patent Rights to
use these components in the I2C system, provided that the system conforms to the I2C
Standard Specification as defined by Philips.

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■Composition of This Manual
This Manual consists of the following 27 Chapters and an Appendix.
CHAPTER 1 "OVERVIEW OF MB90470"
This chapter gives an overview of MB90470, including its basic characteristics, block
diagram, and its functions.
CHAPTER 2 "CPU"
This chapter explains CPU specifications, memory, and the functions of registers to provide
readers with a better understanding of the MB90470 functions.
CHAPTER 3 "INTERRUPT"
This chapter explains interrupts and direct access (DMA).
CHAPTER 4 "RESET"
This chapter explains reset for the MB90470 series.
CHAPTER 5 "CLOCKS"
This chapter describes the clocks of the MB90470 series.
CHAPTER 6 "LOW-POWER CONSUMPTION MODE"
This chapter explains the low-power consumption mode of the MB90470 series.
CHAPTER 7 "MODE SETTING"
This chapter explains mode setting and external memory access.
CHAPTER 8 "I/O PORT"
This chapter shows the configuration and explains the functions of the registers used for the
I/O port.
CHAPTER 9 "TIMEBASE TIMER"
This chapter explains the function and operation of the timebase timer.
CHAPTER 10 "WATCHDOG TIMER"
This chapter describes the operation and function of the watchdog timer.
CHAPTER 11 "WATCH TIMER"
This chapter has an overview of the watch timer, describes the configuration and functions of
the register, and explains the operation of the watch timer.
CHAPTER 12 "16-BIT INPUT/OUTPUT TIMER"
This chapter has an overview of the 16-bit input/output timer, describes the configuration and
function of its register, and explains the operation of the timer.
CHAPTER 13 "8/16-BIT UP-DOWN COUNTER/TIMER"
This chapter has an overview of the 8/16-bit up/down counter/timer, describes the
configuration and functions of its registers, and explains the operation of the 8/16-bit up/
down counter/timer.
CHAPTER 14 "PWC TIMER"
This chapter provides an overview of the PWC timer, provides notes on its use, and explains
the configuration and functions of its registers.
CHAPTER 15 "µ
µµ
µPG TIMER"
This chapter provides a block diagram of the µPG timer and explains the configuration and
functions of its registers.

iii
CHAPTER 16 "16-BIT RELOAD TIMER"
This chapter provides an overview of the 16-bit reload timer and its operation, and explains
the configuration and functions of its registers.
CHAPTER 17 "8/16-BIT PPG TIMER"
This chapter provides an overview of the 8/16-bit PPG timer and its operation, and explains
the configuration and functions of its registers.
CHAPTER 18 "DTP/EXTERNAL INTERRUPT UNIT"
This chapter provides an overview of the DTP/external interrupt unit, its operation, and
explains the configuration and functions of its registers.
CHAPTER 19 "8/10-BIT A/D CONVERTER"
This chapter provides an overview of the 8/10-bit A/D converter and its operation, and
explains the configuration and functions of its registers.
CHAPTER 20 "EXPANDED I/O SERIAL INTERFACE"
This chapter provides an overview of the expanded I/O serial interface and its operation, and
explains the configuration and functions of its registers.
CHAPTER 21 "UART"
This chapter provides an overview of the UART, its operation, and explains the configuration
and functions of its registers.
CHAPTER 22 "I2C INTERFACE"
This chapter provides an overview of the I2C interface and its operation, and explains the
configuration and functions of its registers.
CHAPTER 23 "CHIP SELECTION FACILITY"
This chapter provides an overview of the chip selection facility and its operation, and
explains the configuration and functions of its registers.
CHAPTER 24 "ADDRESS MATCH DETECTION FUNCTION"
This chapter describes the address match detection function and its operation
CHAPTER 25 "ROM MIRROR FUNCTION SELECTION MODULE"
This chapter describes the functions of the ROM mirror function selection module.
CHAPTER 26 "2M BIT FLASH MEMORY"
This chapter describes the functions and operations of the 2M bit flash memory.
CHAPTER 27 "EXAMPLES OF MB90F474/MB90F476 SERIAL PROGRAMMING
CONNECTION"
This chapter shows an example of a serial programming connection using the AF220/AF210/
AF120/AF110 Flash Micro-computer Programmer by Yokogawa Digital Computer
Corporation.
"APPENDIX"
The appendix provides the memory map and lists the instructions used in the F2MC-16LX.

iv
©2003 FUJITSU LIMITED Printed in Japan
• The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales representatives before ordering.
• The information, such as descriptions of function and application circuit examples, in this document are
presented solely for the purpose of reference to show examples of operations and uses of Fujitsu
semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on
such information. When you develop equipment incorporating the device based on such information, you
must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for
any damages whatsoever arising out of the use of the information.
• Any information in this document, including descriptions of function and schematic diagrams, shall not be
construed as license of the use or exercise of any intellectual property right, such as patent right or
copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any
third-party' s intellectual property right or other right by using such information. Fujitsu assumes no liability
for any infringement of the intellectual property rights or other rights of third parties which would result from
the use of information contained herein.
• The products described in this document are designed, developed and manufactured as contemplated for
general use, including without limitation, ordinary industrial use, general office use, personal use, and
household use, but are not designed, developed and manufactured as contemplated (1) for use
accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious
effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport
control, medical life support system, missile launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages
arising in connection with above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or
loss from such failures by incorporating safety design measures into your facility and equipment such as
redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.
• If any products described in this document represent goods or technologies subject to certain restrictions on
export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese
government will be required for export of those products from Japan.

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CONTENTS
CHAPTER 1 OVERVIEW OF MB90470 ............................................................................. 1
1.1 Overview ................................................................................................................................................ 2
1.2 Block Diagram of MB90470 ................................................................................................................... 5
1.3 Package Dimensions ............................................................................................................................. 6
1.4 Pin Assignment ...................................................................................................................................... 8
1.5 Pin Functions ....................................................................................................................................... 10
1.6 I/O Circuit Type .................................................................................................................................... 16
1.7 Handling the Device ............................................................................................................................. 19
CHAPTER 2 CPU ............................................................................................................. 21
2.1 Overview of CPU Specifications .......................................................................................................... 22
2.2 Memory Space ..................................................................................................................................... 23
2.3 CPU Registers ..................................................................................................................................... 27
2.3.1 Accumulator (A) .............................................................................................................................. 29
2.3.2 User Stack Pointer (USP) and System Stack Pointer (SSP) .......................................................... 30
2.3.3 Processor Status (PS) .................................................................................................................... 31
2.3.4 Program Counter (PC) .................................................................................................................... 34
2.3.5 Program Count Bank Register (PCB) ............................................................................................. 35
2.3.6 Direct Page Register (DPR) ........................................................................................................... 36
2.3.7 General-Purpose Register (Register Bank) .................................................................................... 37
2.4 Prefix Codes ........................................................................................................................................ 38
CHAPTER 3 INTERRUPT ................................................................................................ 41
3.1 Overview .............................................................................................................................................. 42
3.2 Interrupt Factor and Interrupt Vector ................................................................................................... 44
3.3 Interrupt Control Register and Peripheral Function ............................................................................. 47
3.3.1 Interrupt Control Register (ICR00 to ICR15) .................................................................................. 49
3.3.2 Interrupt Control Register Functions ............................................................................................... 52
3.4 Hardware Interrupt ............................................................................................................................... 55
3.4.1 Hardware Interrupt Operation ......................................................................................................... 58
3.4.2 Flow of Hardware Interrupt Operation ............................................................................................ 60
3.4.3 Procedure for Using Hardwar Interrupt ........................................................................................... 61
3.4.4 Multiple Interrupts ........................................................................................................................... 63
3.4.5 Hardware Interrupt Processing Time .............................................................................................. 65
3.5 Software Interrupt ................................................................................................................................ 67
3.6 Interrupt by µDMA ............................................................................................................................... 69
3.6.1 DMA Descriptor .............................................................................................................................. 73
3.6.2 Individual Registers of DMA Descriptor .......................................................................................... 75
3.6.3 DMA Processing Procedure ........................................................................................................... 78
3.6.4 µDMA Processing Time .................................................................................................................. 79
3.7 Interrupt of Extended Intelligent I/O Service (EI2OS) .......................................................................... 81
3.7.1 Extended Intelligent I/O Service (EI2OS) Descriptor (ISD) ............................................................. 83
3.7.2 Description of Extended Intelligent I/O service (EI2OS) descriptor (ISD) ....................................... 85
3.7.3 Operation of Extended Intelligent I/O Service (EI2OS) .................................................................. 88

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3.7.4 Setting procedure of Extended Intelligent I/O Service (EI2OS) ..................................................... 89
3.7.5 Processing Time for Extended Intelligent I/O Service (EI2OS) ..................................................... 90
3.8 Exception Processing Interrupt by Executing Undefined Instruction .................................................. 93
3.9 Stack Operation of Interrupt Processing ............................................................................................. 94
3.10 Sample Program of Interrupt Processing ............................................................................................ 96
3.11 Delay Interrupt Event Module ............................................................................................................. 99
3.11.1 Operation of Delay Interrupt Event Module ................................................................................. 100
CHAPTER 4 RESET ...................................................................................................... 101
4.1 Overview of Reset ............................................................................................................................. 102
4.2 Reset Factors and Oscillation Stabilization Wait Time ..................................................................... 104
4.3 External-Reset Pin ............................................................................................................................ 106
4.4 Resetting ........................................................................................................................................... 107
4.5 Reset-Factor Bits .............................................................................................................................. 109
4.6 Condition of Pins as Result of Reset ................................................................................................ 111
CHAPTER 5 CLOCKS ................................................................................................... 113
5.1 Overview ........................................................................................................................................... 114
5.2 Block Diagram of Clock Generator ................................................................................................... 116
5.3 Clock Selection Register (CKSCR) ................................................................................................... 118
5.4 Clock Modes ..................................................................................................................................... 121
5.5 Oscillation Stabilization Wait Time .................................................................................................... 125
5.6 Connecting Oscillator to External Clock ............................................................................................ 126
CHAPTER 6 LOW-POWER CONSUMPTION MODE .................................................... 127
6.1 Overview of Low-Power Consumption Mode .................................................................................... 128
6.2 Block Diagram of Low-power Control Circuit .................................................................................... 131
6.3 Low-Power Consumption Mode Control Register (LPMCR) ............................................................. 133
6.4 CPU Intermittent Operation Mode ..................................................................................................... 136
6.5 Standby Mode ................................................................................................................................... 137
6.5.1 Sleep Mode .................................................................................................................................. 138
6.5.2 Timebase Timer Mode ................................................................................................................. 140
6.5.3 Watch Mode ................................................................................................................................. 142
6.5.4 Stop Mode ................................................................................................................................... 144
6.6 State Transition Diagram .................................................................................................................. 146
6.7 Pin State in Standby Mode, Hold, and Reset .................................................................................... 148
6.8 Caution on Using Low-Power Consumption Mode ........................................................................... 153
CHAPTER 7 MODE SETTING ....................................................................................... 157
7.1 Mode Setting ..................................................................................................................................... 158
7.2 Mode Pins (MD2 to MD0) ................................................................................................................. 159
7.3 Mode Data ........................................................................................................................................ 160
7.4 External Memory Access .................................................................................................................. 164
7.4.1 Automatic ready function selection register (ARSR) .................................................................... 166
7.4.2 External address output control register (HACR) ......................................................................... 168
7.4.3 Bus control signal selection register (EPCR) ............................................................................... 169
7.5 Operation of Each Mode for Mode Setting ........................................................................................ 171
7.5.1 External memory access control signals ...................................................................................... 172

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7.5.2 Ready function .............................................................................................................................. 175
7.5.3 Hold function ................................................................................................................................. 178
CHAPTER 8 I/O PORT ................................................................................................... 181
8.1 Functions of I/O Port .......................................................................................................................... 182
8.2 Registers for I/O Port ......................................................................................................................... 183
8.2.1 Port registers (PDR0 to PDRA) .................................................................................................... 184
8.2.2 Port direction registers (DRR0 to DRRA) ..................................................................................... 185
8.2.3 Other registers .............................................................................................................................. 187
CHAPTER 9 TIMEBASE TIMER .................................................................................... 189
9.1 Overview ............................................................................................................................................ 190
9.2 Timebase Timer Configuration .......................................................................................................... 192
9.3 Timebase Timer Control Register (TBTC) ......................................................................................... 194
9.4 Timebase Timer Interrupt .................................................................................................................. 196
9.5 Timebase Timer Operation ................................................................................................................ 197
9.6 Notes on Using Timebase Timer ....................................................................................................... 199
9.7 Sample Programs .............................................................................................................................. 201
CHAPTER 10 WATCHDOG TIMER ................................................................................. 203
10.1 Overview ............................................................................................................................................ 204
10.2 Watchdog Timer Control Register (WDTC) ....................................................................................... 206
10.3 Watchdog Timer Configuration .......................................................................................................... 208
10.4 Watchdog Timer Operation ................................................................................................................ 210
10.5 Notes on Using Watchdog Timer ....................................................................................................... 212
10.6 Sample Programs .............................................................................................................................. 213
CHAPTER 11 WATCH TIMER ......................................................................................... 215
11.1 Overview ............................................................................................................................................ 216
11.2 Watch Timer Configuration ................................................................................................................ 217
11.3 Watch Timer Control Register (WTC) ................................................................................................ 218
11.4 Watch Timer Operation ...................................................................................................................... 220
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER ................................................................ 223
12.1 Overview ............................................................................................................................................ 224
12.2 16-bit Input/Output Timer Register .................................................................................................... 226
12.2.1 16-bit free-running timer ............................................................................................................... 227
12.2.2 Output compare ............................................................................................................................ 232
12.2.3 Input capture ................................................................................................................................. 236
12.3 16-bit Input/Output Timer Operation .................................................................................................. 239
12.3.1 Operation of 16-bit free-running timer .......................................................................................... 240
12.3.2 Operation of 16-bit output compare .............................................................................................. 242
12.3.3 Operation of 16-bit input capture .................................................................................................. 244
12.3.4 16-bit free-running timer timing ..................................................................................................... 245
12.3.5 Output compare timing ................................................................................................................. 246
12.3.6 Timing of input capture ................................................................................................................. 247
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER ................................................... 249

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13.1 Overview ........................................................................................................................................... 250
13.2 Registers for 8/16-bit Up/Down Counter/Timer ................................................................................. 253
13.2.1 Counter control register H0 (CCRH0) .......................................................................................... 254
13.2.2 Counter control register H1 (CCRH1) .......................................................................................... 256
13.2.3 Counter control register L0/1 (CCRL0/1) ..................................................................................... 258
13.2.4 Counter status register 0/1 (CSR0/1) ........................................................................................... 260
13.2.5 Up/down count register 0/1 (UDCR0/1) ....................................................................................... 262
13.2.6 Reload/compare register 0/1 (RCR0/1) ....................................................................................... 263
13.3 8/16-bit Up/Down Counter/Timer Operation ..................................................................................... 264
13.3.1 Reload/compare function ............................................................................................................. 267
13.3.2 Writing data to up/down count register (UDCR) ........................................................................... 270
CHAPTER 14 PWC TIMER .............................................................................................. 273
14.1 Overview of PWC Timer ................................................................................................................... 274
14.2 PWC Timer Registers ....................................................................................................................... 276
14.2.1 PWC Control/Status Register (PWCSR0 to PWCSR2) ............................................................... 277
14.2.2 PWC Data Buffer Register (PWCR0 to PWCR2) ......................................................................... 282
14.2.3 Divide Ratio Control Register (DIVR0 to DIVR2) ......................................................................... 283
14.3 Operations of PWC Timer ................................................................................................................. 284
14.3.1 Operations of the Timer Function ................................................................................................ 285
14.3.2 Operations of the Pulse Width Measurement Function ............................................................... 286
14.3.3 Selection of Count Clock and Operation Mode ............................................................................ 288
14.3.4 Start and Stop of Timer/Pulse Width Measurement ..................................................................... 290
14.3.5 Timer Mode Operation ................................................................................................................. 292
14.3.6 Operation in Pulse Width Measurement Mode ............................................................................ 295
14.4 Notes on PWC Timer Usage ............................................................................................................. 301
CHAPTER 15 µ
µµ
µPG TIMER ............................................................................................... 303
15.1 Overview of µPG Timer ..................................................................................................................... 304
15.2 µPG Timer Registers ........................................................................................................................ 305
15.3 Timing Chart of µPG Timer ............................................................................................................... 307
CHAPTER 16 16-BIT RELOAD TIMER ........................................................................... 309
16.1 Overview of 16-Bit Reload Timer ...................................................................................................... 310
16.1.1 Functions of the 16-Bit Reload Timer .......................................................................................... 311
16.1.2 Block Diagram of the 16-Bit Reload Timer ................................................................................... 313
16.2 16-Bit Reload Timer Registers .......................................................................................................... 314
16.2.1 Timer Control Status Register (TMCSR) ..................................................................................... 315
16.2.2 16-Bit Timer Register (TMR)/16-Bit Reload Register (TMRLR) ................................................... 319
16.3 Operations of the 16-Bit Reload Timer ............................................................................................. 321
16.3.1 State Transitions During Counter Operation ................................................................................ 322
16.3.2 Operations of Internal Clock Mode (Reload Mode) ...................................................................... 323
16.3.3 Internal Clock Mode (One-Shot Mode) ........................................................................................ 325
16.3.4 Event Count Mode ....................................................................................................................... 327
CHAPTER 17 8/16-BIT PPG TIMER ................................................................................ 329
17.1 Overview of 8/16-bit PPG Timer ....................................................................................................... 330
17.1.1 Block Diagram of the 8/16-Bit PPG Timer ................................................................................... 331

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17.2 8/16-bit PPG Timer Registers ............................................................................................................ 333
17.2.1 PPG0/2/4 Operation Mode Control Register (PPGC0) ................................................................. 334
17.2.2 PPG1/3/5 Operation Mode Control Register (PPGC1) ................................................................. 336
17.2.3 PPG0 to PPG5 Output Control Registers (PPG0/1, PPG2/3, PPG4/5) ........................................ 339
17.2.4 Reload Registers (PPLL0 to PPLL5, PPLH0 to PPLH5) .............................................................. 341
17.3 Operations of 8/16-Bit PPG Timer ..................................................................................................... 342
CHAPTER 18 DTP/EXTERNAL INTERRUPT UNIT ........................................................ 347
18.1 Overview of DTP/External Interrupt Unit ............................................................................................ 348
18.2 DTP/External Interrupt Unit Registers ............................................................................................... 349
18.3 Operations of DTP/External Interrupt Unit ......................................................................................... 351
18.4 Notes on DTP/External Interrupt Unit Usage ..................................................................................... 353
CHAPTER 19 8/10-BIT A/D CONVERTER ...................................................................... 355
19.1 Overview of 8/10-bit A/D Converter ................................................................................................... 356
19.2 8/10-bit A/D Converter Registers ....................................................................................................... 358
19.2.1 Control Status Register 1 (ADCS1) .............................................................................................. 359
19.2.2 Control Status Register 2 (ADCS2) .............................................................................................. 362
19.2.3 Data Registers (ADCR2 and ADCR1) .......................................................................................... 365
19.3 Operations of 8/10-bit A/D Converter ................................................................................................ 366
19.3.1 Example of µDMA Start in Single Mode ....................................................................................... 368
19.3.2 Example of µDMA Start in Continuous Mode ............................................................................... 370
19.3.3 Example of µDMA Start in Stop Mode .......................................................................................... 372
19.4 Conversion Data Protection Function ................................................................................................ 374
19.5 Precautions When Using the 8/10-bit A/D Converter ........................................................................ 376
CHAPTER 20 EXPANDED I/O SERIAL INTERFACE ..................................................... 377
20.1 Overview of Expanded I/O Serial Interface ........................................................................................ 378
20.2 Registers of Expanded I/O Serial Interface ....................................................................................... 379
20.2.1 Serial Mode Control Status Register (SMCS) .............................................................................. 380
20.2.2 Serial Shift Data Register (SDR) .................................................................................................. 384
20.2.3 Dedicated Prescaler Control Register (SDCR) ............................................................................. 385
20.3 Operation of Expanded I/O Serial Interface ....................................................................................... 386
20.3.1 Shift Clock Modes ......................................................................................................................... 387
20.3.2 Operational States of Serial I/O Units ........................................................................................... 388
20.3.3 Start/Stop Timing and Input/Output Timing of Shift Operation ..................................................... 390
20.3.4 Interrupt Function ......................................................................................................................... 392
CHAPTER 21 UART ......................................................................................................... 393
21.1 Overview of the UART ....................................................................................................................... 394
21.2 UART Registers ................................................................................................................................. 396
21.2.1 Serial Mode Register (SMR) ......................................................................................................... 397
21.2.2 Serial Control Register (SCR) ...................................................................................................... 399
21.2.3 Serial Input/Output Register (SIDR/SODR) .................................................................................. 401
21.2.4 Serial Status Register (SSR) ........................................................................................................ 402
21.2.5 Communication Prescaler Control Register (CDCR) .................................................................... 404
21.3 UART Operations .............................................................................................................................. 406
21.3.1 Operation in Asynchronous Mode (Operation Modes 0 and 1) .................................................... 410

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21.3.2 Operation in Synchronous Mode (Operation Mode 2) ................................................................. 413
21.3.3 Two-Way Communication Function (Normal Mode) .................................................................... 415
21.3.4 Master/Slave Communication Function (Multiprocessor Mode) .................................................. 417
21.4 Precautions on Using the UART ....................................................................................................... 420
21.5 UART Program Example .................................................................................................................. 421
CHAPTER 22 I2C INTERFACE ........................................................................................ 423
22.1 Overview of I2C Interface .................................................................................................................. 424
22.2 I2C Interface Registers ...................................................................................................................... 426
22.2.1 Bus Status Register (IBSR) ......................................................................................................... 427
22.2.2 Bus Control Register (IBCR) ........................................................................................................ 429
22.2.3 Clock Control Register (ICCR) ..................................................................................................... 432
22.2.4 Address Register (IADR) ............................................................................................................. 434
22.2.5 Data Register (IDAR) ................................................................................................................... 435
22.3 I2C Interface Operation ..................................................................................................................... 436
CHAPTER 23 CHIP SELECTION FACILITY ................................................................... 439
23.1 Overview of Chip Selection Facility ................................................................................................... 440
23.2 Registers of Chip Selection Facility .................................................................................................. 441
23.2.1 Chip Select Area MASK Register (CMRx) ................................................................................... 442
23.2.2 Chip Selection Area Register (CARx) .......................................................................................... 443
23.2.3 Chip Selection Control Register (CSCR) ..................................................................................... 444
23.2.4 Chip Selector Active Level Register (CALR) ................................................................................ 445
23.3 Operation of the Chip Selection Facility ............................................................................................ 446
CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION .......................................... 449
24.1 Overview of Address Match Detection Function ............................................................................... 450
24.2 Block Diagram of Address Match Detection Function ....................................................................... 451
24.3 Configuration of Address Match Detection Function ......................................................................... 452
24.3.1 Address Detection Control Register (PACSR) ............................................................................. 453
24.3.2 Detect Address Setting Registers (PADR0H and PADR1) ......................................................... 455
24.4 Explanation of Operation of Address Match Detection Function ...................................................... 457
24.4.1 Example of using Address Match Detection Function ................................................................. 458
24.5 Program Example of Address Match Detection Function ................................................................. 463
CHAPTER 25 ROM MIRROR FUNCTION SELECTION MODULE ................................. 465
25.1 Overview of ROM Mirror Function Select Module ............................................................................. 466
25.2 ROM Mirror Function Select Register (ROMM) ................................................................................ 467
CHAPTER 26 2M BIT FLASH MEMORY ......................................................................... 469
26.1 Overview of 2M Bit Flash Memory .................................................................................................... 470
26.2 Sector Configuration of 2M Bit Flash Memory .................................................................................. 471
26.3 Control Status Register (FMCS) ....................................................................................................... 472
26.4 Method for Starting the Flash Memory's Automatic Algorithm .......................................................... 475
26.5 Verifying the Execution State of the Automatic Algorithm ................................................................. 476
26.5.1 Data Polling Flag (DQ7) ............................................................................................................... 478
26.5.2 Toggle Bit Flag (DQ6) .................................................................................................................. 480
26.5.3 Timing Limit Excess Flag (DQ5) .................................................................................................. 481

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26.5.4 Sector Erase Timer Flag (DQ3) .................................................................................................... 482
26.6 Flash Memory Write/Erase Operations .............................................................................................. 483
26.6.1 Setting the Flash Memory to Read/Reset State ........................................................................... 484
26.6.2 Writing Data to Flash Memory ...................................................................................................... 485
26.6.3 Erasing All Data in the Flash Memory (Chip Erase) ..................................................................... 487
26.6.4 Erasing Arbitrary Data in Flash Memory (Sector Erase) .............................................................. 488
26.6.5 Suspending Sector Erasure for the Flash Memory ....................................................................... 490
26.6.6 Resuming the Sector Erasure of Flash Memory ........................................................................... 491
CHAPTER 27 EXAMPLES OF MB90F474/MB90F476 SERIAL PROGRAMMING
CONNECTION ........................................................................................... 493
27.1 Basic Configuration ............................................................................................................................ 494
27.2 Oscillation Clock Frequency and Serial Clock Input Frequency ........................................................ 496
27.3 System Configuration of Flash Microcomputer Programmer ............................................................. 497
27.4 Examples of Serial Programming Connection ................................................................................... 498
27.4.1 Example of Connection in Single-Chip Mode (Using Power from User System) ......................... 499
27.4.2 Example of Minimum Connection with Flash Microcomputer Programmer (Using Power from the User
System) ........................................................................................................................................ 501
APPENDIX .......................................................................................................................... 503
APPENDIX A Memory Map ......................................................................................................................... 504
APPENDIX B Instructions ............................................................................................................................ 515
B.1 Instruction Types ............................................................................................................................. 516
B.2 Addressing ...................................................................................................................................... 517
B.3 Direct Addressing ............................................................................................................................ 519
B.4 Indirect Addressing ......................................................................................................................... 524
B.5 Execution Cycle Count .................................................................................................................... 530
B.6 Effective Address Field ................................................................................................................... 533
B.7 How to Read the Instruction List ..................................................................................................... 534
B.8 F2MC-16LX Instruction List ............................................................................................................. 537
B.9 Instruction Map ................................................................................................................................ 551
INDEX .................................................................................................................................. 573

xii

1
CHAPTER 1 OVERVIEW OF MB90470
This chapter gives an overview of MB90470, including its basic characteristics, block
diagram, and its functions.
1.1 "Overview"
1.2 "Block Diagram of MB90470"
1.3 "Package Dimensions"
1.4 "Pin Assignment"
1.5 "Pin Functions"
1.6 "I/O Circuit Type"
1.7 "Handling of the Devices"

2
CHAPTER 1 OVERVIEW OF MB90470
1.1 Overview
MB90470 is a 16-bit microcontroller designed for applications such as consumer
devices requiring high-speed real-time processing. MB90470 functions are suitable for
controlling PHS, cellular phones, CD-ROMs, and VCRs.
■MB90470 features
The MB90470 has the following features:
• Minimum instruction execution time
• 50.0 ns/5 MHz oscillation multiplied by 4 (20 MHz/3.3 0.3 V for internal operation)
• 62.5 ns/4 MHz oscillation multiplied by 4 (16 MHz/3.0 0.3 V for internal operation)
• PLL clock multiply system
• Maximum memory space: 16 MB
• Instruction system optimized for control applications
• Available data types: bit, byte, word, long word
• Standard addressing modes: 23 types
• Improved high-precision operation using a 32-bit accumulator
• Signed multiply and divide operations, extensive RETI instruction
• Instruction system supporting multitasking in high-level languages (such as C)
• Use of a system stack pointer
• Symmetry of instruction sets and barrel shift instructions
• Multi-bus and non-multi-bus support
• Program patch function (for two address pointers)
• Improved execution speed: 4-byte queue
• Improved interrupt function (priority is a programmable setting of up to 8 levels): 8 external
interrupts
• Data transfer function (µDMAC): maximum of 16 channels
• Built-in ROM (FLASH version: 256 KB; MASKROM version: 128 KB/256 KB)
• Built-in RAM: 10 KB/16 KB
• General-purpose ports: maximum of 84 ports (input pull-up resistor settings available for 16
ports, output open drain settings available for 14 ports, and output open drain for 2 ports)
• A/D converter (RC step-by-step compare type): 8 channels (resolution: 10 bits; conversion
time: 4.65 µs (20 MHz operation))
•I
2C interface: 1 channel
•µPG: 1 channel
• UART: 1 channel
• I/O extensive serial interface (SIO): 2 channels

3
CHAPTER 1 OVERVIEW OF MB90470
• 16-bit PPG: 3 channels (8 bits x 6 channels; mode switching function of 16 bits x 3 channels)
• 8/16-bit U/D timer: 1 channel
• 16-bit PWC: 3 channels (function that compares input by two of the three channels is
installed)
• 16-bit reload timer: 1 channel(8 bits x 2 channels; mode switching function of 16 bits x 1
channel)
• 16-bit input/output timer (input capture x 2 channels; output compare x 6 channels; free-run
timer x 1 channel)
• Built-in dual-system clock generator
• Power-saving mode (e.g., stop, sleep, CPU intermittent operation mode, watch mode)
• Package: QFP100/LQFP100
• CMOS technology
• Available for 3-V single power supply (some pins supply 3/5 V of power from a dual power
supply to support 5-V I/F)

4
CHAPTER 1 OVERVIEW OF MB90470
■Product configuration
Table 1.1-1 "MB90470-series product configuration" is an outline of the MB90470-series product
configuration.
Note:
Writing FLASH requires VCC = 3 V or more.
Table 1.1-1 MB90470-series product configuration
MB90V470B MB90F474L MB90F474H
ROM capacity - FLASH 256KB FLASH 256KB
RAM capacity 16KB 16KB 16KB
Description
EVA function
3-V/5-V version of user
pin*1
FLASH product
Low-voltage version
(VCC=2.4 V; f=10 MHz or
less)
FLASH product
High-speed version
(f=20 MHz)
Emulator-dedicated
power supply*2 Provided - -
MB90473 MB90474 MB90477 MB90478
ROM capacity MASKROM
128KB
MASKROM
256KB
MASKROM 256KB MASKROM
256KB
RAM capacity 10KB 16KB 8KB 8KB
Description MASK product MASK product MASK product
MASK product
I2C interface not
installed
Emulator-dedicated
power supply*2 Provided Provided - -
*1: User pins: P20 to P27, P30 to P37, P40 to P47, P70 to P77
*2: The setting of dip switch S2 is applicable during use of emulation pod MB2145-507.
For more information, refer to the MB2145-507 hardware manual (Section 2.7, "Emulator-specific Power
Supply").