Fujitsu MB91150 Series User manual

FUJITSU LIMITED
FR30
32-BIT MICROCONTROLLER
MB91150 Series
HARDWARE MANUAL

i
PREFACE
■Objectives and Intended Reader
The MB91150 Series, hereafter referred to as MB91150, is a member of the "32-bit single-chip
microcontroller FR30 Series" family and has a CPU based on a new RISC architecture at its
core. This single-chip microcontroller contains peripheral I/O resources suited for audio
equipment and MD drives that require low power consumption.
This manual is for engineers who develop products incorporating the MB91150. It also
describes the functions and operation of the MB91150. Read this manual thoroughly. For details
on each instruction, see the Instructions Manual.
■Trademarks
FR is an abbreviation of FUJITSU RISC controller and a product of FUJITSU LIMITED.
Embedded AlgorithmTM is a trademark of Advanced Micro Device Corporation.
■License
Purchase of FUJITSU I2C components conveys a license under the Philips I2C Patent Right to
use these components in the I2C system, provided that the system conforms to the I2C
Standard Specification as defined by Philips.

ii
■Structure of This Manual
This manual contains 21 chapters and one appendix.
CHAPTER 1 "OVERVIEW OF THE MB91150"
This chapter provides basic items that are required to fully understand the MB91150, such
as a description of MB91150 features, block diagrams, and an outline of functions.
CHAPTER 2 "HANDLING THE DEVICE"
This chapter provides details on handling the MB91150.
CHAPTER 3 "MEMORY SPACE, CPU AND CONTROL UNIT"
This chapter describes basic items that are required to understand the FR Series CPU core
functions, its architecture, specifications, and instructions.
CHAPTER 4 "BUS INTERFACE"
This chapter describes the bus interface and bus operation.
CHAPTER 5 "I/O PORTS"
This chapter describes the I/O ports and provides the block diagrams of individual ports. It
also describes the structure and functions of registers.
CHAPTER 6 "8/16-BIT UP/DOWN COUNTER/TIMER"
This chapter describes the 8-bit and 16-bit up/down counter/timer and provides their block
diagrams. It also describes the structures and functions of registers and the operations of the
8-bit and 16-bit up/down counter/timer.
CHAPTER 7 "16-BIT RELOAD TIMER"
This chapter describes the 16-bit reload timer. It also describes the operations of the 16-bit
reload timer, block diagram, and the structures and functions of the timer registers.
CHAPTER 8 "PPG TIMER"
This chapter describes the PPG timer. It also describes the operations of the PPG timer,
block diagram, and the structures and functions of the timer registers.
CHAPTER 9 "MULTIFUNCTIONAL TIMER"
This chapter describes the multifunctional timer. It also describes the operations of the
multifunctional timer, block diagram, and the structures and functions of the timer registers.
CHAPTER 10 "EXTERNAL INTERRUPT CONTROL BLOCK"
This chapter describes the external interrupt control block. It also describes the operation of
the external interrupt control block, and the structures and functions of the related registers.
CHAPTER 11 "DELAYED INTERRUPT MODULE"
This chapter describes the delayed interrupt module. It also describes the operation of the
delayed interrupt module, and the structures and functions of related registers.
CHAPTER 12 "INTERRUPT CONTROLLER"
This chapter describes the interrupt controller and provides its block diagram. It also
describes the structures and functions of registers and the operation of the interrupt
controller.
CHAPTER 13 "8/10-BIT A/D CONVERTER"
This chapter describes the 8-bit D/A converter and provides its block diagram. It also
describes pins, structures and functions of registers, interrupts, device operation, and the A/
D conversion data protection function. The chapter also provides notes on using the 8/10-bit
A/D converter.

iii
CHAPTER 14 "8-BIT D/A CONVERTER"
This chapter describes the 8-bit D/A converter. It also describes the operation of the
converter, block diagram, and the structures and functions of the converter registers.
CHAPTER 15 "UART"
This chapter describes the UART and provides its block diagram. It also describes pins,
structures and functions of registers, interrupts, timing, baud rates, and device operation.
The chapter also provides notes on using the UART.
CHAPTER 16 "I2C INTERFACE"
This chapter describes the I2C interface and provides its block diagram. It also describes
register structures and functions and I2C interface operation.
CHAPTER 17 "DMAC"
This chapter describes the DMAC and provides its block diagram. It also describes registers,
operation, DMA transfer sources, and DMAC timing. The chapter also provides notes on
using the DMAC.
CHAPTER 18 "BIT SEARCH MODULE"
This chapter describes the bit search module. It also describes the structures and functions
of bit search module registers, and the processing for saving and restoring.
CHAPTER 19 "PERIPHERAL STOP CONTROL"
This chapter describes peripheral stop control and structures and functions of the registers.
CHAPTER 20 "CALENDAR MACROS"
This chapter describes the calendar macros, structures and functions of registers, and the
operation of the calendar macro.
CHAPTER 21 "FLASH MEMORY"
This chapter describes the flash memory, structures and functions of the registers, device
operation, and the automation algorithm. It also provides detailed information on flash
memory writing and erasing.
APPENDIX
The appendix contains I/O maps and information on the interrupt vectors, pin status for
various CPU states, details regarding the little-endian area, and references for programming.

iv
©2003 FUJITSU LIMITED Printed in Japan
• The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales representatives before ordering.
• The information, such as descriptions of function and application circuit examples, in this document are presented
solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device;
Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you
develop equipment incorporating the device based on such information, you must assume any responsibility
arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of
the use of the information.
• Any information in this document, including descriptions of function and schematic diagrams, shall not be
construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or
any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party' s intellectual
property right or other right by using such information. Fujitsu assumes no liability for any infringement of the
intellectual property rights or other rights of third parties which would result from the use of information contained
herein.
• The products described in this document are designed, developed and manufactured as contemplated for general
use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but
are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers
that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to
death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control
in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in
connection with above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy,
fire protection, and prevention of over-current levels and other abnormal operating conditions.
• If any products described in this document represent goods or technologies subject to certain restrictions on
export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese
government will be required for export of those products from Japan.

v
READING THIS MANUAL
■Details Regarding the Manual Format
An explanation of the most important terms in this manual is given in the table below.
Term Meaning
I-BUS 16-bit bus for internal instructions. The FR Series employs internal Harvard
architecture; there are independent buses for instructions and data. A bus
converter is connected to the I-BUS.
D-BUS Internal 32-bit data bus. An internal resource is connected to the D-BUS.
C-BUS Internal multiplex bus. The C-BUS is connected to both the I-BUS and D-Bus
through a switch. An external interface module is connected to the C-BUS. On
external data buses, data and instructions are multiplexed.
R-BUS Internal 16-bit data bus. The R-Bus is connected to the D-BUS via an adapter.
Various I/O devices, a clock generator, and an interrupt controller are connected
to the R-BUS. The R-BUS has a bandwidth of 16 bits over which addresses and
data are multiplexed; CPU access time of these resources is several cycles.
E-unit Arithmetic execution unit
φSystem clock. It provides the clock signals output to each of the built-in
resources connected to the R-BUS from the clock generator. The maximum
clock speed (cycle) is identical to the original clock oscillation. The clock cycle
can be divided by 1, 1/2, 1/4, and 1/8 (or 1/2, 1/4, 1/8, and 1/16) depending on
the setting of the PCK1 and PCK0 bits of the GCR register in the clock
generator.
θSystem clock. Clock used by the CPU and resources connected to a bus other
than the R-BUS. The maximum clock speed (cycle) is identical to the original
clock oscillation. The clock cycle can be divided by 1, 1/2, 1/4, and 1/8 (or 1/2, 1/
4, 1/8, and 1/16) depending on the setting of the CCK1 and CCK0 bits of the
GCR register in the clock generator.

vi

vii
CONTENTS
CHAPTER 1 OVERVIEW OF THE MB91150 ..................................................................... 1
1.1 MB91150 Features ................................................................................................................................ 2
1.2 Block Diagrams ...................................................................................................................................... 5
1.3 Package Dimensions ............................................................................................................................. 7
1.4 Pin Assignment ...................................................................................................................................... 9
1.5 Pin Functions ....................................................................................................................................... 12
1.6 I/O Circuit Types .................................................................................................................................. 20
CHAPTER 2 HANDLING THE DEVICE ........................................................................... 23
2.1 Notes on Handling Devices ................................................................................................................. 24
2.2 Notes on Using Devices ...................................................................................................................... 26
2.3 Power-On ............................................................................................................................................. 27
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT ......................................... 29
3.1 Memory Space ..................................................................................................................................... 30
3.2 CPU Architecture ................................................................................................................................. 33
3.3 Programming Model ............................................................................................................................ 36
3.4 Data Structure ...................................................................................................................................... 44
3.5 Word Alignment ................................................................................................................................... 45
3.6 Special Memory Areas ......................................................................................................................... 46
3.7 Overview of Instructions ...................................................................................................................... 47
3.7.1 Operations with Delay Slots ........................................................................................................... 49
3.7.2 Branch Instructions without a Delay Slot ........................................................................................ 52
3.8 EIT (Exception, Interrupt, and Trap) .................................................................................................... 53
3.8.1 Interrupt Level ................................................................................................................................. 54
3.8.2 Interrupt Stack Operation ............................................................................................................... 55
3.8.3 EIT Vector Table ............................................................................................................................. 56
3.8.4 Multiple EIT Processing .................................................................................................................. 58
3.8.5 EIT Operation ................................................................................................................................. 60
3.9 Reset Sequence .................................................................................................................................. 64
3.10 Operation Mode ................................................................................................................................... 65
3.11 Clock Generator (Low-Power Consumption Mechanism) .................................................................... 67
3.11.1 Reset Source Register (RSRR) and Watchdog Cycle Control Register (WTCR) .......................... 69
3.11.2 Standby Control Register (STCR) .................................................................................................. 71
3.11.3 Time-base Timer Clear Register (CTBR) ....................................................................................... 72
3.11.4 Gear Control Register (GCR) ......................................................................................................... 73
3.11.5 Watchdog Reset Generation Delay Register (WPR) ...................................................................... 75
3.11.6 DMA Request Suppression Register (PDRR) ................................................................................ 76
3.11.7 PLL Control Register (PCTR) ......................................................................................................... 77
3.11.8 Watchdog Function ......................................................................................................................... 78
3.11.9 Gear Function ................................................................................................................................. 80
3.11.10 Retaining a Reset Source ............................................................................................................... 82
3.11.11 Example of Setting the PLL Clock .................................................................................................. 84
3.12 Low-Power Consumption Mode ........................................................................................................... 87

viii
3.12.1 Stop Status .................................................................................................................................... 89
3.12.2 Sleep Status .................................................................................................................................. 92
3.12.3 Status Transition of the Low-power Consumption Mode .............................................................. 95
CHAPTER 4 BUS INTERFACE ....................................................................................... 97
4.1 Outline of Bus Interface ...................................................................................................................... 98
4.2 Block Diagram of the Bus Interface .................................................................................................. 100
4.3 Registers of the Bus Interface ........................................................................................................... 101
4.3.1 Area Select Registers (ASR) and Area Mask Registers (AMR) ................................................... 102
4.3.2 Area Mode Register 0 (AMD0) ..................................................................................................... 104
4.3.3 Area Mode Register 1 (AMD1) ..................................................................................................... 106
4.3.4 Area Mode Register 32 (AMD32) ................................................................................................. 107
4.3.5 Area Mode Register 4 (AMD4) ..................................................................................................... 108
4.3.6 Area Mode Register 5 (AMD5) ..................................................................................................... 109
4.3.7 External Pin Control Register 0 (EPCR0) .................................................................................... 110
4.3.8 External Pin Control Register 1 (EPCR1) .................................................................................... 112
4.3.9 Little-endian Register (LER) ........................................................................................................ 113
4.4 Bus Operation ................................................................................................................................... 114
4.4.1 Relationship Between Data Bus Width and Control Signals ........................................................ 115
4.4.2 Bus Access in Big-endian Mode .................................................................................................. 116
4.4.3 Bus Access in Little-endian Mode ................................................................................................ 122
4.4.4 Comparison of External Access in Big-endian and Little-endian Mode ....................................... 126
4.5 Bus Timing ........................................................................................................................................ 131
4.5.1 Basic Read Cycle ........................................................................................................................ 132
4.5.2 Basic Write Cycle ......................................................................................................................... 134
4.5.3 Read Cycle in Each Mode ........................................................................................................... 136
4.5.4 Write Cycle in Each Mode ........................................................................................................... 138
4.5.5 Mixed Read/Write Cycles ............................................................................................................. 140
4.5.6 Automatic Wait Cycle ................................................................................................................... 141
4.5.7 External Wait Cycle ..................................................................................................................... 142
4.5.8 External Bus Request .................................................................................................................. 143
4.6 Internal Clock Multiply Operation (Clock Doubler) ............................................................................ 144
4.7 Program Examples for the External Bus ........................................................................................... 146
CHAPTER 5 I/O PORTS ................................................................................................ 149
5.1 Overview of I/O Ports ....................................................................................................................... 150
5.2 Block Diagram of Basic I/O Port ....................................................................................................... 151
5.3 Block Diagram of I/O Ports (Including the Pull-up Resistor) ............................................................. 152
5.4 Block Diagram of I/O ports (Including the Open-drain Output and the Pull-up Resistor) .................. 153
5.5 Block Diagram of I/O Port (With Open-Drain Output Function) ........................................................ 155
5.6 Port Data Register (PDR) ................................................................................................................. 156
5.7 Data Direction Register (DDR) .......................................................................................................... 157
5.8 Pull-up Control Register (PCR) ......................................................................................................... 159
5.9 Open-Drain Control Register (ODCR) .............................................................................................. 160
5.10 Analog Input Control Register (AICR) ............................................................................................... 161
CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER ................................................... 163
6.1 Overview of 8/16-Bit Up/Down Counter/Timer .................................................................................. 164

ix
6.2 Block Diagram of the 8/16-bit Up/Down Counter/Timer ..................................................................... 166
6.3 List of Registers of the 8/16-Bit Up/Down Counter/Timer .................................................................. 168
6.3.1 Counter Control Register H/L (CCRH/L) ...................................................................................... 169
6.3.2 Counter Control Register H/L ch1 (CCR H/L Ch1) ....................................................................... 173
6.3.3 Counter status register 0/1 (CSR0/1) ........................................................................................... 174
6.3.4 Up/down count register 0/1 (UDCR 0/1) ....................................................................................... 176
6.3.5 Reload/compare Register 0/1 (RCR 0/1) ...................................................................................... 177
6.4 Selection of Counting Mode ............................................................................................................... 178
6.5 Reload and Compare Functions ........................................................................................................ 181
6.6 Writing data to the up/down count register (UDCR) .......................................................................... 185
CHAPTER 7 16-BIT RELOAD TIMER ........................................................................... 187
7.1 Overview of 16-bit Reload Timer ....................................................................................................... 188
7.2 Block diagram of a 16-bit reload timer ............................................................................................... 189
7.3 Registers of 16-bit Reload Timer ....................................................................................................... 190
7.3.1 Control status register (TMCSR) .................................................................................................. 191
7.3.2 16-bit Timer Register (TMR) and 16-bit Reload Register (TMRLR) ............................................. 193
7.4 Internal Clock Operation .................................................................................................................... 194
7.5 Underflow operation ........................................................................................................................... 195
7.6 Counter Operation States .................................................................................................................. 197
CHAPTER 8 PPG TIMER ............................................................................................... 199
8.1 Overview of PPG Timer ..................................................................................................................... 200
8.2 Block Diagram of PPG Timer ............................................................................................................. 201
8.3 Registers of PPG Timer ..................................................................................................................... 203
8.3.1 Control status registers (PCNH, PCNL) ....................................................................................... 205
8.3.2 PWM cycle set register (PCSR) ................................................................................................... 209
8.3.3 PWM duty set register (PDUT) ..................................................................................................... 210
8.3.4 PWM timer register (PTWR) ......................................................................................................... 211
8.3.5 General control register 1 (GCN1) ................................................................................................ 212
8.3.6 General control register 2 (GCN2) ................................................................................................ 215
8.4 PWM Operation ................................................................................................................................. 216
8.5 One-shot Operation ........................................................................................................................... 218
8.6 PWM Timer Interrupt Source and Timing Chart ................................................................................ 220
8.7 Activating Multiple Channels by Using the General Control Register (GCN) .................................... 222
CHAPTER 9 MULTIFUNCTIONAL TIMER .................................................................... 225
9.1 Overview of Multifunctional Timer ...................................................................................................... 226
9.2 Block Diagram of the Multifunctional Timer ...................................................................................... 228
9.3 Registers of Multifunctional Timer ..................................................................................................... 229
9.3.1 Registers of 16-bit Free-run Timer ............................................................................................... 230
9.3.2 Registers of the Output Compare ................................................................................................. 234
9.3.3 Registers of Input Capture ............................................................................................................ 237
9.4 Operations of Multifunctional Timer ................................................................................................... 239
9.4.1 Operation of 16-bit Free-run Timer ............................................................................................... 240
9.4.2 Operation of 16-bit Output Compare ............................................................................................ 242
9.4.3 Operation of 16-bit Input Capture ................................................................................................. 245

x
CHAPTER 10 EXTERNAL INTERRUPT CONTROL BLOCK ......................................... 247
10.1 Overview of External Interrupt .......................................................................................................... 248
10.2 External Interrupt Registers .............................................................................................................. 249
10.2.1 Enable Interrupt Register (ENIRn) ............................................................................................... 250
10.2.2 External Interrupt Request Register (EIRRn) ............................................................................... 251
10.2.3 External Interrupt Level Setting Register (ELVR: External Level Register) ................................. 252
10.3 External Interrupt Operation .............................................................................................................. 253
10.4 External Interrupt Request Level ...................................................................................................... 254
CHAPTER 11 DELAYED INTERRUPT MODULE ........................................................... 255
11.1 Overview of Delayed Interrupt Module .............................................................................................. 256
11.2 Delayed Interrupt Control Register (DICR) ....................................................................................... 257
11.3 Operation of Delayed Interrupt Module ............................................................................................. 258
CHAPTER 12 INTERRUPT CONTROLLER .................................................................... 259
12.1 Overview of Interrupt Controller ........................................................................................................ 260
12.2 Block Diagram of the Interrupt Controller .......................................................................................... 261
12.3 List of Interrupt Controller Registers ................................................................................................. 262
12.3.1 Interrupt Control Register (ICR) ................................................................................................... 264
12.3.2 Hold-Request Cancellation-Request Level-Set Register (HRCL) ................................................ 266
12.4 Priority Evaluation ............................................................................................................................. 267
12.5 Return from Standby (Stop or Sleep) Mode ...................................................................................... 269
12.6 Hold-Request Cancellation Request ................................................................................................. 270
12.7 Example of Using Hold-Request Cancellation-Request Function (HRCR) ....................................... 271
CHAPTER 13 8/10-BIT A/D CONVERTER ...................................................................... 275
13.1 Overview of the 8/10-bit A/D Converter ............................................................................................ 276
13.2 8/10-bit A/D Converter Block Diagram .............................................................................................. 277
13.3 8/10-bit A/D Converter Pins .............................................................................................................. 279
13.4 8/10-bit A/D Converter Registers ...................................................................................................... 281
13.4.1 A/D Control Status Register 1 (ADCS1) ...................................................................................... 282
13.4.2 A/D Control Status Register 0 (ADCS0) ...................................................................................... 285
13.4.3 A/D Data Register (ADCR) .......................................................................................................... 287
13.5 8/10-bit A/D Converter Interrupt ........................................................................................................ 289
13.6 Operation of the 8/10-bit A/D Converter ........................................................................................... 290
13.7 A/D Converted Data Preservation Function ...................................................................................... 292
13.8 Notes on Using the 8/10-bit A/D Converter ....................................................................................... 293
CHAPTER 14 8-BIT D/A CONVERTER ........................................................................... 295
14.1 Overview of the 8-bit D/A Converter ................................................................................................. 296
14.2 8-bit D/A Converter Block Diagram ................................................................................................... 297
14.3 8-bit D/A Converter Registers ........................................................................................................... 298
14.3.1 D/A Control Registers (DACR0, DACR1, DACR2) ...................................................................... 299
14.3.2 D/A Data Registers (DADR2, DADR1, DADR0) .......................................................................... 300
14.4 8-bit D/A Converter Operation .......................................................................................................... 301
CHAPTER 15 UART ........................................................................................................ 303
15.1 Overview of the UART ...................................................................................................................... 304

xi
15.2 UART Block Diagram ......................................................................................................................... 306
15.3 UART Pins ......................................................................................................................................... 308
15.4 UART Registers ................................................................................................................................. 311
15.4.1 Control register (SCR0-3) ............................................................................................................. 312
15.4.2 Mode register (SMR0-3) ............................................................................................................... 314
15.4.3 Status register (SSR0-3) .............................................................................................................. 316
15.4.4 Input-data register (SIDR0-3), output-data register (SODR0-3) ................................................... 318
15.4.5 Communication prescaler control register (CDCR) ...................................................................... 320
15.5 Interrupts ........................................................................................................................................... 322
15.6 Receive-Interrupt Generation and Flag Set Timing ........................................................................... 324
15.7 Send-Interrupt Generation and Flag Set Timing ................................................................................ 325
15.8 Baud Rate .......................................................................................................................................... 326
15.8.1 Baud Rate Based on the Dedicated Baud-Rate Generator .......................................................... 328
15.8.2 Baud Rate Based on the Internal Timer (16-bit Reload Timer 0) ................................................. 331
15.8.3 Baud Rate Based on the External clock ....................................................................................... 333
15.9 UART Operations .............................................................................................................................. 334
15.9.1 Operation in asynchronous mode (operation modes 0 to 1) ........................................................ 336
15.9.2 Operation in synchronous mode (operation mode 2) ................................................................... 339
15.9.3 Bidirectional communication function (normal mode) ................................................................... 341
15.9.4 Master/slave-type communication function (multiprocessor mode) .............................................. 343
15.10 Notes on Using UART ....................................................................................................................... 345
CHAPTER 16 I2C INTERFACE ........................................................................................ 347
16.1 Overview of I2C Interface ................................................................................................................... 348
16.2 Block Diagram of I2C Interface .......................................................................................................... 349
16.3 Registers of I2C Interface .................................................................................................................. 350
16.3.1 Bus Control Register (IBCR) ........................................................................................................ 351
16.3.2 Bus Status Register (IBSR) .......................................................................................................... 354
16.3.3 Address Register (IADR)/Data Register (IDAR) ........................................................................... 356
16.3.4 Clock Control Register (ICCR) ..................................................................................................... 357
16.4 Operation of I2C Interface .................................................................................................................. 359
CHAPTER 17 DMA CONTROLLER ................................................................................. 361
17.1 Overview of the DMA Controller Overview ........................................................................................ 362
17.2 Block Diagram of the DMA Controller ................................................................................................ 363
17.3 Registers of the DMA Controller ........................................................................................................ 364
17.3.1 DMAC parameter descriptor pointer (DPDP) ............................................................................... 365
17.3.2 MAC control status register (DACSR) .......................................................................................... 366
17.3.3 DMAC pin control register (DATCR) ............................................................................................. 368
17.3.4 Register of the descriptor in RAM ................................................................................................. 370
17.4 Transfer Modes Supported by the DMA Controller ............................................................................ 373
17.4.1 Step Transfer (Single/Block Transfer) .......................................................................................... 376
17.4.2 Continuos Transfer ....................................................................................................................... 377
17.4.3 Burst Transfer ............................................................................................................................... 378
17.4.4 Differences Because of DREQ Sense Mode ................................................................................ 379
17.5 Transfer-Acceptance Signal Output and Transfer-End Signal Output ............................................... 381
17.6 Notes on the DMA Controller ............................................................................................................. 382
17.7 Timing Charts for the DMA Controller ................................................................................................ 384

xii
17.7.1 Timing charts for the descriptor access section ........................................................................... 385
17.7.2 Timing charts for the data transfer section ................................................................................... 387
17.7.3 Timing charts for transfer termination in continuous transfer mode ............................................. 389
17.7.4 Timing charts for the transfer termination operation .................................................................... 391
CHAPTER 18 BIT-SEARCH MODULE ............................................................................ 393
18.1 Overview of the Bit-Search Module .................................................................................................. 394
18.2 Registers of the Bit-Search Module .................................................................................................. 395
18.3 Operation of the Bit-Search Module .................................................................................................. 397
CHAPTER 19 PERIPHERAL STOP CONTROL .............................................................. 399
19.1 Overview of Peripheral Stop Control ................................................................................................. 400
19.2 Peripheral Stop Control Registers .................................................................................................... 401
CHAPTER 20 CALENDAR MACROS ............................................................................. 405
20.1 Overview of Calendar Macros ........................................................................................................... 406
20.2 Calendar Macro Registers ................................................................................................................ 407
20.3 Calendar Macro Operation ................................................................................................................ 411
CHAPTER 21 FLASH MEMORY ..................................................................................... 413
21.1 Overview of Flash Memory ............................................................................................................... 414
21.2 Flash Memory Registers ................................................................................................................... 418
21.3 Flash Memory Operation .................................................................................................................. 421
21.4 Automatic Algorithm of Flash Memory .............................................................................................. 423
21.5 Checking the Automatic Algorithm Execution Status ........................................................................ 427
21.6 Writing and Erasing Flash Memory ................................................................................................... 432
21.6.1 Putting flash memory into read/reset status ................................................................................. 433
21.6.2 Writing data to flash memory ....................................................................................................... 434
21.6.3 Erasing data ................................................................................................................................. 436
21.6.4 Temporarily Stopping and Restarting Sector Erase ..................................................................... 438
APPENDIX .......................................................................................................................... 439
APPENDIX A I/O Map ............................................................................................................................... 440
APPENDIX B Interrupt Vectors ................................................................................................................... 448
APPENDIX C Pin Status in Each CPU State .............................................................................................. 452
APPENDIX D Notes on Using the Little-Endian Area ................................................................................. 459
D.1 C Compiler (fcc911) ....................................................................................................................... 460
D.2 Assembler (fasm911) ..................................................................................................................... 463
D.3 Linker (flnk911) ............................................................................................................................... 464
D.4 Debuggers (sim911, eml911, and mon911) ................................................................................... 465
APPENDIX E Instruction Lists .................................................................................................................... 466
INDEX ...................................................................................................................................487

1
CHAPTER 1 OVERVIEW OF THE MB91150
This chapter provides basic information required to fully understand the MB91150,
such as a description of MB91150 features, block diagrams, and an outline of
functions.
1.1 "MB91150 Features"
1.2 "Comprehensive Block Diagram of MB91150"
1.3 "Exterior Dimensions"
1.4 "Pin Assignment Drawing"
1.5 "Pin Functions"
1.6 "I/O Circuit Types"

2
CHAPTER 1 OVERVIEW OF THE MB91150
1.1 MB91150 Features
The MB91150 is a single-chip microcontroller with peripheral I/O resources suited for
controlling devices such as audio equipment and MD drives that require operation
with low-power consumption. The core of the MB91150 is a 32-bit RISC CPU (FR30
Series).
■MB91150 features
❍CPU
• 32-bit RISC (FR30), load/store architecture, 5-stage pipeline
• 32-bit general-purpose register x 16
• 16-bit fixed-length instructions (basic instruction), one instruction per cycle
• Instructions for memory-to-memory transfer, bit processing, parallel shift, etc.
The instructions are suited for embedded-type usage.
• Instructions for entry/exit functions, multiple load/store instructions for the register contents,
instructions for high-level languages.
• Register interlock function allowing simpler assembler code
• Branch instruction with a delay slot allowing a decrease in overhead for branch processing
• Built-in multiplier, supported on the instruction level
• Signed 32-bit multiplication: 5 cycles
• Signed 16-bit multiplication: 3 cycles
• Interrupt (PC and PS saving): 6 cycles, 16 priority levels
❍Bus interface
• 24-bit address output, 8-bit and 16-bit data I/O
• Basic bus cycle: 2 clock cycles
• Interface for supporting various memory types
• Unused data and address pins can be used as I/O pins.
• Support of little endian mode
❍Internal ROM
• MB91F155A, MB91FV150
• FLASH product, EVA-FLASH product: 510 KB
• MB91155
• Mask product: 510 KB
• MB91154
• Mask product: 384 KB

3
CHAPTER 1 OVERVIEW OF THE MB91150
❍Internal RAM
Mask product, FLASH product, EVA-FLASH product: 2 KB
❍Internal data RAM
• MB91FV150, MB91F155A, MB91155
• EVA-FLASH product, FLASH product, Mask product: 32 KB
• MB91154
• Mask product: 20 KB
❍DMA controller (DMAC)
• DMAC of the descriptor type according to which transfer parameters are allocated in main
storage
• Capable of transferring up to eight internal and external sources
• External source: 3 channels
❍Bit search module
The bit search module makes a one-cycle search for the location of the first I/O bit change
starting with the MSB of a word.
❍Timer
• 16-bit OCU x 8 channels, ICU x 4 channels, free-run timer x 1 channel
• 8-bit or 16-bit up/down timer/counter (8-bit x 2 channels or 16-bit x 1 channel)
• The AIN and BIN pins are shared with internal interrupts.
• 16-bit PPG timer x 6 channels. The cycle and duty of an output pulse can be changed to an
arbitrary value.
• 16-bit reload timer x 4 channels
❍D/A converter
8 bits x 3 channels
❍A/D converter (successive approximation type)
• 10 bits x 8 channels
• Successive approximation type (conversion time: 5.0 µs@33 MHz)
• Singe and scan conversions can be selected, and single, continuous, and stop conversion
modes can be set.
• Hardware-driven or software-driven conversion function

4
CHAPTER 1 OVERVIEW OF THE MB91150
❍Serial I/O
• UART x 4 channels. Each UART can perform clock-synchronized serial transfer with the
LSB/MSB switching function.
• Serial data output and serial clock output can be selected by open-drain or push-pull
software.
• Built-in 16-bit timer (U-Timer) as a dedicated baud rate generator, which can generate any
baud rate
❍I2C bus interface
• 1-channel master/slave transmission/reception
• Arbitration function and clock synchronization function
• (As long as the customer uses this product in an I2C system conforming to the I2C
Standard Specifications prepared by Philips, the customer is granted a license of the I2C
patent of Philips.)
❍Clock switching function
The ratio of the operating clock to the base clock can independently be set with the gear
function to 1:1. 1:2, 1:4, or 1:8 for the CPU and for each peripheral device.
❍Clock function (calendar macro)
• Built-in 32 kHz clock function
• The 32 kHz oscillation clock function can operate in stop mode as well.
• (32-kHz oscillation does not stop in stop mode.)
❍Interrupt controller
• External interrupt input (up to 16 channels)
• The leading edge, trailing edge, H level, or L level can be set.
• Internal interrupt source
• Resource interrupt, delayed interrupt
❍Other features
• Reset sources
• Power-on reset, watchdog timer, software reset, and external reset
• Low-power consumption mode
• Sleep mode and stop mode
• Packages
• PGA-299 (MB91FV150)
• LQFP-144 [MB91F155A, MB91155, MB91154]
• CMOS technology (0.35 µm)
• Power supply
• 3.15 V to 3.6 V