Fujitsu MB91150 Series User manual

FUJITSU LIMITED
FR30
32-BIT MICROCONTROLLER
MB91150 Series
HARDWARE MANUAL

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PREFACE
■Objectives and Intended Reader
The MB91150 Series, hereafter referred to as MB91150, is a member of the "32-bit single-chip
microcontroller FR30 Series" family and has a CPU based on a new RISC architecture at its
core. This single-chip microcontroller contains peripheral I/O resources suited for audio
equipment and MD drives that require low power consumption.
This manual is for engineers who develop products incorporating the MB91150. It also
describes the functions and operation of the MB91150. Read this manual thoroughly. For details
on each instruction, see the Instructions Manual.
■Trademarks
FR is an abbreviation of FUJITSU RISC controller and a product of FUJITSU LIMITED.
Embedded AlgorithmTM is a trademark of Advanced Micro Device Corporation.
■License
Purchase of FUJITSU I2C components conveys a license under the Philips I2C Patent Right to
use these components in the I2C system, provided that the system conforms to the I2C
Standard Specification as defined by Philips.

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■Structure of This Manual
This manual contains 21 chapters and one appendix.
CHAPTER 1 "OVERVIEW OF THE MB91150"
This chapter provides basic items that are required to fully understand the MB91150, such
as a description of MB91150 features, block diagrams, and an outline of functions.
CHAPTER 2 "HANDLING THE DEVICE"
This chapter provides details on handling the MB91150.
CHAPTER 3 "MEMORY SPACE, CPU AND CONTROL UNIT"
This chapter describes basic items that are required to understand the FR Series CPU core
functions, its architecture, specifications, and instructions.
CHAPTER 4 "BUS INTERFACE"
This chapter describes the bus interface and bus operation.
CHAPTER 5 "I/O PORTS"
This chapter describes the I/O ports and provides the block diagrams of individual ports. It
also describes the structure and functions of registers.
CHAPTER 6 "8/16-BIT UP/DOWN COUNTER/TIMER"
This chapter describes the 8-bit and 16-bit up/down counter/timer and provides their block
diagrams. It also describes the structures and functions of registers and the operations of the
8-bit and 16-bit up/down counter/timer.
CHAPTER 7 "16-BIT RELOAD TIMER"
This chapter describes the 16-bit reload timer. It also describes the operations of the 16-bit
reload timer, block diagram, and the structures and functions of the timer registers.
CHAPTER 8 "PPG TIMER"
This chapter describes the PPG timer. It also describes the operations of the PPG timer,
block diagram, and the structures and functions of the timer registers.
CHAPTER 9 "MULTIFUNCTIONAL TIMER"
This chapter describes the multifunctional timer. It also describes the operations of the
multifunctional timer, block diagram, and the structures and functions of the timer registers.
CHAPTER 10 "EXTERNAL INTERRUPT CONTROL BLOCK"
This chapter describes the external interrupt control block. It also describes the operation of
the external interrupt control block, and the structures and functions of the related registers.
CHAPTER 11 "DELAYED INTERRUPT MODULE"
This chapter describes the delayed interrupt module. It also describes the operation of the
delayed interrupt module, and the structures and functions of related registers.
CHAPTER 12 "INTERRUPT CONTROLLER"
This chapter describes the interrupt controller and provides its block diagram. It also
describes the structures and functions of registers and the operation of the interrupt
controller.
CHAPTER 13 "8/10-BIT A/D CONVERTER"
This chapter describes the 8-bit D/A converter and provides its block diagram. It also
describes pins, structures and functions of registers, interrupts, device operation, and the A/
D conversion data protection function. The chapter also provides notes on using the 8/10-bit
A/D converter.

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CHAPTER 14 "8-BIT D/A CONVERTER"
This chapter describes the 8-bit D/A converter. It also describes the operation of the
converter, block diagram, and the structures and functions of the converter registers.
CHAPTER 15 "UART"
This chapter describes the UART and provides its block diagram. It also describes pins,
structures and functions of registers, interrupts, timing, baud rates, and device operation.
The chapter also provides notes on using the UART.
CHAPTER 16 "I2C INTERFACE"
This chapter describes the I2C interface and provides its block diagram. It also describes
register structures and functions and I2C interface operation.
CHAPTER 17 "DMAC"
This chapter describes the DMAC and provides its block diagram. It also describes registers,
operation, DMA transfer sources, and DMAC timing. The chapter also provides notes on
using the DMAC.
CHAPTER 18 "BIT SEARCH MODULE"
This chapter describes the bit search module. It also describes the structures and functions
of bit search module registers, and the processing for saving and restoring.
CHAPTER 19 "PERIPHERAL STOP CONTROL"
This chapter describes peripheral stop control and structures and functions of the registers.
CHAPTER 20 "CALENDAR MACROS"
This chapter describes the calendar macros, structures and functions of registers, and the
operation of the calendar macro.
CHAPTER 21 "FLASH MEMORY"
This chapter describes the flash memory, structures and functions of the registers, device
operation, and the automation algorithm. It also provides detailed information on flash
memory writing and erasing.
APPENDIX
The appendix contains I/O maps and information on the interrupt vectors, pin status for
various CPU states, details regarding the little-endian area, and references for programming.

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©2003 FUJITSU LIMITED Printed in Japan
• The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales representatives before ordering.
• The information, such as descriptions of function and application circuit examples, in this document are presented
solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device;
Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you
develop equipment incorporating the device based on such information, you must assume any responsibility
arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of
the use of the information.
• Any information in this document, including descriptions of function and schematic diagrams, shall not be
construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or
any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party' s intellectual
property right or other right by using such information. Fujitsu assumes no liability for any infringement of the
intellectual property rights or other rights of third parties which would result from the use of information contained
herein.
• The products described in this document are designed, developed and manufactured as contemplated for general
use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but
are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers
that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to
death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control
in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in
connection with above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy,
fire protection, and prevention of over-current levels and other abnormal operating conditions.
• If any products described in this document represent goods or technologies subject to certain restrictions on
export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese
government will be required for export of those products from Japan.

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READING THIS MANUAL
■Details Regarding the Manual Format
An explanation of the most important terms in this manual is given in the table below.
Term Meaning
I-BUS 16-bit bus for internal instructions. The FR Series employs internal Harvard
architecture; there are independent buses for instructions and data. A bus
converter is connected to the I-BUS.
D-BUS Internal 32-bit data bus. An internal resource is connected to the D-BUS.
C-BUS Internal multiplex bus. The C-BUS is connected to both the I-BUS and D-Bus
through a switch. An external interface module is connected to the C-BUS. On
external data buses, data and instructions are multiplexed.
R-BUS Internal 16-bit data bus. The R-Bus is connected to the D-BUS via an adapter.
Various I/O devices, a clock generator, and an interrupt controller are connected
to the R-BUS. The R-BUS has a bandwidth of 16 bits over which addresses and
data are multiplexed; CPU access time of these resources is several cycles.
E-unit Arithmetic execution unit
φSystem clock. It provides the clock signals output to each of the built-in
resources connected to the R-BUS from the clock generator. The maximum
clock speed (cycle) is identical to the original clock oscillation. The clock cycle
can be divided by 1, 1/2, 1/4, and 1/8 (or 1/2, 1/4, 1/8, and 1/16) depending on
the setting of the PCK1 and PCK0 bits of the GCR register in the clock
generator.
θSystem clock. Clock used by the CPU and resources connected to a bus other
than the R-BUS. The maximum clock speed (cycle) is identical to the original
clock oscillation. The clock cycle can be divided by 1, 1/2, 1/4, and 1/8 (or 1/2, 1/
4, 1/8, and 1/16) depending on the setting of the CCK1 and CCK0 bits of the
GCR register in the clock generator.

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