Fujitsu MB89140 Series User manual

F2MC-8L FAMILY
MICROCONTROLLERS
MB89140 SERIES
HARDWARE MANUAL
FUJITSU SEMICONDUCTOR
MICROCONTROLLER MANUAL CM25–10113–1E

F2MC-8L FAMILY
MICROCONTROLLERS
MB89140 SERIES
HARDWARE MANUAL
Edition 1.0 February 1995
1995 FUJITSU DEVICES Inc.
All Rights Reserved.
CircuitdiagramsutilizingFujitsuproductsareincludedasameansofillustratingtypical
semiconductor applications. Complete information sufficient for construction purposes
is not necessarily given.
Theinformationcontainedinthis documenthasbeencarefully checkedandisbelieved
to be reliable. However, Fujitsu assumes no responsibility for inaccuracies.
The information contained in this document does not convey any license under the
copyrights, patent rights or trademarks claimed and owned by Fujitsu.
Fujitsu reserves the right to change products or specifications without notice.
Nopart ofthispublication maybecopied orreproducedin anyformor byanymeans,or
transferred to any third party without prior written consent of Fujitsu.

iii
PREFACE
The terms in this manual are defined as follows:
(1) A clock cycle is one clock cycle of the oscillation frequency.
(2) A system clock cycle is the clock frequency divided by the gear function (see 2.2). One cycle time of the
system clock varies with the settings of the CS1 and CS0 bits of the SYCC register. With some internal
resources, the gear change will cause changes in operating speed. See 3.4 for details.

iv
Table of Contents
1. GENERAL 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 FEATURES 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 PRODUCT SERIES 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 BLOCK DIAGRAM 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 PIN ASSIGNMENT 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 PIN FUNCTION DESCRIPTION 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 HANDLING DEVICES 1-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2. HARDWARE CONFIGURATION 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 CPU 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 MAIN/SUB CLOCK CONTROL BLOCK 2-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 INTERRUPT CONTROLLER 2-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 I/O PORTS 2-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 WATCH PRESCALER 2-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 WATCHDOG TIMER RESET 2-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 TIME-BASE TIMER 2-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 8-BIT PWM TIMER (TIMER 1) 2-43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9 8/16-BIT TIMER (TIMER 2 AND TIMER 3) 2-48. . . . . . . . . . . . . . . . . . . . . . . . . .
2.10 12-BIT MULTIPUL GENERATOR (MPG, TIMER 4) 2-55. . . . . . . . . . . . . . . . . . .
2.11 8-BIT SERIAL I/O 2-70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.12 A/D CONVERTER 2-76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.13 BUZZER OUTPUT CIRCUIT 2-83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.14 EXTERNAL INTERRUPT CIRCUIT 2-85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3. OPERATION 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 CLOCK PULSE GENERATOR 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 RESET 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 Reset Operation 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 Reset Sources 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 INTERRUPT 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 LOW-POWER CONSUMPTION MODES 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 PIN STATES FOR SLEEP, STOP AND RESET 3-9. . . . . . . . . . . . . . . . . . . . . . .
4. INSTRUCTIONS 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 TRANSFER INSTRUCTIONS 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 OPERATION INSTRUCTIONS 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 BRANCH INSTRUCTIONS 4-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 OTHER INSTRUCTIONS 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 F2MC-8L FAMILY INSTRUCTION MAP 4-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5. MASK OPTIONS 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APPENDIX App. 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APPENDIX A I/O MAP App.- 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APPENDIX B EPROM SETTING FOR MB89P147 App.- 5. . . . . . . . . . . . . . . . . . . . .
APPENDIX C LIST OF SYSTEM CLOCK CYCLE TIMES WHEN GEAR
CHANGED (SOURCE CLOCK: 8 MHz, 4 MHz) App.- 7. . . . . . . . . .

v
Tables
Table 1-1 Types and Functions of MB89140 Series of Microcontrollers 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 1-1 Types and Functions of MB89140 Series of Microcontrollers (Continued) 1-6. . . . . . . . . . . . . . . .
Table 1-2 Pin Function Description 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 1-3 Pin for External-ROM 1-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-1 Table of Reset and Interrupt Vectors 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-2 Operating State of Low-power Consumption Modes 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-3 Sources of Reset 2-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-4 List of Port Functions 2-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-5 Port register 2-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-6 Relationship between value Set at OUTCR and Duty 2-65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2-7 Buzzer Output Frequencies
(at 8.0 MHz of oscillation frequency) 2-84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-1 Interrupt Sources and Interrupt Vectors 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-2 Low-power Consumption Mode at Each Clock Mode 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-3 Pin State of MB89140 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-1 Mask Options 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-2 Model Specifications 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi
Figures
Fig. 1.1 MB89140 series 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 1.2 Block Diagram 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 1.3 Pin Assignment (DIP-64P-M01, MDP-64C-P02) 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 1.4 Pin Assignment (FPT-64P-M06, MDP-64C-P01) 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 1.5 Input/Output Circuit Configurations 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.1 Memory Space of MB89140 Series of Microcontrollers 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.2 Arrangement of 16-bit Data in Memory 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.3 Arrangement of 16-bit Data during Execution of Instruction 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.4 Structure of Processor Status 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.5 Rule for Translating Real Addresses at General-purpose Register Area 2-7. . . . . . . . . . . . . . . . .
Fig. 2.6 Register Bank Configuration 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.7 Memory Map in Various Modes 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.8 Machine Clock Control Block Diagram 2-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.9 Interrupt Controller Block Diagram 2-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.10 Interrupt-processing Flowchart 2-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.11 Ports 00 to 07 and 10 to 13 2-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.12 Ports 14 to 16 2-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.13 Ports 20 to 23 2-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.14 Ports 70 and 71 2-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.15 Ports 35 to 32, 30 and 17 2-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.16 Port 31 2-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.17 Ports 40 to 47, 50 to 57 and 60 to 67 2-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.18 BZ 2-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.19 Watch Prescaler Block Diagram 2-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.20 Watchdog Timer Reset Block Diagram 2-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.21 Time-base Timer Block Diagram 2-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.22 8-bit PWM Timer (Timer 1) Block Diagram 2-43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.23 Timer Operation 2-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.24 PWM Pulse Output 2-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.25 8/16-bit Timer Block Diagram 2-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.26 Description Diagram for Internal Clock Mode Operation 2-52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.27 Flow Diagram for Timer Setting 2-52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.28 External Cock Mode Operation Description Diagram 2-53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.29 Operation Diagram when Timer Stop Bit is Used 2-53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.30 MPG Block Diagram 2-56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.31 Transition of DTTI Input 2-59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.32 Outline of PWM Output 2-63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.33 Description of PWM Output Operation 2-63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.34 Flowchart of PWM Operation 2-64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.35 Outline of MPG Output 2-67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.36 Description of PPG Output Operation 2-67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.37 Flowchart of PPG Operation 2-68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.38 8-bit Serial I/O Block Diagram 2-70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.39 Shift Start/Stop Timing 2-74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.40 Input/Output Shift Timing 2-75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.41 A/D Comverter Block Diagram 2-76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.42 Buzzer Output Circuit Block Diagram 2-83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 2.43 External Interrupt Circuit Block Diagram 2-85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 3.1 Clock Pulse Generator 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 3.2 Outline of Reset Operation 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 3.3 Reset Vector Structure 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fig. 3.4 Interrupt-processing Flowchart 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1. GENERAL
1.1 FEATURES 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 PRODUCT SERIES 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 BLOCK DIAGRAM 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 PIN ASSIGNMENT 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 PIN FUNCTION DESCRIPTION 1-10. . . . . . . . . . . . . . . . .
1.6 HANDLING DEVICES 1-16. . . . . . . . . . . . . . . . . . . . . . . . .

GENERAL
1-3
TheMB89140seriesofsingle-chipmicrocontrollersusetheF2MC-8LCPUcoretoenablehigh-speedproces-
sing at low voltages, and features a 25 segment VFD (Vacuum Fluorescent Display) driver. They contain re-
sources such as timers, a serial interface, an A/D converter and an external interrupt input to provide a wide
variety of applications for commercial and industrial equipment, including portable equipment.
The MB89140 series of single-chip microcontrollers has twenty-five VCC-40VP-channel high voltage ports
whichmakesitsuitableforVFDdisplayapplicationsuchasmicrowaveoven,fanheater,roomairconditioner,
dashboard controller, and so on.
1.1 FEATURES
•Minimum instruction execution time: 0.5 µs (at oscillation frequency of 8 MHz)
•CPU core as commonly used for MB89860 series
–Instruction system best for controller
Multiplication and division instructions
16-bit operation
Instruction test and branch instruction
Bit handling instruction, etc.
•Operation at low voltage (A/D converter unused)
•25 segment VFD (Vacuum Fluorescent Display) driver.
•Low current dissipation (applicable to dual-circuit clock)
•Internal high-withstand-voltage ports
•5 timers
–8-bit PWM timer (available as reload timer)
–12-bit MPG timer (available as PPG output, PWM output and reload timer)
–8/16-bit timer/counter (available as two 8-bit timers)
–21-bit time-base counter
•Single serial interface
–Transfer direction selected for communication with various equipment
•A/D converter
–Successive approximation type with 10-bit resolution
•2-channel external interrupt input
–Two channels can be selected independently to cancel the low-power consumption modes (selectable
from rising edge, falling edge, or both edges).
–The INT1 can be applied from –0.7 V to 7.0 V (N-channel open drain).
•Low-power consumption modes
–Stop mode (The oscillation stops to minimize current consumption.)
–Sleep mode (The CPU stops to cut current consumption to about 30% of normal.)
•Reset output or power-on reset available option can be selected.
•Packages
–SDIP-64 and QFP-64 packages

GENERAL
1-4
MB89144
ROM 12K
RAM 256
(Planned) MB89147
ROM 32K
RAM 1K
(Under development)
MB89145
ROM 16K
RAM 512
(Under development)
MB89146
ROM 24K
RAM 768
(Planned)
Small Large
Memory capacity
Fig. 1.1 MB89140 series

GENERAL
1-5
1.2 PRODUCT SERIES
Table 1-1 lists the types and functions of the MB89140 series of microcontrollers.
Table 1-1 Types and Functions of MB89140 Series of Microcontrollers
Classification
ROM capacity 12K ×8 bit 16K ×8 bit 24K ×8 bit 32K ×8 bit
RAM capacity 256 ×8 bit 512 ×8 bit 768 ×8 bit 1K ×8 bit
Number of basic instructions 136
Instruction bit length 8 bits
Instruction length 1 to 3 bytes
CPU functions Data bit length 1, 8, 16 bits
Minimum instruction execution time 0.5 µs/8 MHz to 8.0 µs/8 MHz and 61 µs/32.768 kHz
Interrupt processing time 4.5 µs/8 MHz to 72.0 µs/8 MHz and 562.5 µs/32.768 kHz
Note: The above times vary with gear function.
High-withstand-voltage output port 8 (P60 to P67 for large current)
(P-channel open drain) 16 (P40 to P47, P50 to P57 for small current)
Buzzer output 1 (Large current)
(P-channel open drain, high-withstand-voltage)
Output port (CMOS) 4 (P20 to P23)
Port Input port (CMOS) 2 (P70 to P71; serve as X0A and X1A pins when two
clocks used)
I/O port (CMOS) 23 (P00 to P07, P10 to P17, P30, P32 to P37)
I/O port (N-channel open drain) 1 (P31)
Total 55
VFD 25 segment
Capable of generating four internal pulses of 0.26 ms, 0.51 ms, 1.02 ms and 0.524 s
(at oscillation frequency of 8.0 MHz)
8-bit timer operation (toggle output possible, 1, 2, 8 or 16 system clock cycles of operating clock)
8-bit resolution PWM operation (conversion cycle: 128 µs to 2.0 ms at oscillation frequency of 8.0 MHz
and maximum gear speed)
12-bit resolution PWM operation (maximum conversion cycle: 2048.4 µs to 16.4 ms
12-bit MPB timer 12-bit resolution reload timer operation (toggle output possible)
(Timer 4) 12-bit resolution PPG operation (minimum resolution: 0.5 µs at oscillation frequency of 8.0 MHz and
maximum gear speed)
8/16-bit timer/counter 8/16-bit timer operation (operating clock, internal clock and external trigger). See 2.2 for details.
(Timers 2 and 3) 8/16-bit event counter operation (selectable from rising edge, falling edge, or both edges)
Time-base timer
8-bit PWM timer
(Timer 1)
Model Name MB89144 MB89145 MB89146 MB89147 MB89P147
MB89W147 MB89PV140
Internal
32K ×8 bits
Internal
1K ×8 bits
External 32K ×8
bits (Piggyback)
Internal
1024 ×8 bits
Mass-produced product
(Mask ROM product) OTPROM/ EPROM product Piggyback/evaluation
product for evaluation
and development

GENERAL
1-6
Table 1-1 Types and Functions of MB89140 Series of Microcontrollers (Continued)
8-bit length 1 channel
Transfer clock (external, 4, 8 or 16 system clock cycles)
10-bit resolution, 12 channels
A/D conversion mode (conversion time: 16.5 µs at 8 MHz and maximum gear speed)
Sense mode (conversion time: 9.0 µs at 8 MHz and maximum gear speed)
Continuous start by external activation or internal timer
2 independent channels (edge selection, interrupt vector, interrupt source flag)
External interrupt Interrupt mode selectable from rising edge, falling edge, or both edge. Analog noise filter built in
For releasing Stop/Sleep modes (edge detection possible in Stop mode)
Standby mode Sleep, Stop and Watch mode
Process CMOS
Package DIP-64P-M01 (SDIP-64)/FPT-64P-M06 (QFP64)
Operating voltage 2.7 V to 6.0 V* 2.7 V to 6.0 V
Model Name MB89144 MB89145 MB89146 MB89147 MB89P147
MB89W147 MB89PV140
Serial I/O
A/D converter
MDP-64C-P02/
MQP-64C-P01
* Operating voltage varies depending to the condition such as frequency or others.

GENERAL
1-7
1.3 BLOCK DIAGRAM
Internal bus
4
4
8
BZ
P60 to P67
P50 to P57
P40 to P47
VFD
P32/SCK
P33/SO
P34/SI
P30/TRG/INT0
P37/DTTI
P3/PWO1
P35/EC
P31/INT1
X0
X1
P70, P71
X0A
X1A
P23/WDG
P22
P21/PWO0
P20
MODA
AVCC
AVSS
P17/ADST
P14 to P16
P13/ANB to
P10/AN8
P07/AN7 to
P00/AN0
Main clock oscillator
(Max. 8 MHz)
Clock control
Sub clock oscillator
(32.768 kHz)
Port
7
CMOS input port
Port
2
CMOS output port
8-bit PWM timer
Mode control
10-bit A/D converter
Port
0/1
CMOS output port
Time-base timer
Buzzer
High-withstand-voltage
port 6
High-withstand-voltage
port 5
High-withstand-voltage
port 4
8-bit serial
12-bit MPG
Port
3
8/16-bit timer/counter
External interrupt
input
CMOS I/O port
Other pins
RAM
(Max. 512 ×8 bit )
F2MC-8L
CPU
ROM
(Max. 16 K ×8 bit) VCC, VSS
Fig. 1.2 Block Diagram

GENERAL
1-8
1.4 PIN ASSIGNMENT
BZ ←
P67 ←
P66 ←
P65 ←
P64 ←
P63 ←
P62 ←
P61 ←
P60 ←
VFD →
P57 ←
P56 ←
P55 ←
P54 ←
P53 ←
P52 ←
P51 ←
P50 ←
P47 ←
P46 ←
P45 ←
P44 ←
P43 ←
P42 ←
P41 ←
P40 ←
P23/WDG ←
RST ↔
MODA →
X0 →
X1 ←
VSS ←
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
←VCC
←AVCC
←AVSS
↔P00/AN0
↔P01/AN1
↔P02/AN2
↔P03/AN3
↔P04/AN4
↔P05/AN5
↔P06/AN6
↔P07/AN7
↔P10/AN8
↔P11/AN9
↔P12/ANA
↔P13/ANB
↔P14
↔P15
↔P16
↔P17/ADST
↔P30/INT0/TRG
↔P31/INT1
↔P32/SCK
↔P33/SO
↔P34/SI
↔P35/EC
↔P36/PWO1
↔P37/DTTI
→P20
→P21/PWO0
→P22
←P70/X0A
↔P71/X1A
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
65
66
67
68
69
70
71
72
73
74
75
76
77
78
A15/VAA
A12
A7
A6
A5
A4
A3
A2
A1
A0
O1
O2
O3
VSS
92
91
90
89
88
87
86
85
84
83
82
81
80
79
VCC
A14
A13
A8
A9
A11
OE
A10
CE
O8
O7
O6
O5
O4
TOP VIEW
Items in dotted lines
are only available for
the MB89PV140.
The SH-DIP64 cautions are as follows:
•Pins 33 and 34 serve as input-only ports when used as general-purpose ports.
•Pin 28 serves as an output pin when the reset output option is selected.
•P07toP00andP13toP10serveasanaloginputportsafterreset. Whenusingthemasportinputs,registers
PCR0 and PCR1 must be set.
Fig. 1.3 Pin Assignment (DIP-64P-M01, MDP-64C-P02)

GENERAL
1-9
P61
P60
VFD
P57
P56
P55
P54
P53
P52
P51
P50
P47
P46
P45
P44
P43
P42
P41
P40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
P03/AN3
P04/AN4
P05/AN5
P06/AN6
P07/AN7
P10/AN8
P11/AN9
P12/ANA
P13/ANB
P14
P15
P16
P17/ADST
P30/INT0/TRG
P31/INT1
P32/SCK
P33/SO
P34/SI
P35/EC
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
85
86
87
88
89
90
91
92
93
77
76
75
74
73
72
71
70
69
TOP VIEW
Items in dotted lines are only
available for the MB89PV140.
20 21 22 23 24 25 26 27 28 29 30 31 32
P01
P63 P65 P67 VCC AVSS /AN1
P00/ P02/
P62 P64 P66 BZ AVCC AN0 AN2
P23 MODA X1 P71/ P22 P20 P36/
/WDG X1A PWO1
RST X0 VSS P70/ P21/ P37/
X0A PWO0 DTTI
84 83 82 81 80 79 78
94 95 96 65 66 67 68
64 63 62 61 60 59 58 57 56 55 54 53 52
65 N.C. 73 A2 81 N.C. 89 OE
66 A15/VPP 74 A1 82 O4 90 N.C.
67 A12 75 A0 83 O5 91 A11
68 A7 76 N.C. 84 O6 92 A9
69 A6 77 O1 85 O7 93 A8
70 A5 78 O2 86 O8 94 A13
71 A4 79 O3 87 CE 95 A14
72 A3 80 VSS 88 A10 96 VCC
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
Fig. 1.4 Pin Assignment (FPT-64P-M06, MDP-64C-P01)

GENERAL
1-10
1.5 PIN FUNCTION DESCRIPTION
Table 1-2 and NO TAG lists the pin function and Figure 1.3 shows the input/output circuit configurations.
Table 1-2 Pin Function Description
Function
Pin No. Pin Name Circuit
type
30 23 X0 Used for main clock oscillation
A A crystal resonator should be used.
31 24 X1
Used for input of operation mode select signals
29 22 MODA B Usually connected to VSS. This pin serves as the VPP pin for EPROM-
mounted models.
Used for input/output of reset signals
Consists of an N-channel open-drain output with a pull-up resistor and
28 21 RST C hysteresis input. When the reset on option is selected, a Low level is output
from this pin according to the internal source. The internal circuit is initial-
ized at input of a Low level. A noise canceler is built in.
General-purpose I/O ports
Input is hysteresis type containing a noise filter. Although these ports also
serves as analog input pins, analog input does not pass through the noise
filter for hysteresis input.
General-purpose I/O port
46 39 P17/ADST I Input is hysteresis type containing a noise filter. This port also serves as an
external start pin for the A/D converter.
General-purpose I/O ports
Input is hysteresis type containing a noise filter.
General-purpose I/O ports
Input is hysteresis type containing a noise filter. Although these ports serve
as analog input pins, analog input does not pass through the noise filter for
hysteresis input.
Can be selected as a general-purpose input port or sub-clock generating
34 27 X0A/P70 A/J pin by the mask option. When using as a general-purpose input pin, input
is hysteresis type containing a noise filter.
Can be selected as a general-purpose input port or sub-clock generating
33 26 X1A/P71 A/J pin by the mask option. When using as a general-purpose input pin, input
is hysteresis type containing a noise filter.
35 28 P22 D General-purpose output port
General-purpose output port
This port also serves as a watchdog output pin (see 2.2 for watch dog timer).
General-purpose output port
This port also serves as a PWM output pin for the 8-bit PWM timer.
37 30 P20 D General-purpose output port
SDIP
P07/AN7
54 to 61 47 to 54 to F
P00/AN0
47 to 49 40 to 42 P16 to P14 I
P13/ANB
50 to 53 43 to 46 to F
P10/AN8
27 20 P23/WDG D
36 29 P21/PWO0 D
QFP

GENERAL
1-11
Table 1-2 Pin Function Description (Continued)
Function
Pin No. Pin Name Circuit
type
General-purpose I/O port
Input is hysteresis type containing a noise filter. When overcurrent is
detected, the external rising or falling edge can be input to inactivate the
12-bit MPG output.
General-purpose I/O port
39 32 P36/PWO1 I Input is hysteresis type containing a noise filter. This port also serves as a
12-bit MPG output pin.
General-purpose I/O port
40 33 P35/EC I Input is hysteresis type containing a noise filter. This port also serves as an
external clock input pin for the 8/16-bit timer/counter.
General-purpose I/O port
41 34 P34/SI I Input is hysteresis type containing a noise filter. This port also serves as an
external clock input pin for the 8-bit timer/counter.
General-purpose I/O port
42 35 P33/SO I Input is hysteresis type containing a noise filter. This port also serves as a
serial data output pin for the 8-bit serial interface.
General-purpose I/O port
43 36 P32/SCK I Input is hysteresis type containing a noise filter. This port also serves as a
serial transfer clock pin for the 8-bit serial interface.
General-purpose I/O port
Consists of an N-channel open-drain output and hysteresis input containing
a noise filter. This port also serves as an external interrupt pin. Interrupt
input is also hysteresis type containing a noise filter.
General-purpose I/O port
Input is hysteresis type containing a noise filter. This port can also be used
as an external interrupt pin or MPG trigger input pin. Interrupt input is also
hysteresis type containing a noise filter.
Used for buzzer output only
1 58 BZ H This pin also serves as a P-channel high-withstand-voltage open-drain
output port.
P-channel high-withstand-voltage open drain output ports for small current
19 to 26 12 to 19 P47 to P40 G Two types of microcontrollers are provided: one has a pull-down resistor
between these ports and the VFD pin, and the other does not.
P-channel high-withstanding-voltage open drain output ports for small current
11 to 18 4 to 11 P57 to P50 G Two types of microcontrollers are provided: one has a pull-down resistor
between these ports and the VFD pin, and the other does not.
P-channel high-withstand-voltage open-drain output ports for large current
2 to 9 59 to 2 P67 to P60 G Two types of microcontrollers are provided: one has a pull-down resistor
between these ports and the VFD pin, and the other does not.
Used for voltage supply connected to pull-down resistors for ports 4, 5 and 6
10 3 VFD — This pin serves as an NC pin for microcontrollers without a pull-down resistor
and the MB89PV140 microcontroller.
SDIP
38 31 P37/DTTI I
44 37 P31/INT1 E
45 38 P30/INT0/TRG I
QFP

GENERAL
1-12
Table 1-2 Pin Function Description (Continued)
Function
Pin No. Pin Name Circuit
type
64 57 VCC —Used for power supply
32 25 VSS —Used for power supply (GND)
63 56 AVCC —Used for power supply for A/D converter
Used for power supply for A/D converter
Must be used at same potential as VSS pin
SDIP
62 55 AVSS —
SDIP

GENERAL
1-13
Table 1-3 Pin for External-ROM
Function
Pin No. Pin Name Circuit
type
65 66 VPP Output High-level output pin
66 67 A12
67 68 A7
68 69 A6
69 70 A5
70 71 A4 Output Address-output pins
71 72 A3
72 73 A2
73 74 A1
74 75 A0
75 77 01
76 78 02 Input Data-input pins
77 79 03
78 80 VSS Output Power (GND) pin
79 82 04
80 83 05
81 84 06 Input Data-input pins
82 85 07
83 86 08
84 87 CE Output Chip-enable pin for ROM
A High level is output in the standby mode.
85 88 A10 Output Address-output pin
86 89 OE Output Output-enable pin for ROM
A Low level is always output.
87 91 A11
88 92 A9 Output Address-output pins
89 93 A8
90 94 A13 Output Address-output pin
91 95 A14 Output Address-output pin
92 96 VCC Output Power pin for EPROM
SDIP QFP

GENERAL
1-14
Classification Circuit Remarks
•Feedback resistor: About 2 MΩ
•CMOS input
•Output pull-up resistor (Pch): About 50 kΩ(5 V)
•CMOS hysteresis input (with noise filter)
•CMOS output
•N-ch open drain output
•CMOS hysteresis input (with noise filter)
•CMOS output
•CMOS hysteresis input (with noise filter; analog
input excluded)
X1
X0
Standby control signal
A
B
C
D
E
F
Pch
R
Nch
Pch
Nch
Nch
Pch
Nch
Hysteresis input (with noise filter)
Hysteresis input (with noise filter)
Analog input
Port
Hysteresis input (with noise filter)
Fig. 1.5 Input/Output Circuit Configurations

GENERAL
1-15
Classification Circuit Remarks
•P-channel high-withstand-voltage open-drain
output
•Microcontrollers with and without pull-down resis
tor provided (excluding MB89V140
microcontroller)
•CMOS output
•CMOS hysteresis input (with noise filter)
•The pull-up resistor is optional.
•CMOS hysteresis input (with noise filter)
G
H
I
J
Pch
Nch
Hysteresis input (with noise filter)
Port
Pch
R
Pch •P-channel high-withstand-voltage open-drain
output
VFD
Port
Hysteresis input (with noise filter)
Fig. 1.5 Input/Output Circuit Configurations (Continued)