Fujitsu MB90335 Series User manual

The following document contains information on Cypress products.

FUJITSU MICROELECTRONICS
CONTROLLER MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
MB90335 Series
HARDWARE MANUAL
CM44-10137-6E

FUJITSU MICROELECTRONICS LIMITED
F2MC-16LX
16-BIT MICROCONTROLLER
MB90335 Series
HARDWARE MANUAL
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development. http://edevice.fujitsu.com/micom/en-support/

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Preface
■Purpose of This Document and Intended Reader
We sincerely thank you for your continued use of Fujitsu microelectronics products.
MB90335 series is a 16-bit microcontroller designed for applications such as personal computer
peripheral device requiring USB communication. The USB function is not only function operation of
12 M bps but also simple HOST operation.
MB90335 series has functions which are suitable for controlling personal computer peripheral devices
such as display and audio and mobile devices supporting the USB communication.
This manual describes the functions and operations of the MB90335 Series for engineers who develop
products using the MB90335 Series. Please read through this manual.
For more information on various instructions, refer to "Instruction Manual".
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■Trademarks
The company names and brand names herein are the trademarks or registered trademarks of their
respective owners.
■Organization of This Document
This manual contains the following 23 chapters and appendix.
Chapter 1 OVERVIEW
This chapter describes basics to give the understanding of the MB90335 Series as a whole such as the
features, block diagrams, and overviews of the functions.
Chapter 2 CPU
This chapter explains the setting and operation of the CPU.
Chapter 3 INTERRUPTS
This chapter describes the overview of interruptions, interrupt vector and interrupt cause, register
configuration/function, and interrupt processing operations.
Chapter 4 RESET
This chapter describes the overview of reset, reset cause and oscillation stabilization wait time, and
reset operation.
Chapter 5 CLOCK
This chapter describes the overview of the clock, register configuration/function, clock mode, and
oscillation stability wait time.
Chapter 6 LOW-POWER CONSUMPTION MODE
This chapter describes the overview of the low-power consumption mode, register configuration/
function, and operation of the low-power consumption mode.
Chapter 7 MODE SETTING
This chapter describes the overview of mode settings, mode pin, mode data, and operation in each
mode of mode setting.

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Chapter 8 I/O PORT
This chapter describes the overview of the I/O port and the register configuration/function used in the
I/O port.
Chapter 9 TIME-BASE TIMER
This chapter describes the overview of the time-base time, register configuration/function, interrupt,
and operation of the time-base timer.
Chapter 10 WATCHDOG TIMER
This chapter describes the overview of the watchdog timer, register configuration/function, and
operation of the watchdog timer.
Chapter 11 USB FUNCTION
This chapter describes the functions and overview of the USB Function.
Chapter 12 USB HOST
This chapter describes the functions and operation of USB HOST.
Chapter 13 PWC TIMER
This chapter describes an overview of PWC timer, the configuration and function of register, and the
PWC timer operation and precaution.
Chapter 14 16-BIT RELOAD TIMER
This chapter describes an overview of 16-bit reload timer, the configuration and functions of register
and the 16-bit reload timer operation.
Chapter 15 8/16-BIT PPG TIMER
This chapter describes an overview of 8/16-bit PPG timer, the configuration and functions of register,
and the 8/16-bit PPG timer operation.
Chapter 16 DTP/EXTERNAL INTERRUPT
This chapter describes an overview of DTP/external interrupt, the configuration and functions of
register, and the DTP/external interrupt operation.
Chapter 17 EXTENDED I/O SERIAL INTERFACE
This chapter describes an overview of the extended I/O serial interface, the configuration and function
of registers, and operations of extended I/O serial interface.
Chapter 18 UART
This chapter describes the overview of the UART, the configuration/functions of the register, the
operation of the UART, the usage note of the UART, and the example of UART program.
Chapter 19 I2C INTERFACE
This chapter gives an overview of I2C interface, the configuration and functions of registers, and
operations of I2C interface.
Chapter 20 ROM MIRROR FUNCTION SELECTION MODULE
This chapter describes the functions of the ROM mirror function selection module and the
configuration/function of the register.
Chapter 21 ADDRESS MATCH DETECTION FUNCTION
This chapter explains the address match detection function and its operation.

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Chapter 22 DUAL OPERATION FLASH MEMORY
This chapter describes the function and operation of the dual operation flash memory.
Chapter 23 EXAMPLE of CONNECTING SERIAL WRITING
This chapter describes examples of serial write connection when using AF220/AF210/AF120/AF110
flash microcontroller programmer made by Yokogawa Digital Computer Corporation.
APPENDIX
Appendix includes detailed information on I/O map, interrupt vector, and instruction list, which are
not mentioned in this manual and information that is needed for programming.

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Copyright ©2005-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved.
• The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
• The information, such as descriptions of function and application circuit examples, in this document are presented solely for
the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU
MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of
such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out
of the use of the information.
• Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU
MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-
party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no
liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use
of information contained herein.
• The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is
secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or
other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e.,
submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
• Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
• The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

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CONTENTS
CHAPTER 1 OVERVIEW ................................................................................................... 1
1.1 Feature of MB90335 Series ................................................................................................................ 2
1.2 Block Diagram .................................................................................................................................... 7
1.3 Package Dimension ............................................................................................................................ 8
1.4 Pin Assignment ................................................................................................................................... 9
1.5 Pin Function ...................................................................................................................................... 10
1.6 I/O Circuit Types ............................................................................................................................... 13
1.7 Handling of Device ............................................................................................................................ 16
CHAPTER 2 CPU ............................................................................................................ 19
2.1 Overview of the CPU ........................................................................................................................ 20
2.2 Memory Space .................................................................................................................................. 21
2.3 Linear Addressing ............................................................................................................................. 24
2.4 Bank Addressing ............................................................................................................................... 25
2.5 Multibyte Data in Memory Space ...................................................................................................... 27
2.6 Registers ........................................................................................................................................... 28
2.6.1 Accumulator (A) ........................................................................................................................... 31
2.6.2 User Stack Pointer (USP) and System Stack Pointer (SSP) ....................................................... 32
2.6.3 Processor Status (PS) ................................................................................................................. 33
2.6.4 Program Counter (PC) ................................................................................................................. 36
2.6.5 Bank Registers (PCB, DTB, USB, SSB, ADB) ............................................................................ 37
2.6.6 Direct Page Register (DPR) ........................................................................................................ 38
2.7 Register Bank ................................................................................................................................... 39
2.8 Prefix Codes ..................................................................................................................................... 40
2.9 Interrupt Disable Instructions ............................................................................................................ 43
CHAPTER 3 INTERRUPT ............................................................................................... 45
3.1 Outline of Interrupt ............................................................................................................................ 46
3.2 Interrupt Cause and Interrupt Vector ................................................................................................ 49
3.3 Interrupt Control Register and Peripheral Function .......................................................................... 52
3.3.1 Interrupt Control Registers (ICR00 to ICR15) .............................................................................. 54
3.3.2 Interrupt Control Register Functions ............................................................................................ 56
3.4 Hardware Interrupt ............................................................................................................................ 59
3.4.1 Operation of Hardware Interrupt .................................................................................................. 62
3.4.2 Operation Flow of Hardware Interrupt ......................................................................................... 64
3.4.3 Procedure for Using a Hardware Interrupt ................................................................................... 65
3.4.4 Multiple Interrupts ........................................................................................................................ 66
3.4.5 Hardware Interrupt Processing Time ........................................................................................... 68
3.5 Software Interrupt ............................................................................................................................. 70
3.6 Interrupts by Extended Intelligent I/O Service (EI2OS) ..................................................................... 72
3.6.1 Extended Intelligent I/O Service (EI2OS) Descriptor (ISD) .......................................................... 74
3.6.2 Each Register of Extended Intelligent I/O Service (EI2OS) Descriptor (ISD) .............................. 76
3.6.3 Operation of Extended Intelligent I/O Service (EI2OS) ................................................................ 79