Fujitsu MB90335 Series User manual

The following document contains information on Cypress products.

FUJITSU MICROELECTRONICS
CONTROLLER MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
MB90335 Series
HARDWARE MANUAL
CM44-10137-6E

FUJITSU MICROELECTRONICS LIMITED
F2MC-16LX
16-BIT MICROCONTROLLER
MB90335 Series
HARDWARE MANUAL
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development. http://edevice.fujitsu.com/micom/en-support/

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Preface
■Purpose of This Document and Intended Reader
We sincerely thank you for your continued use of Fujitsu microelectronics products.
MB90335 series is a 16-bit microcontroller designed for applications such as personal computer
peripheral device requiring USB communication. The USB function is not only function operation of
12 M bps but also simple HOST operation.
MB90335 series has functions which are suitable for controlling personal computer peripheral devices
such as display and audio and mobile devices supporting the USB communication.
This manual describes the functions and operations of the MB90335 Series for engineers who develop
products using the MB90335 Series. Please read through this manual.
For more information on various instructions, refer to "Instruction Manual".
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■Trademarks
The company names and brand names herein are the trademarks or registered trademarks of their
respective owners.
■Organization of This Document
This manual contains the following 23 chapters and appendix.
Chapter 1 OVERVIEW
This chapter describes basics to give the understanding of the MB90335 Series as a whole such as the
features, block diagrams, and overviews of the functions.
Chapter 2 CPU
This chapter explains the setting and operation of the CPU.
Chapter 3 INTERRUPTS
This chapter describes the overview of interruptions, interrupt vector and interrupt cause, register
configuration/function, and interrupt processing operations.
Chapter 4 RESET
This chapter describes the overview of reset, reset cause and oscillation stabilization wait time, and
reset operation.
Chapter 5 CLOCK
This chapter describes the overview of the clock, register configuration/function, clock mode, and
oscillation stability wait time.
Chapter 6 LOW-POWER CONSUMPTION MODE
This chapter describes the overview of the low-power consumption mode, register configuration/
function, and operation of the low-power consumption mode.
Chapter 7 MODE SETTING
This chapter describes the overview of mode settings, mode pin, mode data, and operation in each
mode of mode setting.

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Chapter 8 I/O PORT
This chapter describes the overview of the I/O port and the register configuration/function used in the
I/O port.
Chapter 9 TIME-BASE TIMER
This chapter describes the overview of the time-base time, register configuration/function, interrupt,
and operation of the time-base timer.
Chapter 10 WATCHDOG TIMER
This chapter describes the overview of the watchdog timer, register configuration/function, and
operation of the watchdog timer.
Chapter 11 USB FUNCTION
This chapter describes the functions and overview of the USB Function.
Chapter 12 USB HOST
This chapter describes the functions and operation of USB HOST.
Chapter 13 PWC TIMER
This chapter describes an overview of PWC timer, the configuration and function of register, and the
PWC timer operation and precaution.
Chapter 14 16-BIT RELOAD TIMER
This chapter describes an overview of 16-bit reload timer, the configuration and functions of register
and the 16-bit reload timer operation.
Chapter 15 8/16-BIT PPG TIMER
This chapter describes an overview of 8/16-bit PPG timer, the configuration and functions of register,
and the 8/16-bit PPG timer operation.
Chapter 16 DTP/EXTERNAL INTERRUPT
This chapter describes an overview of DTP/external interrupt, the configuration and functions of
register, and the DTP/external interrupt operation.
Chapter 17 EXTENDED I/O SERIAL INTERFACE
This chapter describes an overview of the extended I/O serial interface, the configuration and function
of registers, and operations of extended I/O serial interface.
Chapter 18 UART
This chapter describes the overview of the UART, the configuration/functions of the register, the
operation of the UART, the usage note of the UART, and the example of UART program.
Chapter 19 I2C INTERFACE
This chapter gives an overview of I2C interface, the configuration and functions of registers, and
operations of I2C interface.
Chapter 20 ROM MIRROR FUNCTION SELECTION MODULE
This chapter describes the functions of the ROM mirror function selection module and the
configuration/function of the register.
Chapter 21 ADDRESS MATCH DETECTION FUNCTION
This chapter explains the address match detection function and its operation.

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Chapter 22 DUAL OPERATION FLASH MEMORY
This chapter describes the function and operation of the dual operation flash memory.
Chapter 23 EXAMPLE of CONNECTING SERIAL WRITING
This chapter describes examples of serial write connection when using AF220/AF210/AF120/AF110
flash microcontroller programmer made by Yokogawa Digital Computer Corporation.
APPENDIX
Appendix includes detailed information on I/O map, interrupt vector, and instruction list, which are
not mentioned in this manual and information that is needed for programming.

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Copyright ©2005-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved.
• The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
• The information, such as descriptions of function and application circuit examples, in this document are presented solely for
the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU
MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of
such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out
of the use of the information.
• Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU
MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-
party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no
liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use
of information contained herein.
• The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is
secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or
other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e.,
submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
• Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
• The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

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CONTENTS
CHAPTER 1 OVERVIEW ................................................................................................... 1
1.1 Feature of MB90335 Series ................................................................................................................ 2
1.2 Block Diagram .................................................................................................................................... 7
1.3 Package Dimension ............................................................................................................................ 8
1.4 Pin Assignment ................................................................................................................................... 9
1.5 Pin Function ...................................................................................................................................... 10
1.6 I/O Circuit Types ............................................................................................................................... 13
1.7 Handling of Device ............................................................................................................................ 16
CHAPTER 2 CPU ............................................................................................................ 19
2.1 Overview of the CPU ........................................................................................................................ 20
2.2 Memory Space .................................................................................................................................. 21
2.3 Linear Addressing ............................................................................................................................. 24
2.4 Bank Addressing ............................................................................................................................... 25
2.5 Multibyte Data in Memory Space ...................................................................................................... 27
2.6 Registers ........................................................................................................................................... 28
2.6.1 Accumulator (A) ........................................................................................................................... 31
2.6.2 User Stack Pointer (USP) and System Stack Pointer (SSP) ....................................................... 32
2.6.3 Processor Status (PS) ................................................................................................................. 33
2.6.4 Program Counter (PC) ................................................................................................................. 36
2.6.5 Bank Registers (PCB, DTB, USB, SSB, ADB) ............................................................................ 37
2.6.6 Direct Page Register (DPR) ........................................................................................................ 38
2.7 Register Bank ................................................................................................................................... 39
2.8 Prefix Codes ..................................................................................................................................... 40
2.9 Interrupt Disable Instructions ............................................................................................................ 43
CHAPTER 3 INTERRUPT ............................................................................................... 45
3.1 Outline of Interrupt ............................................................................................................................ 46
3.2 Interrupt Cause and Interrupt Vector ................................................................................................ 49
3.3 Interrupt Control Register and Peripheral Function .......................................................................... 52
3.3.1 Interrupt Control Registers (ICR00 to ICR15) .............................................................................. 54
3.3.2 Interrupt Control Register Functions ............................................................................................ 56
3.4 Hardware Interrupt ............................................................................................................................ 59
3.4.1 Operation of Hardware Interrupt .................................................................................................. 62
3.4.2 Operation Flow of Hardware Interrupt ......................................................................................... 64
3.4.3 Procedure for Using a Hardware Interrupt ................................................................................... 65
3.4.4 Multiple Interrupts ........................................................................................................................ 66
3.4.5 Hardware Interrupt Processing Time ........................................................................................... 68
3.5 Software Interrupt ............................................................................................................................. 70
3.6 Interrupts by Extended Intelligent I/O Service (EI2OS) ..................................................................... 72
3.6.1 Extended Intelligent I/O Service (EI2OS) Descriptor (ISD) .......................................................... 74
3.6.2 Each Register of Extended Intelligent I/O Service (EI2OS) Descriptor (ISD) .............................. 76
3.6.3 Operation of Extended Intelligent I/O Service (EI2OS) ................................................................ 79

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3.6.4 Procedure for Use of Extended Intelligent I/O Service (EI2OS) .................................................. 80
3.6.5 Extended Intelligent I/O Service (EI2OS) Processing Time ......................................................... 81
3.7 Exception Processing Interrupt ......................................................................................................... 84
3.8 Interruption by μDMAC ..................................................................................................................... 85
3.8.1 μDMAC Function ......................................................................................................................... 86
3.8.2 Register of μDMAC ...................................................................................................................... 87
3.8.3 DMA Descriptor Window Register (DDWR) ................................................................................. 94
3.8.4 Explanation of Operation of μDMAC ......................................................................................... 100
3.9 Exceptions ...................................................................................................................................... 102
3.10 Stack Operation of Interrupt Processing ......................................................................................... 103
3.11 Program Example of Interrupt Processing ...................................................................................... 105
3.12 Delayed Interrupt Generation Module ............................................................................................. 109
3.12.1 Operation of Delayed Interrupt Generation Module ................................................................... 110
CHAPTER 4 RESET ...................................................................................................... 111
4.1 Outline of Reset .............................................................................................................................. 112
4.2 Reset Factors and Oscillation Stabilization Wait Times ................................................................. 114
4.3 External Reset Pin .......................................................................................................................... 116
4.4 Reset Operation .............................................................................................................................. 117
4.5 Reset Factor Bit .............................................................................................................................. 119
4.6 State of Each Pin at Reset .............................................................................................................. 121
CHAPTER 5 CLOCK ..................................................................................................... 123
5.1 Outline of Clock .............................................................................................................................. 124
5.2 Block Diagram of Clock Generation Section ................................................................................... 126
5.3 Clock Select Register (CKSCR) ..................................................................................................... 128
5.4 Clock Mode ..................................................................................................................................... 130
5.5 Oscillation Stabilization Wait Time .................................................................................................. 132
5.6 Connection of Oscillator and External Clock .................................................................................. 133
CHAPTER 6 LOW-POWER CONSUMPTION MODE ................................................... 135
6.1 Outline of Low-Power Consumption Mode ..................................................................................... 136
6.2 Block Diagram of Low-power Consumption Control Circuit ............................................................ 139
6.3 Low-power Consumption Mode Control Register (LPMCR) ........................................................... 141
6.4 CPU Intermittent Operation Mode .................................................................................................. 144
6.5 Standby Mode ................................................................................................................................. 145
6.5.1 Sleep Mode ............................................................................................................................... 146
6.5.2 Time-base Timer Mode ............................................................................................................. 148
6.5.3 Stop Mode ................................................................................................................................. 149
6.6 State Transition Diagram ................................................................................................................ 151
6.7 State of the Pin during Standby Mode, and Reset .......................................................................... 153
6.8 Precautions when Using Low-power Consumption Mode .............................................................. 154
CHAPTER 7 MODE SETTING ....................................................................................... 157
7.1 Mode Setting ................................................................................................................................... 158
7.2 Mode Pins (MD2 to MD0) ............................................................................................................... 159
7.3 Mode Data ...................................................................................................................................... 160

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CHAPTER 8 I/O PORT .................................................................................................. 163
8.1 Functions of I/O Ports ..................................................................................................................... 164
8.2 I/O Port Register ............................................................................................................................. 165
8.2.1 Port Data Register (PDR0 to PDR2, PDR4 to PDR6) ............................................................... 166
8.2.2 Port Direction Register (DDR0 to DDR2, DDR4 to DDR6) ........................................................ 167
8.2.3 Other Registers ......................................................................................................................... 168
CHAPTER 9 TIME-BASE TIMER .................................................................................. 169
9.1 Overview of Time-base Timer ......................................................................................................... 170
9.2 Configuration of Time-base Timer .................................................................................................. 172
9.3 Time-base Timer Control Register (TBTC) ..................................................................................... 174
9.4 Interrupt of Time-base Timer .......................................................................................................... 176
9.5 Operations of Time-base Timer ...................................................................................................... 177
9.6 Precautions when Using Time-base Timer ..................................................................................... 179
9.7 Program Example of Time-base Timer ........................................................................................... 181
CHAPTER 10 WATCHDOG TIMER ................................................................................ 183
10.1 Overview of Watchdog Timer ......................................................................................................... 184
10.2 Watchdog Timer Control Register (WDTC) .................................................................................... 185
10.3 Configuration of Watchdog Timer ................................................................................................... 187
10.4 Operations of Watchdog Timer ....................................................................................................... 188
10.5 Precautions when Using Watchdog Timer ...................................................................................... 190
10.6 Program Examples of Watchdog Timer .......................................................................................... 191
CHAPTER 11 USB FUNCTION ....................................................................................... 193
11.1 Overview of USB Function .............................................................................................................. 194
11.2 Block Diagram of USB Function ..................................................................................................... 195
11.3 Registers of USB Function ............................................................................................................. 196
11.3.1 UDC Control Register (UDCC) .................................................................................................. 199
11.3.2 EP0 Control Register (EP0C) .................................................................................................... 202
11.3.3 EP1 to EP5 Control Register (EP1C to EP5C) .......................................................................... 204
11.3.4 Time Stamp Register (TMSP) ................................................................................................... 208
11.3.5 UDC Status Register (UDCS) .................................................................................................... 209
11.3.6 UDC Interruption Enable Register (UDCIE) .............................................................................. 212
11.3.7 EP0I Status Register (EP0IS) .................................................................................................... 214
11.3.8 EP0O Status Register (EP0OS) ................................................................................................ 216
11.3.9 EP1 to EP5 Status Register (EP1S to EP5S) ............................................................................ 219
11.3.10 EP0 to EP5 Data Register (EP0DT to EP5DT) ......................................................................... 223
11.4 Operation Explanation of USB Function ......................................................................................... 224
11.4.1 Detecting Connection and Disconnection .................................................................................. 227
11.4.2 Each Register Operation when Command Responds ............................................................... 229
11.4.3 STALL Response and Release ................................................................................................. 231
11.4.4 Suspend Function ...................................................................................................................... 235
11.4.5 Wake-up Function ..................................................................................................................... 236
11.4.6 DMA Transfer Function ............................................................................................................. 237
11.4.7 NULL Transfer Function ............................................................................................................ 241

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CHAPTER 12 USB HOST ............................................................................................... 243
12.1 Feature of USB HOST .................................................................................................................... 244
12.2 Restriction on USB HOST .............................................................................................................. 245
12.3 Block Diagram of USB HOST ......................................................................................................... 246
12.4 Register of USB HOST ................................................................................................................... 247
12.4.1 Host Control Register 0,1(HCNT0/HCNT1) ............................................................................... 250
12.4.2 Host Interruption Register (HIRQ) ............................................................................................. 254
12.4.3 Host Error Status Register (HERR) ........................................................................................... 257
12.4.4 Host State Status Register (HSTATE) ....................................................................................... 260
12.4.5 SOF Interruption FRAME Comparison Register (HFCOMP) ..................................................... 263
12.4.6 Retry Timer Setting Register (HRTIMER) ................................................................................. 264
12.4.7 Host Address Register (HADR) ................................................................................................. 265
12.4.8 EOF Setting Register (HEOF) ................................................................................................... 266
12.4.9 FRAME Setting Register (HFRAME) ......................................................................................... 267
12.4.10 Host Token Endpoint Register (HTOKEN) ................................................................................ 268
12.5 Operation of USB HOST ................................................................................................................. 270
12.5.1 Connection of Device ................................................................................................................ 271
12.5.2 Reset of USB Bus ...................................................................................................................... 273
12.5.3 Token Packet ............................................................................................................................. 274
12.5.4 Data Packet ............................................................................................................................... 276
12.5.5 Handshake Packet .................................................................................................................... 277
12.5.6 Retry Function ........................................................................................................................... 278
12.5.7 SOF Interrupt ............................................................................................................................. 279
12.5.8 Error Status ............................................................................................................................... 281
12.5.9 Packet End ................................................................................................................................ 282
12.5.10 Suspend Resume ...................................................................................................................... 283
12.5.11 Cutting of Device ....................................................................................................................... 286
12.6 Each Token Flow Chart of USB HOST ........................................................................................... 287
CHAPTER 13 PWC TIMER ............................................................................................. 289
13.1 Overview of PWC Timer ................................................................................................................. 290
13.2 Register of PWC Timer ................................................................................................................... 292
13.2.1 PWC Control Status Register (PWCSR) ................................................................................... 293
13.2.2 PWC Data Buffer Register (PWCR) .......................................................................................... 298
13.2.3 PWC Ratio of Dividing Frequency Control Register (DIVR) ...................................................... 299
13.3 Movement of PWC Timer ............................................................................................................... 300
13.3.1 Operation of PWM Timer Functions .......................................................................................... 301
13.3.2 Operation of Pulse Width Measurement Function ..................................................................... 302
13.3.3 Count Clock Selection and Operation Mode Selection .............................................................. 303
13.3.4 Startup and Stop of Timer/Pulse Width Measurement .............................................................. 305
13.3.5 Operation of Timer Mode ........................................................................................................... 307
13.3.6 Operation of Pulse Width Measurement Mode .......................................................................... 310
13.4 Precautions when Using PWC Timer ............................................................................................. 315
CHAPTER 14 16-BIT RELOAD TIMER ........................................................................... 317
14.1 Overview of 16-bit Reload Timer .................................................................................................... 318
14.1.1 Function of 16-bit Reload Timer ................................................................................................ 319

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14.1.2 Block Diagram of 16-bit Reload Timer ....................................................................................... 321
14.2 Registers of 16-bit Reload Timer .................................................................................................... 322
14.2.1 Timer Control Status Register 0 (TMCSR0) .............................................................................. 323
14.2.2 16-bit Timer Register 0 (TMR0)/16-bit Reload Register 0 (TMRLR0) ....................................... 327
14.3 Movement of 16-bit Reload Timer .................................................................................................. 329
14.3.1 State Transition of Counter Operation ....................................................................................... 330
14.3.2 Operation of Internal Clock Mode (Reload Mode) ..................................................................... 331
14.3.3 Operation of Internal Clock Mode (Single Shot Mode) .............................................................. 334
14.3.4 Event Count Mode ..................................................................................................................... 337
CHAPTER 15 8/16-BIT PPG TIMER ............................................................................... 339
15.1 Overview of 8/16-bit PPG Timer ..................................................................................................... 340
15.1.1 Block Diagram of 8/16-bit PPG Timer ....................................................................................... 341
15.2 Registers of 8/16-bit PPG Timer ..................................................................................................... 343
15.2.1 PPG0/PPG2 Operation Mode Control Register (PPGC0/PPGC2) ............................................ 344
15.2.2 PPG1/PPG3 Operation Mode Control Register (PPGC1/PPGC3) ............................................ 346
15.2.3 PPG0 to PPG3 Output Control Register (PPG01/PPG23) ........................................................ 349
15.2.4 PPG Reload Registers (PRLL0 to PRLL3, PRLH0 to PRLH3) .................................................. 351
15.3 Operation of 8/16-bit PPG Timer .................................................................................................... 352
CHAPTER 16 DTP/EXTERNAL INTERRUPT ................................................................. 357
16.1 Overview of DTP/External Interrupt ................................................................................................ 358
16.2 Register of DTP/External Interrupt .................................................................................................. 359
16.3 Operation of DTP/External Interrupt ............................................................................................... 362
16.4 Precaution of Using DTP/External Interrupt .................................................................................... 364
CHAPTER 17 EXTENDED I/O SERIAL INTERFACE ..................................................... 367
17.1 Outline of Extended I/O Serial Interface ......................................................................................... 368
17.2 Register in Extended I/O Serial Interface ....................................................................................... 369
17.2.1 Serial Mode Control Status Register (SMCS) ........................................................................... 370
17.2.2 Serial Data Register (SDR) ....................................................................................................... 374
17.2.3 Communication Prescaler Control Register (SDCR) ................................................................. 375
17.3 Operation of Extended I/O Serial Interface ..................................................................................... 377
17.3.1 Shift Clock Mode ....................................................................................................................... 378
17.3.2 Operation State of Serial I/O ..................................................................................................... 379
17.3.3 Start/Stop Timing of Shift Operation and Timing of I/O ............................................................. 381
17.3.4 Interrupt Function ...................................................................................................................... 383
CHAPTER 18 UART ........................................................................................................ 385
18.1 Overview of UART .......................................................................................................................... 386
18.2 Block Diagram of UART .................................................................................................................. 388
18.3 UART Pins ...................................................................................................................................... 391
18.4 Register of UART ............................................................................................................................ 392
18.4.1 Serial Control Register 0, 1 (SCR0, SCR1) ............................................................................... 393
18.4.2 Serial Mode Register 0, 1 (SMR0, SMR1) ................................................................................. 395
18.4.3 Serial Status Register 0, 1 (SSR0, SSR1) ................................................................................. 397

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18.4.4 Serial Input Data Register 0, 1 (SIDR0, SIDR1) and Serial Output Data Register 0, 1
(SODR0, SODR1) ..................................................................................................................... 400
18.4.5 UART Prescaler Control Register 0, 1 (UTCR0, UTCR1) and UART Prescaler Reload Register 0, 1
(UTRLR0, UTRLR1) .................................................................................................................. 402
18.5 UART Interrupt ................................................................................................................................ 404
18.5.1 Receive Interrupt Generation and Flag Set Timing ................................................................... 406
18.5.2 Transmit Interrupt Generation and Flag Set Timing .................................................................. 408
18.6 UART Baud Rate ............................................................................................................................ 410
18.6.1 Baud Rate of the UART Internal Clock Using the Dedicated Baud Rate Generator ................. 411
18.6.2 Baud Rate of the External Clock Using the Dedicated Baud Rate Generator ........................... 412
18.6.3 Baud Rate of the External Clock (One-to-one Mode) ................................................................ 413
18.7 Explanation of Operation of UART ................................................................................................. 414
18.7.1 Operation in Asynchronous Mode (Operation Mode 0 or Operation Mode1) ............................ 416
18.7.2 Operation in Synchronous Mode (Operation Mode 2) ............................................................... 419
18.7.3 Bidirectional Communication Function (Normal Mode) ............................................................. 422
18.7.4 Master/Slave Mode Communication Function (Multi-processor mode) ..................................... 424
18.8 Notes on Using UART .................................................................................................................... 427
18.9 Example of UART Programming .................................................................................................... 428
CHAPTER 19 I2C INTERFACE ....................................................................................... 431
19.1 I2C Interface Outline ....................................................................................................................... 432
19.2 I2C Interface Register ..................................................................................................................... 434
19.2.1 I2C Bus Status Register 0 (IBSR0) ............................................................................................ 435
19.2.2 I2C Bus Control Register 0 (IBCR0) .......................................................................................... 437
19.2.3 I2C Bus Clock Control Register 0 (ICCR0) ................................................................................ 443
19.2.4 I2C Bus Address Register 0 (IADR0) ......................................................................................... 445
19.2.5 I2C Bus Data Register 0 (IDAR0) .............................................................................................. 446
19.3 I2C Interface Operation ................................................................................................................... 447
19.3.1 Transfer Flow of I2C Interface ................................................................................................... 449
19.3.2 Mode Flow of I2C Interface ........................................................................................................ 451
19.3.3 Operation Flow of I2C Interface ................................................................................................. 452
CHAPTER 20 ROM MIRROR FUNCTION SELECTION MODULE ................................ 455
20.1 Overview of ROM Mirror Function Select Module .......................................................................... 456
20.2 ROM Mirror Function Select Register (ROMM) .............................................................................. 457
CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION ......................................... 459
21.1 Overview of Address Match Detection Function ............................................................................. 460
21.2 Block Diagram of Address Match Detection Function .................................................................... 461
21.3 Configuration of Address Match Detection Function ...................................................................... 462
21.3.1 Program Address Detection Control Status Register (PACSR) ................................................ 463
21.3.2 Program Address Detection Registers (PADR0, PADR1) ......................................................... 465
21.4 Explanation of Operation of Address Match Detection Function .................................................... 467
21.4.1 Example of Using Address Match Detection Function .............................................................. 468
21.5 Program Example of Address Match Detection Function ............................................................... 473

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CHAPTER 22 DUAL OPERATION FLASH MEMORY ................................................... 475
22.1 Overview of Dual Operation Flash Memory .................................................................................... 476
22.2 Sector/Bank Configuration of Flash Memory .................................................................................. 478
22.3 Registers of Flash Memory ............................................................................................................. 480
22.3.1 Flash Memory Control Status Register (FMCS) ........................................................................ 481
22.3.2 Flash Memory Write Control Register (FWR0/FWR1) ............................................................... 484
22.3.3 Sector Switching Register (SSR0) ............................................................................................. 489
22.4 How to Start Automatic Algorithm of Flash Memory ....................................................................... 491
22.5 Reset Vector Addresses in Flash Memory ..................................................................................... 493
22.6 Check the Execution State of Automatic Algorithm ........................................................................ 494
22.6.1 Data Polling Flag (DQ7) ............................................................................................................ 496
22.6.2 Toggle Bit Flag (DQ6) ................................................................................................................ 498
22.6.3 Timing Limit Over Flag (DQ5) .................................................................................................... 499
22.6.4 Sector Erase Timer Flag (DQ3) ................................................................................................. 500
22.7 Details of Programming/Erasing Flash Memory ............................................................................. 501
22.7.1 Read/Reset State in Flash Memory ........................................................................................... 502
22.7.2 Data Programming to Flash Memory ......................................................................................... 503
22.7.3 Data Erase from Flash Memory (Chip Erase) ........................................................................... 505
22.7.4 Erasing Any Data in Flash Memory (Sector Erasing) ................................................................ 506
22.7.5 Sector Erase Suspension .......................................................................................................... 508
22.7.6 Sector Erase Resumption .......................................................................................................... 509
22.8 Operation of Dual Operation Flash Memory ................................................................................... 510
CHAPTER 23 EXAMPLE of CONNECTING SERIAL WRITING .................................... 513
23.1 Basic Configuration ......................................................................................................................... 514
23.2 Oscillation Clock Frequency and Serial Clock Input Frequency ..................................................... 516
23.3 Flash Microcontroller Programmer System Configuration .............................................................. 517
23.4 Example of Connecting Serial Writing ............................................................................................ 518
23.4.1 Example Connection in Single-chip Mode (when Using User Power) ....................................... 519
23.4.2 Example of Minimum Connection to Flash Microcontroller Programmer (when Using User Power)
.................................................................................................................................................... 521
APPENDIX ......................................................................................................................... 523
APPENDIX A Memory Map ........................................................................................................................ 524
APPENDIX B Instructions ........................................................................................................................... 536
B.1 Instruction Types ............................................................................................................................ 537
B.2 Addressing ..................................................................................................................................... 538
B.3 Direct Addressing ........................................................................................................................... 540
B.4 Indirect Addressing ........................................................................................................................ 546
B.5 Execution Cycle Count ................................................................................................................... 554
B.6 Effective address field .................................................................................................................... 557
B.7 How to Read the Instruction List .................................................................................................... 558
B.8 F2MC-16LX Instruction List ............................................................................................................ 561
B.9 Instruction Map ............................................................................................................................... 575
INDEX................................................................................................................................... 597

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xiii
Main changes in this edition
Page Changes (For details, refer to main body.)
−−USB Mini-HOST →USB HOST
8CHAPTER 1 OVERVIEW
1.3 Package Dimension
■Package Dimension (LQFP-64)
Changed Package
FPT-64P-M09 →FPT-64P-M23
9CHAPTER 1 OVERVIEW
1.3 Pin Assignment
■Pin Assignment (FPT-64P-M23)
Changed Package
FPT-64P-M09 →FPT-64P-M23
35 CHAPTER 2 CPU
2.6 Registers
2.6.3 Processor Status (PS)
■Interrupt Level Mask Register
(ILM)
Corrected "Acceptable interrupt level" in Table 2.6-1.
37 CHAPTER 2 CPU
2.6.5 Bank Registers (PCB, DTB,
USB, SSB, ADB)
Corrected title and explanation.
40 CHAPTER 2 CPU
2.8 Prefix Codes Corrected "Bank select prefix" in Table 2.8-1.
PCC →PCB
245 CHAPTER 12 USB HOST
12.2 Restriction on USB HOST
■Restriction on USB HOST
Changed section title and table.
Diversity with USB HOST →Restriction on USB HOST
475 CHAPTER 22 DUAL OPERATION
FLASH MEMORY Combined two chapters.
"CHAPTER 22 512 KBIT FLASH MEMORY" &
"CHAPTER 23 DUAL OPERATION FLASH"
→
"CHAPTER 22 DUAL OPERATION FLASH MEMORY"
494 CHAPTER 22 DUAL OPERATION
FLASH MEMORY
22.6 Check the Execution State of
Automatic Algorithm
■Hardware Sequence Flags
Changed an explanation.
Deleted descriptions about "DQ2".
CHAPTER 22 DUAL OPERATION
FLASH MEMORY
Table 22.6-1
Changed "Bit No. 2".
DQ2 →−
495 CHAPTER 22 DUAL OPERATION
FLASH MEMORY
Table 22.6-2
Changed the table.
Changed rows.
Deleted "DQ2" column.
Corrected values.
Deleted remark "*".
500 CHAPTER 22 DUAL OPERATION
FLASH MEMORY
22.6 Check the Execution State of
Automatic Algorithm
Deleted "22.7.5 Toggle Bit 2 Flag (DQ2)".
(The section number is the value in old version)

xiv
507 CHAPTER 22 DUAL OPERATION
FLASH MEMORY
22.7.4 Erasing Any Data in Flash
Memory (Sector Erasing)
Figure 22.7-2
Changed figure.
Corrected flowchart.
542 APPENDIX B Instructions
B.3 Direct Addressing
●I/O direct addressing (io)
Changed Figure B.3-5.
(MOVW A, i : 0C0H →MOVW A, I:0C0H)
Added the note to Figure B.3-5.
543 APPENDIX B Instructions
B.3 Direct Addressing
●Abbreviated direct addressing
(dir)
Added the note to Figure B.3-6.
544 APPENDIX B Instructions
B.3 Direct Addressing
●I/O direct bit addressing (io:bp)
Changed Figure B.3-8.
(SETB i : 0C1H : 0 →SETB I:0C1H:0)
Added the note to Figure B.3-8.
APPENDIX B Instructions
B.3 Direct Addressing
●Abbreviated direct bit addressing
(dir:bp)
Added the note to Figure B.3-9.
550 APPENDIX B Instructions
B.4 Indirect Addressing
●Program counter relative branch
addressing (rel)
Changed Figure B.4-7.
(BRA 10H →BRA 3C32H)
551 APPENDIX B Instructions
B.4 Indirect Addressing
●Register list (rlst)
Changed Figure B.4-9.
(POPW, RW0, RW4 →POPW RW0, RW4)
576 APPENDIX B Instructions
B.9 Instruction Map
■Structure of Instruction Map
Changed column: instruction in Table B.9-1.
(@RW2+d8, #8, rel →CBNE @RW2+d8, #8, rel)
577 APPENDIX B Instructions
B.9 Instruction Map Changed the operand at row: +0, column: E0 in Table B.9-2.
(#4 →#vct4)
Changed the mnemonic at row: +0, column: D0 in Table B.9-2.
(MOV →MOVN)
Changed the mnemonic at row: +0, column: B0 in Table B.9-2.
(MOV →MOVX)
Changed the mnemonic at row: +8, column: B0 in Table B.9-2.
(MOV →MOVW)
579 Changed the mnemonic at row: +0, column: E0 in Table B.9-4.
(FILSI →FILSWI)
Page Changes (For details, refer to main body.)

xv
580 APPENDIX B Instructions
B.9 Instruction Map Changed Table B.9-5.
(·Moved "MUL A" and "MULW A" instruction from column:60 to
column:70.
· Changed mnemonic and moved the Instruction from column:60,
row:+A to column:70, row:+A.
(DIVU →DIV) )
581 Changed the operand at row: +E and +F, column: F0 in Table B.9-6.
(,#8, rel →#8, rel)
584 Changed the operand at row: +8 to +E, column: 50 in Table B.9-9.
(@@ →@)
Changed the operand at row: +0 to +7, column: 20 in Table B.9-9.
(RWi →@RWi)
585 Changed the operand at column: E0 and F0 in Table B.9-10.
(,r →,rel)
586 Changed the operand at column: 70 in Table B.9-11.
(NEG A, →NEG)
587 Changed the operand at column: E0 and F0 in Table B.9-12.
(,r →,rel)
595 Changed Table B.9-20 XCH Ri, ea Instruction (First Byte = 7EH).
(Column "A" →Column "A0",
Changed row "+A" ( W2+d16,A →@RW2+d16 ))
The vertical lines marked in the left side of the page show the changes.
Page Changes (For details, refer to main body.)