GE MiCOM P40 Agile User manual

GE Energy Connections
Grid Solutions
MiCOM P40 Agile
P141, P142, P143, P144, P145
Technical Manual
Feeder Management IED
Hardware Version: J
Software Version: 52
Publication Reference: P14xEd1-TM-EN-1

Contents
Chapter 1 Introduction 1
1 Chapter Overview 3
2 Foreword 4
2.1 Target Audience 4
2.2 Typographical Conventions 4
2.3 Nomenclature 5
3 Product Scope 6
3.1 Ordering Options 6
4 Features and Functions 7
4.1 Protection Functions 7
4.2 Control Functions 8
4.3 Measurement Functions 8
4.4 Communication Functions 8
5 Compliance 10
6 Functional Overview 11
Chapter 2 Safety Information 13
1 Chapter Overview 15
2 Health and Safety 16
3 Symbols 17
4 Installation, Commissioning and Servicing 18
4.1 Lifting Hazards 18
4.2 Electrical Hazards 18
4.3 UL/CSA/CUL Requirements 19
4.4 Fusing Requirements 19
4.5 Equipment Connections 20
4.6 Protection Class 1 Equipment Requirements 20
4.7 Pre-energisation Checklist 21
4.8 Peripheral Circuitry 21
4.9 Upgrading/Servicing 22
5 Decommissioning and Disposal 23
6 Regulatory Compliance 24
6.1 EMC Compliance: 2014/30/EU 24
6.2 LVD Compliance: 2014/35/EU 24
6.3 R&TTE Compliance: 2014/53/EU 24
6.4 UL/CUL Compliance 24
6.5 ATEX Compliance: 2014/34/EU 24
Chapter 3 Hardware Design 27
1 Chapter Overview 29
2 Hardware Architecture 30
3 Mechanical Implementation 31
3.1 Housing Variants 31
3.2 List of Boards 32
4 Front Panel 33
4.1 Front Panel 33
4.1.1 Front Panel Compartments 33
4.1.2 HMI Panel 34
4.1.3 Front Serial Port (SK1) 34
4.1.4 Front Parallel Port (SK2) 35
4.1.5 Fixed Function LEDs 35
4.1.6 Function Keys 35

4.1.7 Programable LEDs 36
5 Rear Panel 37
6 Boards and Modules 39
6.1 PCBs 39
6.2 Subassemblies 39
6.3 Main Processor Board 40
6.4 Power Supply Board 41
6.4.1 Watchdog 43
6.4.2 Rear Serial Port 44
6.5 Input Module - 1 Transformer Board 45
6.5.1 Input Module Circuit Description 46
6.5.2 Transformer Board 47
6.5.3 Input Board 48
6.6 Standard Output Relay Board 49
6.7 IRIG-B Board 50
6.8 Fibre Optic Board 51
6.9 Rear Communication Board 52
6.10 Ethernet Board 52
6.11 Redundant Ethernet Board 54
Chapter 4 Software Design 57
1 Chapter Overview 59
2 Sofware Design Overview 60
3 System Level Software 61
3.1 Real Time Operating System 61
3.2 System Services Software 61
3.3 Self-Diagnostic Software 61
3.4 Startup Self-Testing 61
3.4.1 System Boot 61
3.4.2 System Level Software Initialisation 62
3.4.3 Platform Software Initialisation and Monitoring 62
3.5 Continuous Self-Testing 62
4 Platform Software 63
4.1 Record Logging 63
4.2 Settings Database 63
4.3 Interfaces 63
5 Protection and Control Functions 64
5.1 Acquisition of Samples 64
5.2 Frequency Tracking 64
5.3 Direct Use of Sample Values 64
5.4 Fourier Signal Processing 64
5.5 Programmable Scheme Logic 65
5.6 Event Recording 66
5.7 Disturbance Recorder 66
5.8 Fault Locator 66
5.9 Function Key Interface 66
Chapter 5 Configuration 67
1 Chapter Overview 69
2 Settings Application Software 70
3 Using the HMI Panel 71
3.1 Navigating the HMI Panel 72
3.2 Getting Started 72
3.3 Default Display 73
3.4 Default Display Navigation 74
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3.5 Password Entry 75
3.6 Processing Alarms and Records 75
3.7 Menu Structure 76
3.8 Changing the Settings 77
3.9 Direct Access (The Hotkey menu) 78
3.9.1 Setting Group Selection Using Hotkeys 78
3.9.2 Control Inputs 78
3.9.3 Circuit Breaker Control 79
3.10 Function Keys 79
4 Date and Time Configuration 81
4.1 Using an SNTP Signal 81
4.2 Using an IRIG-B Signal 81
4.3 Using an IEEE 1588 PTP Signal 81
4.4 Without a Timing Source Signal 82
4.5 Time Zone Compensation 82
4.6 Daylight Saving Time Compensation 83
5 Settings Group Selection 84
Chapter 6 Current Protection Functions 85
1 Chapter Overview 87
2 Overcurrent Protection Principles 88
2.1 IDMT Characteristics 88
2.1.1 IEC 60255 IDMT Curves 89
2.1.2 European Standards 91
2.1.3 North American Standards 92
2.1.4 IEC and IEEE Inverse Curves 94
2.1.5 Differences Between the North american and European Standards 95
2.1.6 Programmable Curves 95
2.2 Principles of Implementation 95
2.2.1 Timer Hold Facility 96
3 Phase Overcurrent Protection 98
3.1 Phase Overcurrent Protection Implementation 98
3.2 Non-Directional Overcurrent Logic 99
3.3 Directional Element 100
3.3.1 Directional Overcurrent Logic 101
3.4 Application Notes 102
3.4.1 Parallel Feeders 102
3.4.2 Ring Main Arrangements 103
3.4.3 Setting Guidelines 103
3.4.4 Setting Guidelines (Directional Element) 104
4 Voltage Dependent Overcurrent Element 105
4.1 Voltage Dependent Overcurrent Protection Implementation 105
4.1.1 Voltage Controlled Overcurrent Protection 105
4.1.2 Voltage Restrained Overcurrent Protection 106
4.2 Voltage Dependent Overcurrent Logic 107
4.3 Application Notes 107
4.3.1 Setting Guidelines 107
5 Current Setting Threshold Selection 109
6 Cold Load Pickup 110
6.1 Implementation 110
6.2 CLP Logic 111
6.3 Application Notes 111
6.3.1 CLP for Resistive Loads 111
6.3.2 CLP for Motor Feeders 111
6.3.3 CLP for Switch Onto Fault Conditions 112
7 Selective Logic 113
7.1 Selective Logic Implementation 113
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7.2 Selective Logic Diagram 113
8 Timer Setting Selection 115
9 Negative Sequence Overcurrent Protection 116
9.1 Negative Sequence Overcurrent Protection Implementation 116
9.2 Non-Directional Negative Sequence Overcurrent Logic 117
9.3 Composite Earth Fault Start Logic 117
9.4 Directional Element 117
9.4.1 Directional Negative Sequence Overcurrent Logic 118
9.5 Application Notes 118
9.5.1 Setting Guidelines (Current Threshold) 118
9.5.2 Setting Guidelines (Time Delay) 119
9.5.3 Setting Guidelines (Directional element) 119
10 Earth Fault Protection 120
10.1 Earth Fault Protection Elements 120
10.2 Non-directional Earth Fault Logic 121
10.3 IDG Curve 121
10.4 Directional Element 122
10.4.1 Residual Voltage Polarisation 122
10.4.2 Negative Sequence Polarisation 123
10.5 Application Notes 124
10.5.1 Setting Guidelines (Directional Element) 124
10.5.2 Peterson Coil Earthed Systems 124
10.5.3 Setting Guidelines (Compensated networks) 128
11 Sensitive Earth Fault Protection 130
11.1 SEF Protection Implementation 130
11.2 Non-directional SEF Logic 130
11.3 SEF Any Start Logic 131
11.4 EPATR B Curve 131
11.5 Directional Element 132
11.5.1 Wattmetric Characteristic 133
11.5.2 Icos phi / Isin phi characteristic 134
11.5.3 Directional SEF Logic 135
11.6 Application Notes 136
11.6.1 Insulated Systems 136
11.6.2 Setting Guidelines (Insulated Systems) 137
12 Thermal Overload Protection 139
12.1 Single Time Constant Characteristic 139
12.2 Dual Time Constant Characteristic 139
12.3 Thermal Overload Protection Implementation 140
12.4 Thermal Overload Protection Logic 140
12.5 Application Notes 140
12.5.1 Setting Guidelines for Dual Time Constant Characteristic 140
12.5.2 Setting Guidelines for Single Time Constant Characteristic 142
13 Broken Conductor Protection 144
13.1 Broken Conductor Protection Implementation 144
13.2 Broken Conductor Protection Logic 144
13.3 Application Notes 144
13.3.1 Setting Guidelines 144
14 Blocked Overcurrent Protection 146
14.1 Blocked Overcurrent Implementation 146
14.2 Blocked Overcurrent Logic 146
14.3 Blocked Earth Fault Logic 146
14.4 Application Notes 147
14.4.1 Busbar Blocking Scheme 147
15 Second Harmonic Blocking 149
15.1 Second Harmonic Blocking Implementation 149
15.2 Second Harmonic Blocking Logic (POC Input) 150
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15.3 Second Harmonic Blocking Logic (SEF Input) 151
15.4 Application Notes 151
15.4.1 Setting Guidelines 151
16 Load Blinders 152
16.1 Load Blinder Implementation 152
16.2 Load Blinder Logic 153
17 Neutral Admittance Protection 156
17.1 Neutral Admittance Operation 156
17.2 Conductance Operation 156
17.3 Susceptance Operation 157
18 Busbar Protection 159
18.1 Buswire Supervision 160
Chapter 7 Restricted Earth Fault Protection 161
1 Chapter Overview 163
2 REF Protection Principles 164
2.1 Resistance-Earthed Star Windings 165
2.2 Solidly-Earthed Star Windings 165
2.3 Through Fault Stability 166
2.4 Restricted Earth Fault Types 166
2.4.1 Low Impedance REF Principle 167
2.4.2 High Impedance REF Principle 168
3 Restricted Earth Fault Protection Implementation 171
3.1 Restricted Earth Fault Protection Implementation 171
3.2 Low Impedance REF 171
3.2.1 Setting the Bias Characteristic 171
3.2.2 Delayed Bias 172
3.2.3 Transient Bias 172
3.3 High Impedance REF 172
3.3.1 High Impedance REF Calculation Principles 173
4 Application Notes 174
4.1 Star Winding Resistance Earthed 174
4.2 Low Impedance REF Protection Application 175
4.2.1 Setting Guidelines for Biased Operation 175
4.2.2 Low Impedance REF Scaling Factor 175
4.2.3 Parameter Calculations 176
4.3 High Impedance REF Protection Application 177
4.3.1 High Impedance REF Operating Modes 177
4.3.2 Setting Guidelines for High Impedance Operation 178
Chapter 8 CB Fail Protection 181
1 Chapter Overview 183
2 Circuit Breaker Fail Protection 184
3 Circuit Breaker Fail Implementation 185
3.1 Circuit Breaker Fail Timers 185
3.2 Zero Crossing Detection 185
4 Circuit Breaker Fail Logic 187
5 Undercurrent and ZCD Logic for CB Fail 190
6 CB Fail SEF Protection Logic 191
7 CB Fail Non Current Protection Logic 192
8 Circuit Breaker Mapping 193
9 Application Notes 194
9.1 Reset Mechanisms for CB Fail Timers 194
9.2 Setting Guidelines (CB fail Timer) 194
9.3 Setting Guidelines (Undercurrent) 195
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Chapter 9 Current Transformer Requirements 197
1 Chapter Overview 199
2 CT requirements 200
2.1 Phase Overcurrent Protection 200
2.1.1 Directional Elements 200
2.1.2 Non-directional Elements 200
2.2 Earth Fault Protection 201
2.2.1 Directional Elements 201
2.2.2 Non-directional Elements 201
2.3 SEF Protection (Residually Connected) 201
2.3.1 Directional Elements 201
2.3.2 Non-directional Elements 201
2.4 SEF Protection (Core-Balanced CT) 202
2.4.1 Directional Elements 202
2.4.2 Non-directional Elements 202
2.5 Low Impedance REF Protection 202
2.6 High Impedance REF Protection 202
2.7 High Impedance Busbar Protection 203
2.8 Use of Metrosil Non-linear Resistors 203
2.9 Use of ANSI C-class CTs 205
Chapter 10 Voltage Protection Functions 207
1 Chapter Overview 209
2 Undervoltage Protection 210
2.1 Undervoltage Protection Implementation 210
2.2 Undervoltage Protection Logic 211
2.3 Application Notes 212
2.3.1 Undervoltage Setting Guidelines 212
3 Overvoltage Protection 213
3.1 Overvoltage Protection Implementation 213
3.2 Overvoltage Protection Logic 214
3.3 Application Notes 215
3.3.1 Overvoltage Setting Guidelines 215
4 Rate of Change of Voltage Protection 216
4.1 Rate of Change of Voltage Protection Implementation 216
4.2 Rate of Change of Voltage Logic 216
5 Residual Overvoltage Protection 218
5.1 Residual Overvoltage Protection Implementation 218
5.2 Residual Overvoltage Logic 219
5.3 Application Notes 219
5.3.1 Calculation for Solidly Earthed Systems 219
5.3.2 Calculation for Impedance Earthed Systems 220
5.3.3 Neutral Voltage Displacement (Nvd) Protection Applied To Condenser Bushings (Capacitor Cones) 221
5.3.4 Setting Guidelines 227
6 Negative Sequence Overvoltage Protection 228
6.1 Negative Sequence Overvoltage Implementation 228
6.2 Negative Sequence Overvoltage Logic 228
6.3 Application Notes 228
6.3.1 Setting Guidelines 228
7 Sensitive Overvoltage Supervision 230
7.1 Sensitive Overvoltage Implementation 230
7.1.1 Sensitive Overvoltage Filter Mode 230
7.2 Sensitive Overvoltage Logic 231
7.2.1 Sensitive Overvoltage Operation Logic 231
7.2.2 Sensitive Overvoltage Filter Mode Logic 232
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7.2.3 Sensitive Overvoltage Blocking Logic 232
Chapter 11 Frequency Protection Functions 233
1 Chapter Overview 235
2 Frequency Protection Overview 236
2.1 Frequency Protection Implementation 236
3 Underfrequency Protection 238
3.1 Underfrequency Protection Implementation 238
3.2 Underfrequency Protection Logic 238
3.3 Application Notes 239
3.3.1 Setting Guidelines 239
4 Overfrequency Protection 240
4.1 Overfrequency Protection Implementation 240
4.2 Overfrequency Protection Logic 240
4.3 Application Notes 241
4.3.1 Setting Guidelines 241
5 Independent R.O.C.O.F Protection 242
5.1 Indepenent R.O.C.O.F Protection Implementation 242
5.2 Independent R.O.C.O.F Protection Logic 243
5.3 Application Notes 243
5.3.1 Setting Guidelines 243
6 Frequency-supervised R.O.C.O.F Protection 245
6.1 Frequency-supervised R.O.C.O.F Implementation 245
6.2 Frequency-supervised R.O.C.O.F Logic 246
6.3 Application Notes 246
6.3.1 Frequency-Supervised R.O.C.O.F Example 246
6.3.2 Setting Guidelines 247
7 Average Rate of Change of Frequency Protection 248
7.1 Average R.O.C.O.F Protection Implementation 248
7.2 Average R.O.C.O.F Logic 249
7.3 Application Notes 249
7.3.1 Setting Guidelines 249
8 Load Shedding and Restoration 251
8.1 Load Restoration Implementation 251
8.2 Holding Band 251
8.3 Load Restoration Logic 254
8.4 Application Notes 254
8.4.1 Setting Guidelines 254
Chapter 12 Power Protection Functions 257
1 Chapter Overview 259
2 Overpower Protection 260
2.1 Overpower Protection Implementation 260
2.2 Overpower Logic 261
2.3 Application Notes 261
2.3.1 Forward Overpower Setting Guidelines 261
2.3.2 Reverse Power Considerations 261
2.3.3 Reverse Overpower Setting Guidelines 262
3 Underpower Protection 263
3.1 Underpower Protection Implementation 263
3.2 Underpower Logic 264
3.3 Application Notes 264
3.3.1 Low Forward Power Considerations 264
3.3.2 Low Forward Power Setting Guidelines 264
4 Sensitive Power Protection 266
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4.1 Sensitive Power Protection Implementation 266
4.2 Sensitive Power Measurements 266
4.3 Sensitive Power Logic 267
4.4 Application Notes 267
4.4.1 Sensitive Power Calculation 267
4.4.2 Sensitive Power Setting Guidelines 269
5 Transient Earth Fault Detection 270
5.1 Transient Earth Fault Detection Implementation 271
5.1.1 Transient Earth Fault Detector 271
5.1.2 Fault Type Detector 271
5.1.3 Direction Detector 271
5.2 Transient Earth Fault Detection Logic 272
5.2.1 Transient Earth Fault Detection Logic Overview 272
5.2.2 Fault Type Detector Logic 273
5.2.3 Direction Detector Logic - Standard Mode 273
5.2.4 Transient Earth Fault Detection Output Alarm Logic 273
Chapter 13 Autoreclose 275
1 Chapter Overview 277
2 Introduction to 3-phase Autoreclose 278
3 Implementation 279
4 Autoreclose Function Inputs 280
4.1 CB Healthy 280
4.2 Block AR 280
4.3 Reset Lockout 280
4.4 AR Auto Mode 280
4.5 Auto Mode 280
4.6 LiveLine Mode 280
4.7 Telecontrol Mode 280
4.8 Circuits OK 280
4.9 AR Sys Checks OK (403) 281
4.10 Ext AR Prot Trip (External AR Protection Trip) 281
4.11 Ext AR Prot Start (External AR Protection Start) 281
4.12 DAR Complete (Delayed Autoreclose Complete) 281
4.13 CB in Service (Circuit Breaker in Service) 281
4.14 AR Restart 281
4.15 DT OK To Start (Dead Time OK to Start) 281
4.16 DeadTime Enabled 282
4.17 AR Init TripTest (Initiate Trip Test) 282
4.18 AR Skip Shot 1 282
4.19 Inh Reclaim Time (Inhibit Reclaim Time) 282
5 Autoreclose Function Outputs 283
5.1 AR In Progress 283
5.2 AR in Progress 1 (DAR In Progress) 283
5.3 Sequence Counter Status DDB signals 283
5.4 Successful Close 283
5.5 AR In Service 283
5.6 Block Main Prot (Block Main Protection) 283
5.7 Block SEF Prot (Block SEF Protection) 283
5.8 Reclose Checks 283
5.9 DeadT In Prog (Dead Time in Progress) 284
5.10 DT Complete (Dead Time Complete) 284
5.11 AR Sync Check (AR Synchronisation Check) 284
5.12 AR SysChecks OK (AR System Checks OK) 284
5.13 Auto Close 284
5.14 Protection Lockt (Protection Lockout) 284
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