HOLT ADK-5200 User manual

QSG-5200 Rev. A Holt Integrated Circuits
ADK-5200
Quick Start Guide:
HI-5200 10Base-T/100Base-TX
Physical Layer Transceiver
April 2018

QSG-5200
2 Holt Integrated Circuits
REVISION HISTORY
Revision
Date
Description of Change
QSG-5200, Rev. New
02-09-18
Initial Release
Rev. A
04-23-18
Remove HI-5201 option

QSG-5200
3 Holt Integrated Circuits
Introduction
The Holt HI-5200 is a 10Base-T/100Base-TX physical layer transceiver with both MII and RMII MAC
interfaces. It utilizes a unique mixed-signal design to extend signaling distance while reducing power
consumption, and offers HP Auto MDI/MDI-X for reliable detection of and correction for crossover and
straight-through cables. The device comes in a 32-pin, lead-free QFN package and provides an ideal
solution for 10Base-T/100Base-TX applications that have limited PCB board space.
The HI-5200 ADK evaluation board, ADK-5200, provides a convenient platform to evaluate HI-5200
features. All device configuration pins are accessible either by jumpers, test points or interface
connectors on the board.
Figure 1. HI-5200 ADK Evaluation Board, ADK-5200

QSG-5200
4 Holt Integrated Circuits
Features
●Holt 10Base-T/100Base-TX Physical Layer Transceiver
●RJ-45 Jack for Fast Ethernet cable interface
●HP Auto-MDIX for automatic detection and correction for straight-through and crossover cables
●MII (Media Independent Interface) connector to interface with a MAC controller
●RMII (Reduced MII) option with external 50MHz system clock
●2 LED Indicators for status and activity
●Jumpers to configure strapping pins
●Manual Reset Button for quick reboot after re-configuration of strapping pins
Hardware Design Overview
Figure 2 shows a block diagram of the HI-5200 ADK evaluation board. It plugs into any industry standard
“Fast Ethernet” board with Ethernet MACs that expose the MII interface. Configuration of the HI-5200 is
accomplished through on-board jumper selections and/or by PHY register access via the MDC/MDIO
management pins of the MII Interface.
Other features include a RJ-45 Jack for “Fast Ethernet” cable connection, programmable LEDs for
reporting link status and activity, and a manual reset button for quick reboot after reconfiguration of
strapping pins.
The HI-5200 evaluation board receives +5V DC input power through its MII connector.
Figure 2. ADK-5200 Evaluation Board Block Diagram
10Base-T
100Base-TX
RJ45 Jack
Single Port
Magnetic
Module
TX / RX
Pairs
HI-5200PC
Config
Headers
Port
Status
LEDs
Config
Headers
Reset
Button
MII / RMII Port Connector
MII / RMII
Signals
Port
Status
LEDs
25 MHz
Crystal
Oscillator
MII Mode Only
RMII 50 MHz REF_CLK
LDO 3.3V
Regulator
5 VDC
Input
RMII Mode Only (From MAC)

QSG-5200
5 Holt Integrated Circuits
MII (Media Independent Interface) Default Configuration
The MII interface is defined by Clause 22 of the IEEE 802.3 Specification. The HI-5200 PHY evaluation
board receives power and accesses MII data and management information from the MII connector J1. In
MII mode, the PHY is clocked at 25 MHz. A crystal oscillator on the board provides the clock, or an
external 25MHz clock can be connected to the XI pin.
MII Management (MIIM) is conducted thru pins MDC (clock line) and MDIO (data line). MIIM allows
upper-layer devices to monitor and control the states of the HI-5200. An external device with
MDC/MDIO capability can read the PHY status or configure/write the PHY registers. The MIIM frame
format and timing information can be found in the HI-5200 Datasheet and in Clause 22 of the IEEE 802.3
Specification.
The HI-5200 PHY board has a bottom-side 50-pin connector J1 for MII connection. Table 1 lists the pin-
outs for the MII interface on connector J1.
Table 1. Connector J1 Fast Ethernet Port MII Pin Definition.
J1 Pin #
Signal
J1 Pin #
Signal
1
--
2
--
3
--
4
--
5
+5V
6
+5V
7
MDIO
8
GND
9
MDC
10
GND
11
RXD3
12
GND
13
RXS2
14
GND
15
RXD1
16
GND
17
RXD0
18
GND
19
RXDV
20
GND
21
RXCLK
22
GND
23
RXER
24
GND
25
TXER
26
GND
27
TXCLK
28
GND

QSG-5200
6 Holt Integrated Circuits
J1 Pin #
Signal
J1 Pin #
Signal
29
TXEN
30
GND
31
TXD0
32
GND
33
TXD1
34
GND
35
TXD2
36
GND
37
TXD3
38
GND
39
COL
40
GND
41
CRS
42
GND
43
+5V
44
+5V
45
--
46
--
47
--
48
--
49
--
50
--
RMII (Reduced Media Independent Interface) Configuration Option
The HI-5200 ADK PHY evaluation board can use its 50-pin male edge connector (J1) with some minor
board population changes to interface with RMII MACs. Like MII mode, the HI-5200 ADK PHY evaluation
board, ADK-5200, receives power and accesses RMII data and management information via connector J1
in RMII mode. In RMII mode, the 50MHz clock (from the MAC) is connected to the XI pin.
The HI-5200 ADK PHY evaluation board and MAC hardware devices can be configured to RMII mode and
interface with each other using the same J1 connector interface. The board changes to support RMII
mode are as follows:
1. Remove crystal circuit (Y1, C16, C17) and TXC clock termination (R6).
2. Populate R14 with 0 Ohm and R19 with 33 Ohm to connect HI-5200 RMII 50MHz reference clock
(provided by MAC side via J1 pin 27) to U1 pin 9 (XI input).
3. Select RMII mode by setting strapping pins CONFIG[2:0] to ‘001’.
These board changes can also be found in the HI-5200 ADK PHY evaluation board schematic diagram.

QSG-5200
7 Holt Integrated Circuits
Table 2 lists the pin outs for the RMII interface on connector J1.
Table 2. Connector J1 Fast Ethernet Port RMII Pin Definition.
J1 Pin #
Signal
J1 Pin #
Signal
1
--
2
--
3
--
4
--
5
+5V
6
+5V
7
MDIO
8
GND
9
MDC
10
GND
11
not used
12
GND
13
not used
14
GND
15
RXD1
16
GND
17
RXD0
18
GND
19
RXDV
20
GND
21
not used
22
GND
23
RXER
24
GND
25
not used
26
GND
27
REFCLK
28
GND
29
TXEN
30
GND
31
TXD0
32
GND
33
TXD1
34
GND
35
not used
36
GND
37
not used
38
GND
39
not used
40
GND
41
not used
42
GND

QSG-5200
8 Holt Integrated Circuits
J1 Pin #
Signal
J1 Pin #
Signal
43
+5V
44
+5V
45
--
46
--
47
--
48
--
49
--
50
--

QSG-5200
9 Holt Integrated Circuits
Jumper Setting & Definition
The HI-5200 ADK PHY evaluation board does not require any jumper for normal operation. At power-up,
the HI-5200 ADK PHY is configured using the chip’s internal pull-up and pull-down resistors with its
default strapping pin values. Jumpers are provided to override the default settings, allowing for quick
configuration and re-configuration of the board. To override the default settings, simply select and close
the desired jumper setting(s) and toggle the on-board manual reset button (S1) for the new setting(s) to
take effect.
The HI-5200 ADK PHY evaluation board jumper settings are defined in Table 3 below.
Table 3. HI-5200PC Evaluation Board Jumper Definitions.
Jumper
Definition
Open (default)
Closed
JP1
PHYAD0
1
0
JP2
PHYAD1
0
1
JP3
PHYAD2
0
1
Jumper
Definition
CONFIG[2:0]
Mode
JP4
CONFIG0
[open, open, open]
MII (default)
JP5
CONFIG1
[open, open, close]
RMII
JP6
CONFIG2
[close, open, open]
PCS Loopback
All other CONFIG[2:0] combinations are reserved, not used.
Jumper
Definition
Open (default)
Closed
JP7
Isolate Mode
Disabled
Enabled
JP8
Auto Negotiation
Enabled
Disabled
JP9
Forced Speed
100Base-TX
10Base-T
JP10
Forced Duplex
Half Duplex
Full Duplex

QSG-5200
10 Holt Integrated Circuits
Table 4 lists the pin strapping definitions for the HI-5200 ADK PHY evaluation board jumpers.
Table 4. HI-5200PC Pin Strapping Options on PHY Evaluation Board.
Jumper
U1 Pin #
Pin
Name
Pin Function
JP3
JP2
JP1
15
14
13
PHYAD2
PHYAD1
PHYAD0
The PHY address is latched at power-up / reset
and is configurable to any value from 1 to 7.
The default PHY address is 00001.
PHY address bits [4:3] are always set to 00.
JP6
JP5
JP4
18
29
28
CONFIG2
CONFIG1
CONFIG0
The CONFIG[2:0] pins are latched at power-up / reset and
are defined as follows:
CONFIG[2:0] = 000 MII Mode (default)
CONFIG[2:0] = 001 RMII Mode
CONFIG[2:0] = 100 PCS Loopback
All other CONFIG[2:0] combinations are reserved.
JP7
20
ISO
ISOLATE Mode
Pull-Up = Enable
Pull-Down = Disable (default)
At power-up / reset, the state of this pin is latched into
register 0 bit 10.
JP9
31
SPEED
SPEED Mode
Pull-Up = 100Mbps (default)
Pull-Down = 10Mbps
At power-up / reset, the state of this pin is latched into
register 0 bit 13 as the Speed Select, and is also latched
into register 4 (Auto Negotiation Advertisement) as the
Speed capability support.
JP10
16
DUPLEX
DUPLEX Mode
Pull-Up = Half Duplex (default)
Pull-Down = Full Duplex
At power-up / reset, the state of this pin is latched into
register 0 bit 8 as the Duplex Mode.
JP8
30
NWAYEN
Nway Auto-Negotiation Enable
Pull-Up = Enable Auto-Negotiation (default)
Pull-Down = Disable Auto-Negotiation
At power-up / reset, the state of this pin is latched into
register 0 bit 12.