HP 1660C Series User manual

Service Guide
Publication number 01660-97026
First edition, November 1997
For Safety information, Warranties, and Regulatory
information, see the pages at the end of the book.
Copyright Hewlett-Packard Company 1987–1997
All Rights Reserved.
HP 1660C/CS/CP-Series
Logic Analyzers

HP 1660C-Series, HP 1660CS-Series, and
HP 1660CP-Series Logic Analyzers
The HP 1660C-Series are 100-MHz State/500 MHz Timing Logic Analyzers.
The HP 1660CS-Series includes all the features of the HP 1660C-Series, as well as a
2-channel, 1 GSa/s oscilloscope.
The HP 1660CP-Series includes all the features of the HP 1660C-Series, as well as a
32-channel pattern generator.
Features
Some of the main features of the HP 1660C-Series Logic Analyzers are as follows:
•128 data channels and 6 clock/data channels in the HP 1660C
•96 data channels and 6 clock/data channels in the HP 1661C
•64 data channels and 4 clock/data channels in the HP 1662C
•32 data channels and 2 clock/data channels in the HP 1663C
•3.5-inch flexible disk drive
•540 MB hard disk drive
•HP-IB, RS-232-C, and Centronics printer interfaces
•Variable setup/hold time
•4k states deep memory on all channels with 8k states in half channel mode
•Marker measurements
•12 levels of trigger sequencing for state and 10 levels of sequential triggering for
timing
•100 MHz time and number-of-states tagging
•Full programmability
•DIN mouse
•DIN keyboard support
The HP 1660CP-Series Logic Analyzers also include the following features:
•32 channels of stimulus
•Maximum output rate of 200 MHz in half-channel mode and 100 MHz in
full-channel mode
•Memory depth of 258,048 vectors
•Support for TTL, 3-state TTL/3.3v, 3-state TTL/CMOS, ECL terminated, ECL
unterminated, and differential ECL (without pod).
ii

The HP 1660CS-Series Logic Analyzers also include the following features:
•1 GSa/s digitizing for 250 MHz bandwidth single shot oscilloscope
•8000 samples per channel
•Automatic pulse parameters
displays time between markers, acquires until specified time between markers is
captured, performs statistical analysis on time between markers
•Lightweight miniprobes
Options
The HP 1660C-Series, HP 1660CP-Series, and HP 1660CS-Series Logic Analyzers can
be ordered with the optional Thinlan and Ethertwist LAN ports.
Service Strategy
The service strategy for this instrument is the replacement of defective assemblies.
This service guide contains information for finding a defective assembly by testing
and servicing the HP 1660C/CS/CP-Series Logic Analyzers.
This logic analyzer can be returned to Hewlett-Packard for all service work, including
troubleshooting. Contact your nearest Hewlett-Packard Sales Office for more details.
The HP 1660-Series Logic Analyzer
iii

In This Book
This book is the service guide for the HP 1660C/CS/CP-Series Logic Analyzers and is divided
into eight chapters.
Chapter 1 contains information about the logic analyzer and includes accessories,
specifications and characteristics, and equipment required for servicing.
Chapter 2 tells how to prepare the logic analyzer for use.
Chapter 3 gives instructions on how to test the performance of the logic analyzer.
Chapter 4 contains calibration instructions for the logic analyzer.
Chapter 5 contains self-tests and flowcharts for troubleshooting the logic analyzer.
Chapter 6 tells how to replace assemblies of the logic analyzer and how to return them to
Hewlett-Packard.
Chapter 7 lists replaceable parts, shows an exploded view, and gives ordering information.
Chapter 8 explains how the logic analyzer works and what the self-tests are checking.
iv

Table of Contents
1 General Information
Accessories 1–2
Specifications (logic analyzer) 1–3
Specifications (oscilloscope) 1–4
Specifications (pattern generator) 1–4
Characteristics (logic analyzer) 1–5
Characteristics (oscilloscope) 1–5
Characteristics (pattern generator) 1–6
Supplemental Characteristics (logic analyzer) 1–7
Supplemental Characteristics (oscilloscope) 1–10
Recommended test equipment (logic analyzer) 1–14
Recommended test equipment (oscilloscope) 1–15
Recommended test equipment (pattern generator) 1–16
2 Preparing for Use
To inspect the logic analyzer 2–2
To apply power 2–3
To operate the user interface 2–3
To set the line voltage 2–3
To degauss the display 2–4
To clean the logic analyzer 2–4
To test the logic analyzer 2–4
3 Testing Performance
To perform the self-tests 3–3
To make the test connectors (logic analyzer) 3–7
To test the threshold accuracy (logic analyzer) 3–9
Set up the equipment 3–9
Set up the logic analyzer 3–10
Connect the logic analyzer 3–10
Test the TTL threshold 3–11
Test the ECL threshold 3–13
Test the −User threshold 3–14
Test the + User threshold 3–15
Test the 0 V User threshold 3–16
Test the next pod 3–17
To test the glitch capture (logic analyzer) 3–18
Set up the equipment 3–18
Set up the logic analyzer 3–19
Connect the logic analyzer 3–19
Test the glitch capture on the connected channels 3–21
Test the next channels 3–23
v

To test the single-clock, single-edge, state acquisition (logic analyzer) 3–24
Set up the equipment 3–24
Set up the logic analyzer 3–25
Connect the logic analyzer 3–27
Verify the test signal 3–29
Check the setup/hold combination 3–31
Test the next channels 3–36
To test the multiple-clock, multiple-edge, state acquisition (logic analyzer) 3–37
Set up the equipment 3–37
Set up the logic analyzer 3–38
Connect the logic analyzer 3–40
Verify the test signal 3–42
Check the setup/hold with single clock edges, multiple clocks 3–44
Test the next channels 3–48
To test the single-clock, multiple-edge, state acquisition (logic analyzer) 3–49
Set up the equipment 3–49
Set up the logic analyzer 3–50
Connect the logic analyzer 3–52
Verify the test signal 3–54
Check the setup/hold with single clock, multiple clock edges 3–56
Test the next channels 3–59
To test the time interval accuracy (logic analyzer) 3–60
Set up the equipment 3–60
Set up the logic analyzer 3–61
Connect the logic analyzer 3–64
Acquire the data 3–64
To test the CAL OUTPUT ports (oscilloscope) 3–65
Set up the equipment 3–65
Set up the logic analyzer 3–66
Verify the DC CAL OUTPUT port 3–67
Set up the logic analyzer 3–68
Verify the AC CAL OUTPUT port 3–68
To test the input resistance (oscilloscope) 3–69
Set up the equipment 3–69
Set up the logic analyzer 3–70
Connect the logic analyzer 3–71
Acquire the data 3–72
Perform an operational accuracy calibration 3–72
Contents
vi

To test the voltage measurement accuracy (oscilloscope) 3–73
Set up the equipment 3–73
Set up the logic analyzer 3–74
Connect the logic analyzer 3–75
Acquire the data 3–76
To test the offset accuracy (oscilloscope) 3–77
Set up the equipment 3–77
Set up the logic analyzer 3–78
Connect the logic analyzer 3–79
Acquire the zero input data 3–80
Acquire the DC input data 3–81
To test the bandwidth (oscilloscope) 3–82
Set up the equipment 3–82
Set up the logic analyzer 3–83
Connect the logic analyzer 3–85
Acquire the data 3–86
To test the time measurement accuracy (oscilloscope) 3–87
Set up the equipment 3–87
Set up the logic analyzer 3–88
Connect the logic analyzer 3–90
Acquire the data 3–90
To test the trigger sensitivity (oscilloscope) 3–91
Set up the equipment 3–91
Set up the logic analyzer 3–92
Connect the logic analyzer 3–94
Acquire the data 3–94
Performance Test Record (logic analyzer) 3–95
Performance Test Record (oscilloscope) 3–101
Performance Test Record (pattern generator) 3–104
Contents
vii

4 Calibrating and Adjusting
Logic analyzer calibration 4–2
To calibrate the oscilloscope 4–3
Set up the equipment 4–3
Load the Default Calibration Factors 4–4
Self Cal menu calibrations 4–5
To adjust the CRT monitor alignment 4–6
To adjust the CRT intensity 4–8
5 Troubleshooting
To use the flowcharts 5–2
To check the power-up tests 5–17
To run the self-tests 5–18
To test the power supply voltages 5–24
To test the CRT monitor signals 5–26
To test the keyboard signals 5–27
To test the flexible disk drive voltages 5–28
To test the hard disk drive voltages 5–30
To perform the BNC test 5–31
To test the logic analyzer probe cables 5–32
To verify pattern output (HP 1660CP-Series only) 5–36
To test the auxiliary power 5–38
6 Replacing Assemblies
To remove and replace the handle 6–5
To remove and replace the feet and tilt stand 6–5
To remove and replace the cover 6–5
To remove and replace the disk drive assembly 6–6
To remove and replace the power supply 6–7
To remove and replace the CPU board 6–7
To remove and replace SIMM memory 6–8
To remove and replace the switch actuator assembly 6–9
To remove and replace the rear panel assembly 6–10
To remove and replace the HP 1660C-series acquisition board 6–11
To remove and replace the HP 1660CS-series oscilloscope board 6–12
To remove and replace the HP 1660CP-series pattern generator board 6–13
To remove and replace the front panel and keyboard 6–14
To remove and replace the intensity adjustment 6–14
To remove and replace the monitor 6–15
To remove and replace the handle plate 6–15
To remove and replace the fan 6–16
To remove and replace the line filter 6–16
To remove and replace the HP 1660CP-series pattern generator cables 6–17
To remove and replace the HP-IB and RS-232-C cables 6–17
To remove and replace the I/O board 6–18
Contents
viii

To return assemblies 6–18
7 Replaceable Parts
Replaceable Parts Ordering 7–2
Replaceable Parts List 7–3
Exploded View 7–4
Power Cables and Plug Configurations 7–8
8 Theory of Operation
Block-Level Theory 8–3
The HP 1660C/CS/CP Series Logic Analyzer 8–3
The Logic Acquisition Board 8–7
The Oscilloscope Board 8–10
The Pattern Generator Board 8–13
Self-Tests Description 8–15
Power-up Self-Tests 8–15
System Tests (System PV) 8–16
Analyzer Tests (Analy PV) 8–20
Oscilloscope tests (Scope PV) 8–22
Pattern Generator tests (Patt Gen) 8–23
HP-IB 8–27
RS-232-C 8–28
Contents
ix

x

1
Accessories 1–2
Specifications (logic analyzer) 1–3
Specifications (oscilloscope) 1–4
Specifications (pattern generator) 1–4
Characteristics (logic analyzer) 1–5
Characteristics (oscilloscope) 1–5
Characteristics (pattern generator) 1–6
Supplemental Characteristics (logic analyzer) 1–7
Supplemental Characteristics (oscilloscope) 1–10
Recommended test equipment (logic analyzer) 1–14
Recommended test equipment (oscilloscope) 1–15
Recommended test equipment (pattern generator) 1–16
General Information

General Information
This chapter lists the accessories, the specifications and characteristics, and the
recommended test equipment.
Accessories
The following accessories are supplied with the HP 1660C/CS/CP-series logic analyzers.
Accessories Supplied HP Part Number Qty
Probe tip assemblies 01650-61608 Note 1
Probe cables 01660-61605 Note 2
Grabbers (20 per pack) 5090-4356 Note 1
Probe ground (5 per pack) 5959-9334 Note 1
Demo Training Kit E2433-60012 1
HP 1660C User’s Guide 01660-99016 1*
Symbol Utility (disk and manual) E2450A 1
Accessories Pouch 01660-84501 1
RS-232-C Loopback Connector 01650-63202 1
PS2 Mouse A2839B 1
* The HP 1660CS and HP 1660CP have their own User’s Guide. For those products, the
HP 1660C User’s Guide is not shipped.
Note 1 Quantities: 8 - 1660C.CS Note 2 Quantities: 4 - 1660C.CS
6 - 1661C.CS 3 - 1661C.CS
4 - 1662C.CS 2 - 1662C.CS
2 - 1663C.CS 1 - 1663C.CS
CP-Series Additional Accessories
Accessories Supplied HP Part Number Qty
Data Output Cable 16522-61601 4
Clock Output Cable 16522-61602 1
HP 1660CP User’s Guide 01660-97023 1
CS-Series Additional Accessories
Accessories Supplied HP Part Number Qty
10:1 probes 10430A 2
BNC miniprobe adapter 1250-1454 1
HP 1660CS User’s Guide 01660-99019 1
Accessories Available
Other accessories available for the HP 1660C/CS/CP Series Logic Analyzer are listed in the
Accessories for HP Logic Analyzers brochure.
1–2

Specifications (logic analyzer)
The specifications are the performance standards against which the product is tested.
Maximum State Speed 100 MHz
Minimum State Clock Pulse Width*3.5 ns
Minimum Master to Master Clock Time*10.0 ns
Minimum Glitch Width* 3.5 ns
Threshold Accuracy ±(100 mV + 3% of threshold setting)
Setup/Hold Time:*
Single Clock, Single Edge 0.0/3.5 ns through 3.5/0.0 ns,
adjustable in 500-ps increments
Single Clock, Multiple Edges 0.0/4.0 ns through 4.0/0.0 ns,
adjustable in 500-ps increments
Multiple Clocks, Multiple Edges 0.0/4.5 ns through 4.5/0.0 ns,
adjustable in 500-ps increments
* Specified for aninput signal VH = −0.9 V, VL = −1.7 V, slew rate = 1 V/ns, and threshold=−1.3 V.
General Information
Specifications (logicanalyzer)
1–3

Specifications (oscilloscope)
The HP 1660CS Logic Analyzers also include the following specifications:
Bandwidth (*,1) DC to 250 MHz (real time, dc-coupled)
Time Interval Measurement Accuracy(*, 2) ±[(0.005% X ∆t)+
(2 x 10−6x delay setting)+150 ps]
DC Offset Accuracy(*) ±(1.0% of channel offset + 2.0% of full scale)
Voltage Measurement Accuracy(*, 3) ±[(1.5% of full scale + offset accuracy)
+ (0.008 x V/div)]
Trigger Sensitivity(*) DC to 50 MHz: 0.063 x full scale,
50 to 250 MHz: 0.125 x full scale
Input R (selectable) (*) 1 MΩ: ±1%, 50 Ω: ±1%
* Specifications(validwithin±10°C of auto-calibration temperature, excluding bandwidth−see note 1 for bandwidthspecification.)
1. Upper bandwidth reduces by 2.5 MHz for every degree C above 35°C.
2. Specification applies to the maximum sampling rate. At lower rates, the specification is:±[(0.005% x ∆t)+(2 x 10-6 x delay setting) +
(0.15 x sample interval)] for bandwidth limited signals (tr= 1.4 x sample interval). Sampleinterval is defined as 1
sample rate
3. Digitizing level = (#vertical divisions)(1
2)( 1
LSB
), whereLSB=2#bitsinADC
Specifications (pattern generator)
There are no specifications for the pattern generator portion of the HP 1660CP-Series Logic
Analyzers.
General Information
Specifications (oscilloscope)
1–4

Characteristics (logic analyzer)
These characteristics are not specifications, but are included as additional information.
Full Channel Half Channel
Maximum State Clock Rate 100 MHz 100 MHz
Maximum Conventional Timing Rate 250 MHz 500 MHz
Maximum Transitional Timing Rate 125 MHz 250 MHz
Maximum Timing with Glitch Rate N/A 125 MHz
Memory Depth 4K 8K*
Channel Count:
HP 1660C,CP,CS 136 68
HP 1661C,CP, CS 102 51
HP 1662C,CP,CS 68 34
HP 1663C,CP,CS 34 17
* For all modes except glitch.
Characteristics (oscilloscope)
The HP 1660CS Logic Analyzers also include the following characteristics:
Maximum Sample Rate 1 Gigasample per second
Number of Channels 2
Rise Time(1) 1.4 ns
ADC 8-bit real time
Vertical Resolution 8 bits over 4 vertical divisions (±0.4%)
Waveform Record Length 8000 points
Vertical (DC) Gain Accuracy(2) ±1.25% of full scale
Input Coupling 1 MΩ: ac and DC, 50 Ω: DC only
Input C Approximately 7 pF
1. Rise time is calculated from the formula: t
r
=0.35
bandwidth
2. Vertical gain accuracy decreases 0.08% per degree C from software calibration temperature.
General Information
Characteristics (logic analyzer)
1–5

Characteristics (pattern generator)
The HP 1660CP Logic Analyzers also include the following characteristics:
Output channels 16 channels at 200 MHz clock; 32 channels at
100 MHz clock
Memory depth 258,048 vectors
Logic levels (data pods) TTL, 3-state TTL/3.3v, 3-state TTL/CMOS,
ECL terminated, ECL unterminated, and differential
ECL (without pod)
Data inputs 3-bit pattern - level sensing (clock pod)
Clock outputs Synchronized to output data, delay of 11 ns in 9 steps
(clock pod)
Clock input DC to 200 MHz (clock pod)
Internal clock period Programmable from 5 ns to 250 µs in a 1, 2, 2.5, 4, 5, 8
sequence
External clock period (user supplied) DC to 200 MHz
External clock duty cycle 2 ns minimum high time
Maximum number of "IF condition" 1
blocks at 50 MHz clock
Maximum number of different macros 100
Maximum number of lines in a macro 1024
Maximum number of macro invocations 1,000
Maximum number of Repeat loop 1,000
invocations
Maximum number of Wait event patterns 4
General Information
Characteristics (pattern generator)
1–6

Supplemental Characteristics (logic analyzer)
Probes
Input Resistance 100 kΩ, ±2%
Input Capacitance ~ 8 pF
Minimum Voltage Swing 500 mV, peak-to-peak
Threshold Range ±6.0 V, adjustable in 50-mV increments, CAT I
Maximum Input Voltage ±40 volts, CAT I
State Analysis
State/Clock Qualifiers 1660/61C,CP,CS - 6; 1662C,CP,CS - 4; 1663C,CP,CS - 2
Time Tag Resolution*8 ns or 0.1%, whichever is greater
Maximum Time Count
Between States 34 seconds
Maximum State Tag Count*4.29 x 109
Timing Analysis
Sample Period Accuracy 0.01 % of sample period
Channel-to-Channel Skew 2 ns, typical
Time Interval Accuracy ±[sample period + channel-to-channel skew
+(0.01%)(time reading)]
Triggering
Sequencer Speed 125 MHz, maximum
State Sequence Levels 12
Timing Sequence Levels 10
Maximum Occurrence Counter
Value 1,048,575
Pattern Recognizers 10
Maximum Pattern Width 136 channels in HP 1660C,CP,CS, 102 channels in
HP 1661C,CP,CS, 68 channels in HP 1662C,CP,CS,
34 channels in HP 1663C,CP,CS
Range Recognizers 2
Range Width 32 bits each
Timers 2
Timer Value Range 400 ns to 500 seconds
Glitch/Edge Recognizers 2 (timing only)
Maximum Glitch/Edge Width 136 channels in HP 1660C,CP,CS, 102 channels in
HP 1661C,CP,CS, 68 channels in HP 1662C,CP,CS,
34 channels in HP 1663C,CP,CS
*Maximum state clock rate with time or state tags on is 100 MHz. When all pods are assigned to astate or timingmachine, time or
state tags halve thememory depth.
General Information
SupplementalCharacteristics (logicanalyzer)
1–7

Measurement and Display Functions
Displayed Waveforms 24 lines maximum, with scrolling across 96 waveforms.
Measurement Functions
Run/Stop Functions Run starts acquisition of data in specified trace mode.
Stop In single trace mode or the first run of a repetitive acquisition, Stop halts
acquisition and displays the current acquisition data. For subsequent runs in repetitive
mode, Stop halts acquisition of data and does not change the current display.
Trace Mode Single mode acquires data once per trace specification. Repetitive mode
repeats single mode acquisitions until Stop is pressed or until the time interval between
two specified patterns is less than or greater than a specified value, or within or not within
a specified range.
Indicators
Activity Indicators Provided in the Configuration and Format menus for identifying
high, low, or changing states on the inputs.
Markers Two markers (X and O) are shown as vertical dashed lines on the display.
Trigger Displayed as a vertical dashed line in the Timing Waveform display and as line 0
in the State Listing display.
Data Entry/Display
Labels Channels may be grouped together and given a 6-character name. Up to
126 labels in each analyzer may be assigned with up to 32 channels per label.
Display Modes State listing, State Waveforms, Chart, Compare Listing, Compare
Difference Listing, Timing Waveforms, and Timing Listings. State Listing and Timing
Waveforms can be time-correlated on the same displays.
Timing Waveform Pattern readout of timing waveforms at X or O marker.
Bases Binary, Octal, Decimal, Hexadecimal, ASCII (display only), Two’s Complement,
and User-defined symbols.
Symbols 1,000 maximum. Symbols can be downloaded over RS-232 or HP-IB.
General Information
Supplemental Characteristics(logic analyzer)
1–8

Marker Functions
Time Interval The X and O markers measure the time interval between a point on a
timing waveform and the trigger, two points on the same timing waveform, two points on
different waveforms, or two states (time tagging on).
Delta States (state analyzer only) The X and O markers measure the number of
tagged states between one state and trigger or between two states.
Patterns The X and O markers can be used to locate the nth occurrence of a specified
pattern from trigger, or from the beginning of data. The O marker can also find the nth
occurrence of a pattern from the X marker.
Statistics X and O marker statistics are calculated for repetitive acquisitions. Patterns
must be specified for both markers, and statistics are kept only when both patterns can be
found in an acquisition. Statistics are minimum X to O time, maximum X to O time,
average X to O time, and ratio of valid runs to total runs.
Auxiliary Power
Power through cables 1/3 amp at 5 V maximum per cable, CAT I, Pollution degree 2.
Operating Environment
Temperature Instrument, 0 °C to 55 °C (+32 °F to 131 °F).
Probe lead sets and cables,
0 °C to 65 °C (+32 °F to 149 °F).
Humidity Instrument, probe lead sets, and cables, up to
80% relative humidity at +40 °C(+122 °F).
Altitude To 3067 m (10,000 ft).
Vibration Operating: Random vibration 5 to 500 Hz,
10 minutes per axis, ≈0.3 g (rms).
Non-operating: Random vibration 5 to 500 Hz,
10 minutes per axis, ≈ 2.41 g (rms);
and swept sine resonant search, 5 to 500 Hz,
0.75 g (0-peak), 5 minute resonant dwell
at 4 resonances per axis.
Dimensions
General Information
SupplementalCharacteristics (logicanalyzer)
1–9

Product Regulations
Safety IEC 1010-1:1990+A1 / EN 61010-1:1993
UL3111
CSA-C22.2 No. 1010.1:1993
EMC This product meets the requirement of the European
Communities (EC) EMC Directive 89/336/EEC.
Emissions EN55011/CSIPR 11 (ISM, Group1,Class A equipment)
IEC 555-2 and IEC 555-3
Immunity EN50082-1 Code1Notes2
IEC 801-2 (ESD)4kV CD, 8kV AD 1
IEC 801-3 (Rad.) 3V/m 1
IEC 801-4 (EFT) 1kV 1
1Performance Codes:
1 PASS - Normal operations, no effect.
2 PASS - Temporary degradation, self recoverable.
3 PASS - Temporary degradation, operator intervention required.
4 FAIL - Not recoverable, component damage.
Supplemental Characteristics (oscilloscope)
Vertical (at BNC)
Vertical Sensitivity Range 4 mV/div to 10 V/div in 1-2-4 increments
(1:1 Probe)
DC Offset Range (1:1 Probe)
Vertical Sensitivity Available Offset
4 mV/div to 100 mV/div ±2 V
>100 mV/div to 500 mV/div ±10 V
>500 mV/div to 2.5 V/div ±50 V
>2.5 V/div to 10 V/div ±250 V
Probe Factors Any integer ratio from 1:1 to 1000:1
Maximum Safe Input Voltage 1 MΩ: ±250 V [DC + peak ac (< 10 KHz)], CAT II
50 Ω: ±5 VRMS
Channel-to-Channel Isolation DC to 50 MHz: 40 dB, 50 MHz to 250 MHz: 30 dB
General Information
Supplemental Characteristics(oscilloscope)
1–10