Ibm System/370 User manual

Systems

A Guide

to

the IBM System/370

Model 165

This guide presents hardware, programming systems, and

other pertinent information about the

IBM

System/370

Model 165 that describes its significant new features and

advantages. Its contents are intended

to

acquaint the

reader with the Model 165 and

to

be

of

benefit in

planning for its installation.

First Edition (June 1970)

This guide

is

intended for planning purposes only.

It

will be updated from

time to time to reflect system changes; however, the reader should remember

that

the authoritative sources

of

system information are the Systems Reference

Library (SRL) publications for the Model 165, its associated components and

its programming support. These publications will ftrst reflect such changes.

Copies

of

this and other

IBM

publications can be obtained through

IBM

branch

offIces.

A form has been provided

at

the back

of

this publication for readers' comments.

If

this form has been removed, address comments to:

iBM

Corporation,

Technical Publications Department, 112 East Post Road, White Plains, New York

10601.

PREFACE

Page ofGC20-1730-0

Revised 11/20/70

By

TNL GN20-2277

It

is

assumed

that

the

reader

of

this

document

is

familiar

with

System/360.

The

reader

should

have

a

general

knowledge

of

System/360

architecture,

channels,

I/O

devices,

and

programming

systems

support.

This

guide

highlights

only

those

Model

165

hardware,

I/O,

and

programming

systems

features

that

are

different

from

those

of

System/360

models

and

discusses

their

significance.

Additional,

more

detailed

information

regarding

System/370

Model

165

hardware

and

programming

systems

support

can

be

found

in

the

following

SRL

publications:

IBM

System/370

Model

165

Functional

Characteristics

(GA22-6935)

IBM

System/370

Principles

of

Operation

(GA22-7000)

IBM

System/370

System

Summary

(GA22-7001)

IBM

System/370

I/O

configurator

(GA22-7002)

Component

Summary:

3830

Storage

Control,

3330

Disk

Storage

(GA26-1592)

IBM

System/360

Component

Description:

2835

Storage

Control

and

2305

Fixed

Head

Storage

Module

(GA26-1589)

3211

Printer

and

3811

Control

Unit

Component

Description

(GA24-3543)

IBM

Component

Description:

3803/3420

Magnetic

Tape

Subsystem

(GA32-0020)

Form-Design

Considerations

-

System

Printers

(GA24-3488)

Emulating

the

7070/7074

on

the

IBM

System/370

Model

165

using

OS/360

(GC27-6948)

Emulating

the

709,

7090,

7094,

709411

on

the

IBM

System/370

Model

165

using

OS/360

(GC27-6951)

Emulating

the

7080

on

the

IBM

System/370

Model

165

using

OS/360

(GC27-6952)

IBM

System/360

Operating

System:

Planning

for

the

IBM

3211

Printer,

Data

Management

Macro-Instructions

and

Services

(GC21-5008)

Page

of

GC20-173(}-0

Revised

11/20/70

By

TNL

GN20-2277

CONTENTS

Section

01:

System

Highlights.

• . • .

Section

10:

Architecture

and

System

Components

10:05

Architecture

Design

•.••.•..•.

1

6

10:10

The

Central

Processing

Unit

(CPU)

and

the

system

Console.

8

Central

Processing

Unit.

. . .

•.•

Instruction

and

Execution

Units

••..

Local

Storage

and

Control

Storage

.•.

• • • • 8

Program

States

and

System

Interrupts

• . • • • • 9

9

CPU

Features

• . • • • • • • .

CPU

Cooling.

• • • • •

Motor

Generator

Set.

.

System

Console

• • . • •

10:15

Storage

•.••••••••

Processor

(Main)

Storage

••••

·

11

·

13

·

14

·

15

Processor

Storage

Reconfiguration.

• . • • • • •

..

18

Storage

Ripples.

• • • • •

High-Speed

Buffer

Storage.

• • . • .

10:20

Channels

•••••••••••

General

Description.

• • • • • • • . . • • • •

The

2880

Block

Multiplexer

Channel

•

·

19

24

·

24

·

28

10:25

Block

Multiplexing

Operations

with

Rotational

Position

Sensing

Devices.

• • • • • • • • . • • • • • • . • •

Summary

of

Block

Multiplexing

Operations

with

I/O

Devices.

• • • • • • • • • • • •

••

• • • • •

10:30

Standard

and

Optional

System

Features.

Standard

Features.

•

Optional

Features.

•

Section

20:

I/O

Devices

••••

20:05

I/O

Device

Support.

20:10

3330

Disk

Storage

and

3830

Storage

Control.

20:15

The

2305

Fixed

Head

Storage

Module

and

2835

Storage

Control

Models

1

and

2 • • • • •

Data

Recording

on

the

Model

2

••

Data

Recording

on

the

Modell

••

·

30

• • •

33

34

· .

35

36

·

36

·

41

· .

42

·

43

• • •

45

Effective

Capacity

of

2305

Facilities

••

Rotational

Position

Sensing

and

Multiple

Requesting

••.

47

20:

20

The

3211

Printer

• • • • • • • • • • •

20:25

The

3803/3420

Magnetic

Tape

Subsystem.

·

50

·

51.1

Section

30:

Programming

Systems

Support.

• • .

52

30:05

Trends

in

Data

Processing

and

Programming

Systems..

.

52

30:

10

OS

Support

. • . • • • • . • . .

53

Section

40:05

40:10

40:15

40:20

40:

Emulator

Programs.

•

•••••

Features

Common

to

7000-Series

Emulator

Programs

7070/1074

Emulator

Program

• • • • • •

709/7090/7094/709411

Emulator

Program.

7080

Emulator

Program.

• • . •

Section

50:

Reliability,

Availability,

and

Serviceability

(RAS)

Features

• •

50:05

Introduction

••

t:::'7

• ..J I

·

57

60

•

63

66

69

• 69

50:10

Recovery

Features.

• • . • • • • • • • • . • •

70

Automatic

CPU

Retry.

. • • • •

70

Eec

Validity

Checking

on

Processor

Storage

.

I/O

Operation

Retry.

• . • . • .

Expanded

Machine

Check

Int.errupt

Facilities.

Recovery

Management

Support

(RMS) -

as

MFT

and

M~~

•

MeR

and

CCll

Routines

~

• • • . .

Error

Recovery

Procedures

(ERP'

s).

• •

71

•

73

74

• •

79

•

79

·

81

I

50:15

50:20

Page

of

GC20-1730-0

Revised 11/20/70

By

TNL GN20-2277

Statistical

Data

Recorder

(SDR)

and

Outboard

Recorder

(OBR) • • • • • • • •

Environment

Recording,

Edit,

and

Print

Program

• • • • .

82

(EREP).

• 82

I/O

RMS

(APR

and

OOR).

• • • • • • •

Advanced

Checkpoint/Restart

and

Warm

Repair

Features.

• • • • • • • • • • •

OLTEP

and

OLT's.

• • • • • • •

•••

Processor

Logout

Analysis

Program.

•

• • • . .

82

Start

Facilities

•.

83

·

83

•

84

· 84

System

Test,

Channel

Test,

CPU

Test,

and

Storage

Test

Programs

• • • • • • • • • • • •

Microdiagnostics

•

RAS

summary.

• • •

•

85

·

85

•

85

Section

60:

programming

Systems

Preinstallation

Planning

• •

87

60

:

05

OS

MFT

and

MVT

Transition.

• • • • • • • • • • • 87

Existing

Processing

Programs

and

Job

Control

•

Conversion

to

3330

and

2305

Facilities

• • • •

Conversion

to

the

3803/3420

Magnetic

Tape

Subsystem.

•

88

·

88

•

89

60:10

Planning

Optimal

System

Performance,

Using

Block

Multiplexer

Channels

and

RPS

Devices

•

System

Configuration

and

Generation.

Job

Scheduling

• • • • • • •

Data

Management

Parameters

• • •

90

·

90

•

91

• 92

60

:15

OS

Portability

• • • • • • • • •

60:20

Use

of

Other

Programming

Systems

•

93

•

94

Section

70:

Comparison

Table

of

Hardware

and

OS

Features

for

Index

• • •

FIGURES

10.05.1

10.10.1

10.15.1

10.15.2

10.15.3

10.15.4

10.15.5

10.15.6

20.10.1

20.15.1

20.15.2

20.15.3

20.25.1

40.05.1

50.10.1

50.10.2

50.10.3

50.10.4

System/360

Model

65

and

System/370

Model

165

•••

97

System/370

Model

165

system

elements

• • • • •

Conceptual

flow

of

the

water

cooling

system

in

the

Model

165.

• • • • • • • • • • • • • • • • • •

Model

165

processor

storage

configurations

• •

Model

165

storage

components

and

controls

•••

Conceptual

data

flow

in

the

Model

165

•••••

8K

Buffer

organization

• • • • •

Processor

storage

address

format

for

buffer

reference.

Buffer

address

format.

• • • • • • • • •

The

3330

facility.

• • • • • • • • • • • • • • • •

Top

view

of

a

2305

Model

2

disk

surface

••••••

.105

7

12

16

·

17

20

·

22

·

23

·

23

•

37

• 43

·

45

2305

Model

1

module.

• • • • • • • • • • • • • •

Multiple

requesting

on

the

2305

facility

• • • •

48

Tape

switching

configurations

for

the

3803/3420

Magnetic

Tape

Subsystem.

• • • • • • • •

•••

51.6

Partition

or

region

layout

for

a

7000-series

emulator

program

job

step

• • •

.'

• • • • • • • • • • • • • • • .

58

Data

representation

used

in

Model

165

processor

storage.

72

Data

representation

used

in

Models

65

and

75

and

in

the

Model

165

in

other

than

processor

storage.

. 72

Model

165

fixed

storage

locations.

• •

75

Machine

check

code

-

Model

165

• • • • • • • 77

TABLES

20.10.1

20.10.2

20.10.3

20.15.1

20.15.2

20.15.3

20.25.1

20.25.2

40.10.1

40.10.2

40.15.1

40.15.2

40.20.1

40.20.2

50.10.1

Page

of

GC20-1730-0

Revised

11/20/70

By

TNL GN20-2277

capacity

and

timing

characteristics

of

the

3330

and

2314

facilities

and

the

2321

Data

Cell

Drive.

• • • . 38

3336

and

2316

Disk

Pack

characteristics.

• • • • . 38

Hardware

features

of

3330

and

2314

facilities.

• .

41

Effective

capacity

of

the

2305

Model

2,

the

2305

Modell

and

the

2301

for

various

block

sizes

with

a

25-byte

key.

46

Effective

capacity

of

the

2305

Model

2,

the

2305

Modell

and

the

2301

for

various

block

sizes

when

records

are

written

without

a

key.

• • • • • • • • • • • . • . 46

2305

facilities

and

2301

Drum

storage

characteristics

•.

49

3803

control

unit

configurations

and

capabilities

with

Dual

Density

and

Seven-Track

features

3420,

2420

and

2401

Magnetic

Tape

unit

.

51.5

characteristics.

• • • • • • • • • • • • • • •

51.9

7074

hardware

and

I/O

devices

supported

by

the

Model

165

7074

Emulator

Program.

• • • • • • • • • • • • •

61

7074

I/O

devices

and

features

not

supported

by

the

7074

Emulator

program

for

the

Model

165.

• • •

7094

hardware

and

I/O

devices

supported

by

the

7094

Emulator

program

for

the

Model

165

• . • • • • .

64

7094

I/O

devices

and

features

not

supported

by

the

7094

Emulator

program

for

the

Model

165

• • • • • • • • • • .

65

7080

hardware

and

I/O

devices

supported

by

the

7080

Emulator

program

for

the

Model

165

• • • • • • .

67

7080

I/O

devices

and

features

not

supported

by

the

7080

Emulator

program

for

the

Model

165

• • • • • .

67

Model

165

machine

check

interrupts

• • • • • •

76

I

SECTION

01:

SYSTEM

HIGHLIGHTS

The

System/310

Model

165

is

designed

to

enhance,

extend,

and

broaden

the

successful

concepts

of

System/360

architecture.

It

is

a

high-

speed,

large-scale

growth

system

for

System/360

Model 65

and

15

users

that

provides

significant

price

performance

improvement

without

the

necessity

of

major

reprogrammdng.

The

Model

165

is

a

general

purpose

system

and

offers

high

performance

for

both

commercial

and

scientific

applications.

It

is

compatible

with

the

System/310

Model

155.

Transition

from

System/360

models

to

the

System/310

Model

165

can

be

accomplished

with

a minimum

of

effort

because

most

current

System/360

user

programs,

I/O

devices,

and

programming

systems

are

upward

compatible

with

the

new

system.

Upward

transition

from

a Model

165

to

a Model

195

can

also

be

accomplished.

Additional

capabilities

will

be

added

to

OS

to

support

new

features

of

the

Model

165,

thereby

providing

proven

operating

system

performance

as

well

as

continuity,.

Transition

with

little

or

no

reprogramming

is

also

provided

for

1051/11/111/1080,

1010/1014,

and

109/1090/1094/109411

users

who

are

presently

emulating

on

System/360.

Emulators

that

operate

under

OS

control

on

the

Model

165

are

provided

for

these

systems.

Highlights

of

the

Model

165

are

as

follows.

• Upward

compatibility

with

most

System/360

architecture

and

programming

has

been

maintained.

•

Internal

performance

is

approximately

two

to

five

times

that

of

the

Model

65.

•

CPU

features

of

the

System/310

Model

165

are

as

follows:

The Model

165

standard

instruction

set

includes

new

general

purpose

instructions

in

addition

to

the

powerful

System/360

instruction

set.

These

instructions

enhance

decimal

arithmetic

performance,

eliminate

the

need

for

multiple

move

or

compare

instructions

or

move

subroutines,

and

facilitate

record

blocking

and

deblocking,

field

padding,

and

storage

clearing.

Extended

precision

floating

point

is

a

standard

feature

to

provide

precision

of

up

to

28

hexadecimal

digits,

equal

to

approximately

34

decimal

digits.

A

high-speed

multiply

feature

is

available

to

provide

faster

execution

of

binary

and

floating-point

arithmetic

operations.

Execution

speed

increases

by

a

factor

of

2

to

3.

An

interval

timer

of

3.33

ms

resolution

to

improve

job

accounting

accuracy

is

standard.

A

16.6

ms

resolution

timer

is

standard

on

the

Model

65.

A

time

of

day

clock

is

included

to

provide

more

accurate

time

of

day

values

than

the

interval

timer.

It

has

a 1

microsecond

resolution.

Separate

instruction

and

execution

units

are

implemented

that

provide

overlap

of

instruction

fetching,

instruction

decoding,

operand

fetching"

and

instruction

execution

to

increase

internal

performance.

1

2

CPU

retry

of

most

failing

CPU

hardware

operations

is

handled

automatically

by

the

hardware

without

programming

assistance.

Writable

control

storage

(WCS)

is

included

in

addition

to

read-

only

storage

(ROS)

to

contain

new

Model

165

instructions,

emulator

microcode,

and

CPU

diagnostics.

•

Relocatable

emulators

are

provided

that

operate

under

OS

control.

Concurrent

execution

of

System/370

programs

with

7000-series

programs

is

supported.

A

7080,

a

7070/7074,

and

a

709/7090/7094/709411

emulator

are

available

on

a

mutually

exclusive

basis.

• A

free-standing

3066

System

Console

is

required.

Its

features

are:

A

buffered

cathode

ray

tube

and

an

alphameric

keyboard

for

rapid

operator/system

communication

An

indicator

viewer

to

display

system

status

A

system

activity

monitor

to

provide,

via

the

system

activity

meter,

visual

display

of

average

system

activity

A

microfiche

document

viewer

for

CE

use

A

processor

storage

configuration

plugboard

A

device

for

loading

WCS

and

diagnostic

routines

•

Channel

features

of

the

Model

165

are

as

follows:

2870

Multiplexer

Channels,

2860

Selector

Channels,

and

the

new

2880

Block

Multiplexer

Channels

can

be

attached

-

for

a

total

of

seven

addressable

channels.

A

single

2880

channel

can

operate

at

a 3

MB

rate

with

attachment

of

an

optional

feature.

The

Extended

Channels

feature

permits

a

Model

165

to

have

up

to

twelve

addressable

channels,

which

can

support

an

aggregate

channel

data

rate

in

excess

of

nine

megabytes

per

second.

The

2880

Block

Multiplexer

Channel

is

a

superset

of

the

2860

Selector

Channel.

When

used

in

conjunction

with

rotational

position

sensing

devices,

it

can

increase

total

system

throughput

by

permitting

more

data

to

enter

and

leave

the

system

in

a

given

time

period

than

can

the

2860.

A

single

2880

channel

can

support

interleaved,

concurrent

execution

of

multiple

high-speed

I/O

operations.

Channel

retry

data

is

provided

after

channel

errors

so

that

error

recovery

routines

can

retry

I/O

operations.

•

storage

features

offered

by

the

Model

165

are

as

follows:

A

two-level

memory

system,

consisting

of

fast,

large-size

processor

(main)

storage

used

as

backing

storage

for

a

smaller,

very

high-

speed

buffer

storage,

is

implemented.

The

CPU

works

mostly

with

the

buffer

so

that

the

effective

access

time

for

data

is

reduced

to

a

fraction

of

the

processor

storage

cycle

time.

8K

or

16K

bytes

of

SO-nanosecond

monolithic

buffer

storage

is

available

(SK

is

standard).

The

CPU

can

initiate

a

request

for

eight

bytes

from

the

buffer

every

80

nanoseconds.

P,;ge

of

r.c20-1730-0

Revised i

1/20/70

By

TNL GN20-2277

512K

to

3072K

of

four-way,

doubleword

int€rleaved,

two-

microsecond

processor

storage

is

available

-

three

times

the

maximum

available

on

the

Model

65.

Byte

boundary

alignment

is

permitted

for

the

operands

of

non-

privileged

instructions

to

eliminate

the

necessity

of

adding

padding

bytes

within

records

or

to

blocked

records

for

the

purpose

of

aligning

fixed

or

floating-point

data.

Error

checking

and

cor~ection

(ECC>

hardware

that

automatically

corrects

all

single-bit

processor

storage

errors

and

detects

all

double-bit

and

most

multiple-bit

errors

is

standard

•

I/O

devices

for

the

Model

165

are

as

follows:

Most

currently

announced

I/O

devices

for

System/360

Models

65

and

above

can

be

attached.

The

new

3330

facility

is

available

for

attachment

to

2880

channels.

It

offers

significantly

faster

seeks

and

more

than

twice

the

data

rate

of

the

2314

facility,

more

than

three

times

the

capacity

of

the

2314,

and

automatic

error

correction

features.

The

new

rotational

position

sensing

and

multiple

requesting

capabilities

announced

for

the

2305

facility

are

standard.

The

3330

has

an

806

KB

data

transfer

rate,

average

seek

time

of

30

ms,

and

full

rotation

time

of

16.7

ms.

Up

to

800

million

bytes

can

be

contained

on

an

eight

drive

facility.

The

2305

facility

Models

1

and

2

can

be

connected

to

2880

channels

to

provide

significantly

faster

data

transfer

operations.

The

Model

1

has

a 3

megabyte

data

rate,

a

maximum

module

capacity

of

5.4

million

bytes,

and

average

access

time

of

2.5

ms.

The

Model

2

has

a

1.5

megabyte

data

rate,

a

maximum

module

capacity

of

11.2

million

bytes,

and

average

access

time

of

5

ros.

The

new

high-speed

3211

Printer

with

a

tapeless

carriage

and

an

alphameric

print

speed

of

2000

lines

per

minute

is

available.

The

tapeless

carriage

decreases

operator

intervention

by

eliminating

carriage

tape

loading

and

unloading.

The

new

3803/3420

Magnetic

Tape

Subsystem

is

attachable.

Models

3,

5,

and

7

of

the

3420

Magnetic

Tape

Unit,

with

data

rates

of

120

KB,

200

KB,

and

320

KB,

respectively,

at

l600-BPI

recording

density,

are

provided.

Phase-encoded

recording,

which

automatically

corrects

all

single-bit

read

errors

in-flight,

is

used.

This

new

tape

subsystem

offers

improved

price

performance;

Dual

Density

and

Seven-Track

features

for

compatibility

with,

and

conversion

of,

2400-series

tape

volumes;

greatly

reduced

operator

handling

through

implementation

of

such

features

as

automatic

tape

threading

and

cartridge

loading;

lower

cost

tape

switching

than

is

currently

pro-

vided;

and

enhanced

reliabilty,

availability,

and

serviceability

features

.

•

Extensive

hardware

and

programming

systems

error

recovery

and

repair

features

are

provided

to

improve

system

reliability,

availability,

and

serviceability

•

Compact

physical

design

reduces

Model

165

CPU

and

processor

storage

space

requirements.

The

Model

165

CPU

has

three

times

the

number

of

circuits

as

a

Model

65,

in

excess

of

75,000

versus

25,000,

yet

a 512K

or

1024K

Model

165

requires

the

same

amount

of

space

as

a

512K

Model

65.

As

the

highlights

indicate,

Model

65

and

75

users

have

a

broader

range

of

Model

165

configurations

to

choose

from

than

before

when

tailoring

a

growth

system

with

improved

throughput

and

expanded

3

capabilities.

Specifically,

the

Model

165

offers

the

following

advantages

over

Models

65

and

75:

Larger

Processor

(Main)

Storage

Sizes

Storage

sizes

of

512K,

102QK,

1536K,

2048K,

and

3072K

are

provided.

The

Model

65

offers

a maximum

of

1024K.

Larger

Model

165

storage

sizes

are

available

at

smaller

cost

increments,

and

additional

storage

can

contribute

significantly

to

system

performance

and

capabilities.

The

addition

of

more

processor

storage

provides

the

Model

165

user

with

the

ability

to:

•

Execute

more

jobs

concurrently,

including

new

application

and

integrated

7000-series

emulator

jobs

•

Add

and

expand

applications,

such

as

graphics,

teleprocessing,

time

sharing,

remote

job

entry,

and

data

based,

that

require

large

amounts

of

storage

•

Use

higher

level

language

translators

and

linkage

editors

that

provide

more

functions

and

execute

faster

•

Execute

larger

processing

programs

without

the

necessity

of

overlay

structures

•

Allocate

more

processor

storage

to

language

translators

and

sorts

to

improve

their

execution

speed

•

Use

more

and

larger

I/O

buffers

to

speed

up

input/output

operations

and

optimize

use

of

direct

access

storage

space

•

Include

system

generation

options

that

improve

control

program

performance

and

support

additional

functions

Expanded

Channel

Capabilities

The

fast

internal

performance

of

the

Model

165,

together

with

expanded

use

of

multiprogramming,

requires

that

more

data

be

available

faster.

The

Model

165

offers

more

and

faster

channels

than

the

Model

65,

twelve

instead

of

seven,

and

1.5

MB

and

3.0

MB

data

rates

on

the

2880

in

addition

to

a

1.3

MB

rate

on

the

2860.

The

channel

features

of

the

Model

165

provide:

• A

significantly

higher

attainable

aggregate

data

rate

than

provided

by

the

Model

65

to

balance

the

high

performance

capabilities

of

the

Model

165

cpu. A

twelve-channel

Model

165

system

can

support

I/O

conf~gurations

with

an

aggregate

data

rate

in

excess

of

9-MB.

•

Attachment

of

high-speed

direct

access

devices,

such

as

3330

and

2305

facilities,

that

will

increase

I/O

throug:1put

•

Channel

throughput

increase

capabilities

via

use

of

block

multiplexing

with

rotational

position

sensing

to

improve

effective

data

transfer

rates

Faster

I/O

Devices

with

Increased

Data

Capacity

The

3330

and

the

2305

facilities

offer

significantly

faster

data

access

than

the

2314

facility

and

2301

Drum

Storage

because

of

higher

data

transfer

rates,

faster

rotation,

and

new

features.

Rotational

position

sensing

and

multiple

requesting

used

with

block

multiplexing

4

I

Page

of

GC20-173o-0

Revised

7/14/70

By

TNL GN20-2227

can

improve

I/O

throughput

by

making

more

efficient

use

of

channel

time.

These

direct

access

facilities

also

offer

higher

availability

through

use

of

advanced

hardware-only

and

program-assisted

error

correction

features.

The

3330

facility

provides.

high

capacity

and

fast

access

for

less

cost

per

bit.

It

is

a

growth

device

for

the

2314

facility

and

the

2321

Data

Cell

Drive

that

offers

increased

price

performance.

The

3330

facility

is

designed

to

be

used

in

every

area

in

which

direct

access

storage

is

needed,

for

example:

• As a

system

residence

device

and

for

program

library

storage

•

In

teleprocessing

applications

for

message

queuing

and

residence

of

online

applications

data

•

In

online,

data-based

applications,

such

as

management

information

systems,

airline

reservat.ions,

etc.

•

In

time-sharing

(or

interactive)

environments

as

a

swap

device

and

for

online

work

storage

(for

program

and

data

residence)

• As

high-speed

work

storage

for

sorting,

assembling,

and

link

editing

•

For

residence

of

data

indexes,

such

as

for

ISAM

data

sets

The

2305

facilities

offer

larger

capacity

and

faster

access

than

the

2301

drum.

For

Model

165

users,

the

2305

facilities

can

contribute

significantly

to

system

throughput

improvements

when

used:

• As

system

residence

devices

•

In

time-sharing

environments,

as

a

swap

device

and

for

program

and

data

residence

•

As

high-speed

work

storage

and

for

residence

of

data

indexes

SUMMARY

The

combination

of

new

and

improved

hardware

and

input/output

facilities,

enhanced

operating

systems

support,

integrated

emulation,

and

increased

system

availability

provided

by

the

Model

165

offers

Model

65

and

75

users

expanded

computing

capabilities

without

the

necessity

of

a

large

conversion

effort.

Little

or

no

time

need

be

spent

modifying

operational

System/360

code

or

7000-series

programs

currently

being

emulated.

Existing

CPU-bound

programs

can

execute

faster

because

of

the

increased

internal

performance

of

the

Model

165,

while

I/O-bound

programs

can

benefit

from

the

use

of

more

storage,

more

channels,

faster

I/O

devices,

and

block

multiplexing.

The

increased

power

and

new

functions

of

the

Model

165

provide

the

base

for

expanded

applications

growth

and

penetration

of

previously

marginal

application

areas.

The

increased

price

performance

of

the

Model

165

offers

the

user

the

opportunity

to

widen

his

data

processing

base

for

comparatively

less

cost

and

the

Model

165

can

be

an

integral

part

of

a

growth

plan

to

the

higher

performance

Model

195.

5

SECTION

10:

ARCHITECTURE

AND

SYSTEM

COMPONENTS

10:05

ARCHITECTURE DESIGN

The

basic

design

objectives

embodied

in

System/370

Model

165

architecture

provide

System/360

Model

65

and

75

users

and

7000-series

emulator

users

with

a

growth

system

that

incorporates

improvements

and

additions

to

System/360

architecture.

The

Model

165

provides

new

system

capabilities,

performance

improvements,

and

features

to

increase

system

reliability,

availability,

and

serviceability.

This

has

been

achieved

under

the

following

conditions:

•

System/370

Model

165

architecture

is

upward

compatible

with

that

of

System/360

models

so

that

most

user

programs

written

for

system/360

will

run

efficiently

on

the

Model

165

without

modification.

•

Programming

systems

support

for

the

Model

165

is

based

on

that

provided

for

System/360

models,

namely

on

OS

MFT

and

MVT.

•

Most

currently

announced

System/360

I/O

devices

will

operate

on

the

Model

165.

(See

Section

20:05

for

a

list

of

the

I/O

devices

that

cannot

be

included

in

a

Model

165

configuration.)

•

The

open-ended

design

characteristic

of

System/360

has

been

preserved

and

extended

in

System/370.

As

a

result

of

the

architecture

design

criteria

used

for

this

new

system,

all

programs

written

for

System/360

(Models

25

and

up)

will

operate

on

a

System/370

Model

165

with

a

comparable

hardware

configuration,

with

the

following

exceptions:

1.

Time-dependent

programs

2.

Programs

using

machine-dependent

data

such

as

that

which

is

logged

in

the

machine-dependent

logout

area.

(OS SER

and

MCH

and

DOS

MCRR

error-logging

routines

for

System/360

models

will

not

execute

correctly.)

3.

Programs

that

use

the

ASCII

mode

bit

in

the

PSW

4.

Programs

that

depend

on

the

nonusable

lower

processor

storage

area

being

smaller

than

1512

bytes.

This

area

can

be

reduced

to

512

bytes

by

moving

the

CPU

logout

area.

(See

Section

50.)

5.

Programs

deliberately

written

to

cause

certain

program

checks

6.

Programs

that

depend

on

devices

or

architecture

not

implemented

in

the

Model

165,

for

example,

the

native

file

of

the

Model

44,

relocation

implemented

in

the

Model

67,

etc.

7.

Programs

that

use

model-dependent

operations

of

the

System/370

Model

165

that

are

not

necessarily

compatible

with

the

same

operations

on

System/360

models

Note

that

these

are

the

same

types

of

restrictions

that

exist

for

compatibility

among

System/360

models.

The

major

elements

of

the

Model

165

computing

system

are

illustrated

in

Figure

10.05.1.

Each

component

and

its

new

features

are

discussed

6

in

the

subsections

that

follow.

Programming

systems

support

of

these

features

is

covered

in

Section

30.

Reliability,

availability,

and

serviceability

(RAS)

hardware

features

are

mentioned

only

briefly.

A

full

discussion

of

both

hardware

and

programming

systems

RAS

facilities

is

contained

in

Section

50.

Multiplexer

Channel

2870

#2

Multiplexer

Channel

2870

# 1

Selector

Channel

2860

Selector

Channel

2860

Block Multiplexer

Channel

2880

Block Multiplexer

Channel

2880

Block

Multiplexer

Channel

2880

Note:

Not

indicative

of

layout

or

scale.

Processor

Storage

Model

KJ

Processor

Storage

Models

JI and K

~

Power and Coolant

Distribution

Unit

Processor Processor

Storage Storage

Models I and J Models I and J

Central Processing

Unit

CRT and

Keyboard

t

Console

Unit

with

30'

cable

Figure

10.05.1.

System/370

Model

165

system

elements

Processor

Storage

Model

KJ

Processor

Storage

Models

JI and K

I

Document Viewer,

Magnetic disk

cartridge device,

and Indicator

Viewer

7

10:10

THE

CENTRAL

PROCESSING UNIT (CPU)

AND

THE

SYSTEM

CONSOLE

CENTRAL

PROCESSING UNIT

The

CPU

contains

all

the

elements

necessary

to

decode

and

execute

the

instructions

in

the

System/370

Model

165

instruction

set

and,

optionally,

those

in

the

hardware

compatibility

feature

required

by

one

of

the

three

7000-series

emulator

programs.

The

CPU

has

an

80-nanosecond

cycle

time

and

an

8-byte-wide

data

path.

Extensive

parity

checking

is

performed

in

the

CPU

to

insure

the

validity

of

the

data

being

used.

All

data

transfer,

logical,

and

arithmetic

operations

are

checked.

Automatic

hardware

retry

of

most

failing

CPU

operations,

without

programming

assistance,

is

provided

as

an

availability

feature

and

is

discussed

in

the

RAS

section.

Among

the

major

elements

in

the

CPU

are

the

instruction

unit,

the

execution

unit,

local

storage,

and

control

storage.

Instruction

and

Execution

Units

The

faster

internal

performance

of

the

Model

165

is

due

in

part

to

the

use

of

more

concurrence

in

CPU

operations

than

is

implemented

in

the

Model

65.

The

Model

165

CPU

contains

an

instruction

unit

and

an

execution

unit

that

overlap

instruction

fetching

and

preparation

with

instruction

execution.

The

Model

165

instruction

unit

is

controlled

by

logic

circuits

and

can

process

several

instructions

concurrently

while

the

execution

unit

is

executing

a

single

instruction.

The

instruction

unit

prefetches

instructions

(maintaining

them

in

sequence),

decodes

instructions,

calculates

addresses,

prefetches

instruction

operands,

and

makes

estimates

of

the

success

of

conditional

branches.

When a

conditional

branch

is

encountered,

the

instructions

immediately

following

the

branch

and

those

located

at

the

branch

address

are

prefetched

and

placed

in

separate

instruction

buffers

within

the

instruction

unit.

TWo

16-byte

instruction

buffers

are

used.

This

insures

the

availability

of

prefetched

instructions

whether

the

branch

is

taken

or

not.

The

execution

unit

is

microprogram

controlled

and

can

execute

one

instruction

at

a

time.

It

has

the

capability

of

processing

a

new

instruction

every

cycle.

Emphasis

is

placed

on

optimizing

fixed

binary

and

floating-point

arithmetic

operations.

A

64-bit

parallel

adder

is

used

to

perform

binary

and

floating-point

arithmetic,

while

an

8-

bit

serial

adder

is

used

in

the

execution

of

packed

decimal

arithmetic.

An

imprecise

interrupt

occurs

on

a

Model

165

only

if

an

attempt

is

made

to

store

data

at

an

invalid

storage

address

or

at

a

storage-

protected

location.

Local

Storage

and

Control

Storage

Local

storage

contains

the

general

purpose

and

floating-point

registers

and

has

a

read

or

write

cycle

time

of

80

nanoseconds.

It

can

be

accessed

by

four

sources

and

written

into

from

one

source

simultaneously.

Model

165

control

storage

consists

of

a

capacitor

read-only

storage

(ROS)

and

a

monolithic

writable

control

storage

eWCS),

both

of

which

have

an

80-nanosecond

cycle

time.

ROS

and

WCS

contain

all

required

microcode

for

a

specific

system

configuration.

ROS

contains

the

microcode

necessary

to

execute

the

majority

of

the

Model

165

instructions

and

some

specialized

routines.

WCS

contains

the

8

microprogramming

required

to

handle

the

balance

of

the

instruction

set

for

the

Model

165

and

other

optional

features,

such

as

a

1000-

series

compatibility

feature.

WCS

is

also

used

to

house

diagnostic

routines.

The

use

of

some

writable

control

storage

in

the

Model

165

in

addition

to

ROS

allows

nonresident

diagnostics

to

overlay

each

other.

Thus

more

extensive

diagnostics

can

be

provided

without

the

necessity

of

adding

more

control

storage.

During

a

power-on

sequence,

WCS

is

automatically

loaded

with

system

microcode

from

a

removable

magnetic

disk

cartridge

contained

on

a

device

in

the

console

unit.

The

magnetic

disk

cartridges

sent

to

an

installation

will

be

tailored

to

include

the

microcode

required

by

the

optional

features

included

in

the

system

configuration.

Program

States

and

System

Interrupts

The

program

states

in

which

the

Model

165

is

operating

are

reflected

in

the

current

program

status

word

(PSW)

and

in

new

CPU

status

indicators,

called

control

registers,

located

in

the

CPU. Up

to

16

control

registers,

0-15,

can

be

addressed;

however,

only

4

are

implemented

in

the

Model

165.

They

are

program

addressable

when

the

CPU

is

in

the

supervisor

state.

A

control

register

can

be

set

with

the

new

LOAD

CONTROL

instruction,

and

its

contents

can

be

placed

in

processor

storage

with

the

STORE

CONTROL

instruction.

Additional

status

indicators

contained

in

control

registers

are

required

in

order

to

support

new

system

functions.

The

contents,

layout,

and

function

of

fixed

locations

0-121

in

System/310

models

are

identical

to

these

locations

in

Systern/360

models

with

one

exception.

Bit

12

in

the

PSW,

which

sets

EBCDIC

or

ASCII

mode

in

System/360

models,

is

not

used

for

this

purpose

in

the

Model

165.

(It

must

be

set

to

zero.)

ASCII

mode

is

not

implemented

in

the

Model

165,

nor

was

the

mode

bit

supported

by

IBM

programming

systems

for

Systern/360

models,

since

the

expectation

that

System/360

ASCII-8

would

become

the

ASCII

standard

has

not

been

borne

out.

The

implementation

of

the

machine

check

level

of

interruption

in

the

Model

165

has

been

altered

considerably

from

its

implementation

in

Models

65

and

15

in

order

to

enhance

system

availability

(see

Section

50).

However,

the

other

four

interrupt

levels

operate

in

the

same

manner

on

the

Model

165

as

on

Models

65

and

15.

CPU

Features

Significant

features

of

the

Model

165

CPU

are

the

following:

Expanded

Instruction

Set

The

standard

instruction

set

for

the

Systern/310

Model

165

is

a

superset

of

that

provided

for

System/360

Models

65

and

15.

It

consists

of

the

System/360

instruction

set

plus

new

instructions

that

support

System/310

architecture

and

provide

additional

functions.

The

Model

165

standard

instruction

set

includes

all

general

purpose

and

I/O

instructions

and

all

binary,

decimal,

floating-point,

and

extended

precision

floating-point

arithmetic

instructions.

Storage

protect

and

time

of

day

clock

instructions

are

also

standard.

The

new

STORE

CPU

ID

instruction

permits

a

program

to

determine

the

model

upon

which

it

is

operating

and

provides

the

system

serial

number.

The

new

STORE

CHANNEL

ID

instruction

can

be

used

to

identify

the

types

of

channels

present

in

the

system.

Other

new

standard

instructions

are:

9

•

Extended

Precision

Floating

Point

Precision

of

up

to

28

hexadecimal

digits,

approximately

equal

to

34

decimal

digits,

is

provided

by

the

extended

precision

data

format.

Extended

precision

is

achieved

by

using

two

doublewords

(16

bytes)

to

represent

an

extended

precision

floating-point

number

instead

of

using

one

doubleword

as

is

done

in

long

form

representation.

Fourteen

hexadecimal

digits,

or

up

to

17

decimal

digits,

of

precision

is

provided

by

the

long

floating-point

format.

Seven

floating-point

instructions

are

included

in

the

extended

preciSion

feature.

They

provide

addition,

subtraction,

and

multiplication

operations

for

extended

precision

data,

using

a

pair

of

floating-point

registers,

and

the

ability

to

round

from

long

to

short

form

or

from

extended

to

long

form.

•

General

Purpose

Instructions

Six

general

purpose

instructions,

which

will

be

of

benefit

to

both

control

and

processing

program

performance,

have

been

added

to

the

Model

165

standard

instruction

set.

SHIFT

AND

ROUND

DECIMAL,

using

a

single

instruction,

provides

right

or

left

shifting

of

packed

decimal

data.

This

instruction

can

save

6

to

18

bytes

of

instruction

storage

and

instruction

execution

time

for

each

decimal

shift

and

round

operation

performed

in

commercial

processing.

MOVE

LONG

provides

for

the

movement

of

up

to

16

million

bytes

from

one

location

in

storage

to

another

with

a

single

instruction,

thereby

removing

the

current

limitation

of

256

bytes

per

move.

This

instruction

can

eliminate

the

necessity

of

multiple

move

instructions

or

the

inclusion

of

move

subroutines.

The

format

and

operation

of

MOVE

LONG

facilitates

efficient

record

blocking

and

deblocking,

field

padding,

and

storage

clearing,

operations

frequently

performed

in

commercial

processing.

COMPARE

LOGICAL

LONG

can

be

used

to

compare

logically

two

fields

of

up

to

16

million

bytes

in

length,

thus

removing

the

current

256-byte

limit

on

byte

compares.

In

addition,

when

an

unequal

compare

occurs,

the

two

characters

that

caused

the

inequality

are

identified.

The

MOVE

LONG

and

COMPARE

LOGICAL

LONG

instructions

are

interruptable.

Thus,

when

an

I/O

operation

terminates

during

their

execution,

the

interrupt

can

be

taken,

and

the

channel

is

not

held

up

awaiting

termination

of

what

might

be

a

lengthy

move

or

compare.

COMPARE

LOGICAL, STORE,

and

INSERT

CHARACTERS

UNDER

MASK

instructions

provide

byte

addressability

within

the

general

purpose

registers

and

permit

nonword-size

data

that

is

not

on

a

word

boundary

to

be

compared

to

data

in

a

register,

loaded

into

a

register~

and

stored

from

a

register.

These

three

instructions

can

be

of

most

benefit

to

control

program

programmers,

to

compiler

writers,

and

to

others

who

must

manipulate

processor

storage

addresses.

High-Speed

Multiply

Feature

(Optional)

This

feature

substantially

increases

the

internal

performance

of

fixed-

and

floating-point

multiply

operations.

With

use

of

this

feature

a

long

precision

floating-point

multiply

operation

improves

from

1.81

to

.61

microseconds.

A

fixed-point

mUltiply

operation

improves

from

.78

to

.42

microseconds.

10

Page

of

GC20-1730-0

Revised

7/14/70

By

TNL

GN20-2227

Architecture

Implementation

Alterations

Two

alterations

have

been

made

to

the

system

action

taken

on

a

Model

165

during

the

execution

of

certain

instructions

common

to

both

System/310

and

System/360

models.

The

first

involves

all

instructions

that

check

the

validity

of

operands

involved

in

packed

decimal

operations.

On

the

Model

165.

an

invalid

sign

in

an

operand

causes

the

instruction

to

be

suppressed

(never

executed)

rather

than

terminated

during

execution

as

is

done

on

System/360

models.

Suppression,

rather

than

termination,

of

an

instruction

when

an

invalid

sign

occurs

insures

that

the

data

fields

involved

remain

unchanged.

Therefore,

when

a

program

check

occurs,

a

routine

can

be

executed

that

inspects

the

field

that

has

the

invalid

sign.

For

example,

when

an

invalid

sign

results

from

packing

an

entirely

blank

field,

the

sign

can

be

corrected

by

programming.

and

transaction

deletion

or

program

termination

is

avoided.

The

second

alteration

concerns

the

recognition

of

a

storage

protection

exception

during

the

execution

of

an

EDIT

or

an

EDIT

AND

MARK

instruction.

On a

Model

165

a

protection

exception

always

occurs

when

a

pattern

character

is

fetched

from

a

location

protected

for

storing

but

remains

unchanged

during

the

edit

operation.

This

change

eliminates

unpredictable

system

operation

during

editing

on

a

Model

165.

The

occurrence

of

a

protection

exception

for

the

situation

described

is

model-dependent

for

System/360

models.

Interval

Timer

(Standard)

The

interval

timer

in

decimal

location

80

in

fixed

processor

storage

of

a

Model

165

has

a

resolution

of

3.33

ms

instead

of

the

16.6

ms

resolution

(with

60-cycle

power)

implemented

for

the

standard

timer

on

the

Model

65.

Its

maximum

time

period

remains

15.5

hours.

The

higher

resolution

of

this

interval

timer

will

eliminate

many

of

the

problems

encountered

in

accounting

routine

accuracy

caused

by

task

execution

durations

that

are

less

than

the

16.6

ms

resolution.

Time

of

Day

Clock

(Standard)

This

new

clock

is

a

binary

counter

of

52

bits

with

a

cycle

of

approximately

142

years.

It

is

updated

every

microsecond.

Two

new

instructions

(SET

CLOCK

and

STORE CLOCK)

are

provided

to

set

the

time

and

to

request

that

the

current

time

be

stored

in

a

specified

double-

word

of

processor

storage.

The

time

can

be

set

only

when

the

CPU

is

in

supervisor

state

and

only

when

the

clock

security

switch

on

the

system

console

panel

is

in

the

enable

set

position.

The

time

of

day

clock

can

be

used

for

more

accurate

time

stamping

than

the

interval

timer.

Accurate

time

of

day

can

be

maintained

because

during

normal

operations

the

clock

stops

only

when

CPU

power

is

turned

off.

The

interval

timer

cannot

be

as

accurate

as

the

clock

for

time

of

day

mainte-

nance

because

it

is

not

updated

when

the

system

is

in

the

stopped

state,

and

its

updating

may

be

omitted

under

certain

conditions

of

excessive

sys-

tem

activity.

The

lS.S-hour

cycle

time

of

the

interval

timer

is

also

a

re-

striction.

The

time

of

day

clock

better

answers

the

timing

needs

of

tele-

processing

and

real-time

applications.

£PU

Cooling

The

heat

generated

by

the

logic

boards

in

the

Model

165

CPU

and

its

associated

power

frames

is

removed

by

forced

air

and

a

closed-loop

water

circulation

system.

Use

of

a

liquid

coolant

in

addition

to

air

is

required

because

of

the

amount

of

heat

generated

by

the

densely

packed

circuits

in

the

CPU.

11

The

user

must

supply

30

gallons

of

cooled

water

per

minute

(45

0

to

60

0

F.>

to

the

coolant

distribution

unit

(CDU>,

which

is

housed

in

a

stand-alone

frame

that

also

contains

power

and

the

power

distribution

unit.

Water

is

supplied

to

the

CDU

in

pipes

under

the

raised

floor.

The

chilled

water

entering

the

CDU

is

used

to

control

the

temperature

of

the

internal

water

that

passes

through

the

cpu.

That

is,

the

user-supplied

water

does

not

enter

the

closed-loop

system

of

the

cpu.

(See

Figure

10.10.1.>

The

CDU

houses

the

necessary

controls

to

maintain

the

proper

temperature

in

the

closed-loop

system.

The

user

must

supply

the

controls

to

maintain

the

temperature

of

the

chilled

water

supplied

to

the

CDU.

User-supplied

water

(45°-

60°F)

Coolant Distribution

Unit

CPU

Figure

10.10.1.

Conceptual

flow

of

the

water

cooling

system

in

the

Model

165

The

use

of

water

as

the

cooling

liquid

offers

several

advantages.

First,

it

is

readily

available.

The

chilled

water

normally

supplied

for

air

conditioning

is

acceptable.

Second,

water

offers

safety

features.

Low

pressure

is

required

and

the

cooling

system

can

operate

at

room

temperature,

thereby

eliminating

problems

with

condensation.

Last,

a

simplified

circulation

system

suffices,

with

relatively

few

moving

parts

and

less

exposure

to

leaks.

Pipe

components

within

the

cpu

are

separated

easily,

and

the

valved

connections

close

off

automatically

to

prevent

water

from

escaping.

12

Physical

planning

for

Model

165

installation

should

insure

that

arrangements

are

made

to

provide

the

required

water.

(See

System/370

Installation

Information,

Physical

Planning,

GA22-6971

for

more

details,.

)

Motor

Generator

Set

The

motor

generator

(MG)

set

is

the

converter

unit

that

provides

the

power

required

by

the

Model

165

CPU.

It

takes

60

Hz

(cycle)

power

from

the

building

electrical

distribution

system,

converts

it

to

415

Hz

power,

and

supplies

it

to

the

cPU.

Unlike

the

MG

sets

provided

for

the

7000-series,

which

were

small

enough

to

be

housed

within

the

covers

of

the

system

itself,

the

MG

set

(including

the

required

starter)

for

the

Model

165

is

a

stand-alone

unit

approximately

six

feet

long,

weighing

3000

lbs.

(See

system/370

Installation

Information,.

Physical

Planning

for

more

details

concerning

MG

set

size

and

installation

requirements.)

The

MG

set

should

be

ordered

at

the

same

time

as

the

Model

165,

with

delivery

up

to

two

months

prior

to

system

installation.

While

IBM

does

not

manufacture

MG

sets.

a

procedure

is

established

for

ordering

the

required

MG

set

through

IBM.

3066

SYSTEM

CONSOLE

A

stand-alone

system

console

unit,.

which

can

be

located

up

to

approximately

25

feet

away

from

the

CPU.

is

required

for

the

Model

165.

This

unit

contains

the

system

control

panel

(buttons,

switches,

lights,

etc.,

required

for

system

operation),

as

well

as

standard

advanced

console

features:

a

cathode

ray

tube

and

keyboard,

a

microfiche

indicator

viewer,

a

microfiche

document

viewer,

a

processor

storage

configuration

plugboard.

a

system

activity

monitor,

and

a

device

for

loading

microcode

and

diagnostics.

Certain

of

these

features

are

included

to

enable

the

customer

engineer

to

detect

CPU

malfunctions

more

rapidly

than

would

otherwise

be

possible.

Installation

of

the

optional

Remote

Operator

Console

Panel

Attachment

feature

on

a

Model

165

permits

duplication

of

the

operator

control

panel

section

of

the

system

console

unit

on

a

2150

Console

or

a

2250

Display

Unit

Model

1.

The

cathode

ray

tube

(CRT)

unit

provided

contains

a

4K

buffer.

In

normal

mode,

the

CRT

and

alphameric

keyboard

are

designed

to

be

used

as

the

operating

system

operator's

console

to

provide

the

rapid

message

display

required

by

large

systems

like

the

Model

165.

Two

operator

warning

indicators

are

provided.

A

switch

setting

determines

whether

a

visual

indicator

or

an

audible

alarm

with

volume

control

is

used.

In

CE

mode.

the

CRT

and

a

set

of

16

data

keys

can

be

used

to

display

and

manually

alter

processor

storage,

the

general

purpose

and

floating-point

registers,

the

channel

buffers,

or

the

CPU

buffer

address

array.

Data

is

entered

in

hexadecimal

by

means

of

the

data

keys,

each

of

which

represents

a

hexadecimal

digit.

The

microfiche

indicator

viewer

is

included

in

the

console

unit

for

display

of

status

and

control

indications.

The

display

utilizes

a

-framing-

concept:

the

customer

engineer

uses

a

-frame

selection

switch-

to

select

anyone

of

ten

images.

Each

image

consists

of

up

to

240

indicators"

the

current

value

of

which

is

then

displayed

in

incandescent

lights

along

with

the

appropriate

microfiche

image

that

labels

the

lights.

In

this

way

up

to

2400

status

and

control

triggers

may

be

displayed,

yet

the

console

requires

only

240

incandescent

lights.

13

IBM System/370 User manual

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