ICP DAS USA PIO-D64 User manual

PIO-D64/PIO-D64U User’s Manual ( Ver.1.6, Mar. 2015, PMH-007-16 ) ----- 1
PIO-D64/PIO-D64U
User’s Manual
Warranty
All products manufactured by ICP DAS are warranted
against defective materials for a period of one year from the
date of delivery to the original purchaser.
Warning
ICP DAS assume no liability for damages consequent to
the use of this product. ICP DAS reserves the right to
change this manual at any time without notice. The
information furnished by ICP DAS is believed to be accurate
and reliable. However, no responsibility is assumed by ICP
DAS for its use, nor for any infringements of patents or other
rights of third parties resulting from its use.
Copyright
Copyright 2004 by ICP DAS. All rights are reserved.
Trademark
The names used for identification only may be
registered trademarks of their respective companies.
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PIO-D64/PIO-D64U User’s Manual ( Ver.1.6, Mar. 2015, PMH-007-16 ) ----- 2
Tables of Contents
1. Introduction............................................................................... 5
1.1 Features .................................................................................................6
1.2 Specifications .........................................................................................7
1.3 Product Check List..................................................................................8
1.3.1 Product options....................................................................... 8
2. Hardware configuration ........................................................... 9
2.1 Board Layout ....................................................................................9
2.2 I/O Port Location.............................................................................10
2.3 Pin Assignments..............................................................................10
2.4 I/O Operation ...................................................................................12
2.4.1 DO Port Architecture (CN1 & CN3)....................................... 12
2.4.2 DI Port Architecture (CN2 & CN4).........................................13
2.5 Timer/ Counter Architecture ............................................................14
2.6 Clock source....................................................................................16
2.7 Interrupt Operation ..........................................................................17
2.7.1 Interrupt Block Diagram of PIO-D64/PIO-D64U.................... 18
2.7.2 INT_CHAN_0........................................................................ 19
2.7.3 INT_CHAN_1........................................................................ 20
2.7.4 INT_CHAN_2........................................................................ 21
2.8 Daughter Boards .............................................................................22
2.8.1 DB-16P Isolated Input Board.................................................22
2.8.2 DB-16R Relay Board.............................................................23
2.8.3 DB-24PRD, DB-24POR, DB-24C..........................................24
2.8.4 Daughter Board Comparison Table.......................................25
3. I/O Control Register................................................................ 26
3.1 How to Find the I/O Address............................................................26
3.2 The Assignment of I/O Address.......................................................28
3.3 The I/O Address Map ......................................................................30
3.3.1 RESET\ ControlRegister.......................................................31
3.3.2 AUX Control Register............................................................31
3.3.3 AUX data Register.................................................................31
3.3.4 INT Mask Control Register....................................................32
3.3.5 Aux Status Register.............................................................. 33
3.3.6 Interrupt Polarity Control Register.........................................33
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PIO-D64/PIO-D64U User’s Manual ( Ver.1.6, Mar. 2015, PMH-007-16 ) ----- 3
3.3.7 Read/Write 8254................................................................... 34
3.3.8 Read Card ID........................................................................ 34
4. Software Installation .............................................................. 35
4.1 Software Installing Procedure ......................................................... 35
4.2 PnP Driver Installation.......................................................................... 36
5. DLL Function Description...................................................... 37
5.1 Table of ErrorCode and ErrorString ................................................ 38
5.2 Function Descriptions .................................................................... 38
5.3 FUNCTIONS OF TEST .................................................................. 39
5.3.1 PIODIO_GetDllVersion..........................................................39
5.3.2 PIODIO_ShortSub................................................................39
5.3.3 PIODIO_FloatSub................................................................. 39
5.4 Digital I/O FUNCTIONS .................................................................. 40
5.4.1 PIODIO_OutputByte..............................................................40
5.4.2 PIODIO_InputByte................................................................ 40
5.4.3 PIODIO_OutputWord............................................................ 41
5.4.4 PIODIO_InputWord...............................................................41
5.5 Driver Relative Functions ................................................................ 42
5.5.1 PIODIO_GetDriverVersion.................................................... 42
5.5.2 PIODIO_DriverInit................................................................. 42
5.5.3 PIODIO_SearchCard............................................................ 43
5.5.4 PIODIO_DriverClose...............................................................43
5.5.5 PIODIO_GetConfigAddressSpace........................................ 44
5.6 INTERRUPT FUNCTION ................................................................ 45
5.6.1 PIODIO_IntResetCount........................................................ 45
5.6.2 PIODIO_IntGetCount............................................................ 45
5.6.3 PIODIO_IntInstall.................................................................. 46
5.6.4 PIODIO_IntRemove.............................................................. 46
5.6.5 Architecture of Interrupt mode...............................................47
5.7 COUNTER FUNCTION................................................................... 48
5.7.1 PIOD64_SetCounter............................................................. 48
5.7.2 PIOD64_ReadCounter.......................................................... 48
5.7.3 PIOD64_SetCounterA...........................................................49
5.7.4 PIOD64_ReadCounterA........................................................49
5.7.5 Program Architecture............................................................ 50
6Demo Programs for Windows ............................................... 51
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PIO-D64/PIO-D64U User’s Manual ( Ver.1.6, Mar. 2015, PMH-007-16 ) ----- 4
6.1 Digital Input/Output..........................................................................52
6.2 Interrupt of EXTIRQ.........................................................................52
6.3 Counter Function of counter0 ..........................................................53
Appendix....................................................................................... 54
Appendix A. Related DOS Software .........................................................54
A-1 Where is the related software...................................................54
A-2 DOS LIB Function.....................................................................55
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PIO-D64/PIO-D64U User’s Manual ( Ver.1.6, Mar. 2015, PMH-007-16 ) ----- 5
1. Introduction
The PIO-D64U card is the new generation product that ICP DAS provides to
meet RoHS compliance requirement. The new PIO-D64U card is designed as a
drop-in replacement for the PIO-D64, and users can replace the PIO-D64 by the
PIO-D64U directly without software/driver modification.
The PIO-D64U universal PCI card supports 3.3 V/5 V PCI bus while the PIO-
D64 supports 5 V PCI bus. These cards provide 32-ch digital input and 32-ch
digital output that consist of two 16-bit input ports and two 16-bit output ports.
The PIO-D64U and PIO-D64 also offer 6-ch counter/timer with four-clock
sources, 2 MHz, 1 MHz, 500 kHz and 250 kHz. The user can use the clock
source from the soldering pad. 3 of the 6-ch timer/ counter are for general
purposes such as frequency measurement, event counting and pulse
generation; the other 3 channels are for interrupt function.
The PIO-D64U also adds a Card ID switch and pull-high/ pull-low resisters for DI
on-board. Users can set Card ID and recognize the board by the ID via software
when using two or more PIO-D64U cards in one computer. The pull-high/ pull-
low resisters allow the DI status to be specified when the DI channels are
unconnected; the DI status may remain in high or low status other than floating.
The PIO-D64/D64U supports various OS such as Linux, DOS, Windows
98/NT/2000 and Windows 32/64-bit Windows XP/2003/Vista/7/8. It also
provides the DLL and Active X control, and various language sample program
in Turbo C++, Borland c++, Microsoft C++, Visual C++, Borland Delphi, Borland
C++ Builder, Visual Basic, C#.NET, Visual Basic.NET and LabVIEW to help
users to quickly and easily develop their applications.
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PIO-D64/PIO-D64U User’s Manual ( Ver.1.6, Mar. 2015, PMH-007-16 ) ----- 6
1.1 Features
Support the +5 V PCI bus for PIO-D64
Support the +5 V/+3.3 V PCI bus for PIO-D64U
32 digital input channels ( strobe control selectable );
32 digital output channels;
Four independent programmable 16-bit timers/counters;
One 32-bit timer with a 4 MHz clock base;
Provide clock source: 2 MHz, 1 MHz, 500 KHz, 250 KHz;
Interrupt source: 3 channels;
Breadboard area for add-on circuit;
Five 20-pin flat cable connectors;
Connect directly to DB-24PR, 24POR, DB-24C, DB-16P, DB-16R;
SMD, short card, power saving;
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PIO-D64/PIO-D64U User’s Manual ( Ver.1.6, Mar. 2015, PMH-007-16 ) ----- 7
1.2 Specifications
Model Name
PIO-D64
PIO-D64U
Digital Input
Channels
32
Compatibility
5 V/TTL
Input Voltage
Logic 0: 0.8 V max.
Logic 1: 2.0 V min.
Response Speed
1 MHz
Digital Output
Channels
32
Compatibility
5 V/TTL
Output Voltage
Logic 0: 0.4 V max.
Logic 1: 2.4 V min.
Output Capability
Sink: 24 mA @ 0.8 V
Source: 15 mA @ 2.0 V
Response Speed
1 MHz
Timer/Counter
Channels
6 (Independent x 3/EVTIRQ x 1/TMRIRQ x 1/EXTIRQ x 1)
Resolution
16-bit
Compatibility
5 V/TTL
Input Frequency
10 MHz max.
Reference Clock
Internal: 4 MHz
General
Bus Type
5 V PCI, 32-bit, 33 MHz
3.3 V/5 V Universal PCI,
32-bit, 33 MHz
Data Bus
8-bit
Card ID
No
Yes (4-bit)
I/O Connector
20-pin box header x 5
Dimensions (L x W x D)
156 mm x 110 mm x 22 mm
Power Consumption
580 mA @ +5 V
Operating Temperature
0 ~ 60 °C
Storage Temperature
-20 ~ 70 °C
Humidity
5 ~ 85% RH, non-condensing
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PIO-D64/PIO-D64U User’s Manual ( Ver.1.6, Mar. 2015, PMH-007-16 ) ----- 8
1.3 Product Check List
Your package includes the following items:
One PIO-D64/PIO-D64U card
One company CD
One Quick Start Guide
It is recommended to read the Quick Start Guide first. All the necessary and
essential information are given in the Quick Start Guide as follows:
Where to get the software driver, demo programs and other resources.
How to install the software.
How to test the card.
Attention!
If any of these items is missed or damaged, contact the dealer from whom you
purchased the product. Save the shipping materials and carton in case you
want to ship or store the product in the future.
1.3.1 Product options
DB-24PR, DB-24PRD: 24 channels power relay board;
DB-24POR: 24 channels PhotoMos output board;
DB-24C: 24 channels open-collector output board;
DB-16P: 16 channels isolated D/I board;
DB-16R: 16 channels relay board.
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PIO-D64/PIO-D64U User’s Manual ( Ver.1.6, Mar. 2015, PMH-007-16 ) ----- 9
2. Hardware configuration
2.1 Board Layout
Figure 2.1
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PIO-D64/PIO-D64U User’s Manual ( Ver.1.6, Mar. 2015, PMH-007-16 ) ----- 10
2.2 I/O Port Location
There are two 16-bit digital input ports and two 16-bit digital output ports
on the PIO-D64/PIO-D64U.These I/O port locations are given as below and
illustrated in Figure 2.1.
Connector of
PIO-D64/PIO-D64U
Description
CN1
DO0~DO15
CN2
DI0~DI15
CN3
DO16~DO31
CN4
DI16~DI31
Besides, there is also a connector interface (CN5) for timer and counter
function, as shown in Figure 2.1.
2.3 Pin Assignments
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PIO-D64/PIO-D64U User’s Manual ( Ver.1.6, Mar. 2015, PMH-007-16 ) ----- 11
All signals are TTL compatible.
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PIO-D64/PIO-D64U User’s Manual ( Ver.1.6, Mar. 2015, PMH-007-16 ) ----- 12
2.4 I/O Operation
2.4.1 DO Port Architecture (CN1 & CN3)
When the PC is power-up, all of DO states are clear to low-state by the
RESET\ signal. Fore more information about RESET\ signal, please refer to Sec.
3.1.1. Note that the RESET\ is in Low-state in order to clear all DO states to low
level signal. The detail block diagram of DO function is represented as Figure
2.2.
Figure 2.2: Block diagram of DO function
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PIO-D64/PIO-D64U User’s Manual ( Ver.1.6, Mar. 2015, PMH-007-16 ) ----- 13
2.4.2 DI Port Architecture (CN2 & CN4)
The enable/disable of DI port is controlled by the RESET\ signal, as
depicted as below:
The RESET\ is in Low-state all DI operation is disable
The RESET\ is in High-state all DI operation is enable
Note that when the PC is power-up, all operation of DI port is disabled
because RESET\ is in low level. Besides, user may need to latch input data by
external strobe single in some application. We provide the following architecture,
as shown in Figure 2.3, to allow user to apply the STROBE pin to latch D/I input
signal. If no signal is connected to strobe pin, the input data is transparent.
Figure 2.3
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PIO-D64/PIO-D64U User’s Manual ( Ver.1.6, Mar. 2015, PMH-007-16 ) ----- 14
2.5 Timer/ Counter Architecture
PIO-D64/PIO-D64U has two timer/counter chips, 8254. The first 8254 chip is
used as general purpose timer/counter, as shown in Figure 2.4. The pin
assignment is presented in Sec.2.3.
Figure 2.4
The second 8254 chip is used to generate interrupt trigger signals, as
shown in Figure 2.5. The Counter3 accept event signal and will generate trigger
signal of the interrupt. And the Counter4 and Counter5 are cascaded together,
which has clock source 4 MHz. It is used to generate pacer timer trigger of the
interrupt.
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PIO-D64/PIO-D64U User’s Manual ( Ver.1.6, Mar. 2015, PMH-007-16 ) ----- 15
Figure 2.5
Note: Refer to Sec.2.3 for more information about pin assignment.
Refer to Sec.2.7 for more information about operation of interrupt.
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PIO-D64/PIO-D64U User’s Manual ( Ver.1.6, Mar. 2015, PMH-007-16 ) ----- 16
2.6 Clock source
The PIO-D64 / PIO-D64U provides wide range clock source as below table.
By jumper setting of JP1, user can select suitable clock output from the
corresponding P4 soldering pad.
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PIO-D64/PIO-D64U User’s Manual ( Ver.1.6, Mar. 2015, PMH-007-16 ) ----- 17
2.7 Interrupt Operation
There are three interrupt sources in PIO-D64/PIO-D64U. These three
signals are named as INT_CHAN_0, INT_CHAN_1 and INT_CHAN_2. Their
signal sources are given as follows: (Refer to Sec. 2.5 for the source of
interrupt signal)
INT_CHAN_0: EXTIRQ
INT_CHAN_1: EVTIRQ
INT_CHAN_2: TMRIRQ
If only one interrupt signal source is used, the interrupt service routine
does not have to identify the interrupt source. Refer to DEMO3.C, DEMO4.C
and DEMO5.C of DOS operating system for more information.
If there are more than one interrupt source, the interrupt service routine
has to identify the active signals as follows: (refer to DEMO6.C of DOS
operation system)
1. Read the new status of all interrupt signal sources(refer to Sec 3.1.5)
2. Compare the new status with the old status to identify the active signals
3. If INT_CHAN_0 is active, service it
4. If INT_CHAN_1 is active, service it
5. If INT_CHAN_2 is active, service it
6. Update interrupt status
Note that if the interrupt signal is too short, the new status may be as same
as old status. In that condition the interrupt service routine can not identify which
interrupt source is active. So the interrupt signal must be hold_active long
enough until the interrupt service routine is executed. This hold_time is different
for different operating system. The hold_time can be as short as micro-second
or as long as second. In general, 20 ms is enough for all operating system.
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PIO-D64/PIO-D64U User’s Manual ( Ver.1.6, Mar. 2015, PMH-007-16 ) ----- 18
2.7.1 Interrupt Block Diagram of PIO-D64/PIO-D64U
Figure 2.6
The interrupt output signal of PIO-D64/PIO-D64U, INT\, is level-trigger &
Active_Low. If the INT\ generates a low-pulse, the PIO-D64/PIO-D64U will
interrupt the PC once a time. If the INT\ is fixed in low level, the PIO-D64/PIO-
D64U will interrupt the PC continuously. Therefore, for the normal application,
the INT_CHAN_0/1/2 must be controlled in a pulse_type signals. That is, they
must be fixed in low level state normally and generate a high_pulse to
interrupt the PC.
The priority of INT_CHAN_0/1/2 is the same. If all these three signals are
active at the same time, then INT\ will be active only once a time. So the
interrupt service routine has to read the status of all interrupt channels for multi-
channel interrupt. Refer to DEMO6.C in DOS operating system for demonstrate
the application under the condition of both INT_CHAN_1 and INT_CHAN_2.
If only one interrupt source is used, the interrupt service routine doesn’t
have to read the status of interrupt source. The demo programs, DEMO3.C,
DEMO4.C and DEMO5.C in DOS operating system, are designed for single-
channel interrupt application as follows:
DEMO3.C for INT_CHAN_0 only
DEMO4.C for INT_CHAN_1 only
DEMO5.C for INT_CHAN_2 only
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PIO-D64/PIO-D64U User’s Manual ( Ver.1.6, Mar. 2015, PMH-007-16 ) ----- 19
2.7.2 INT_CHAN_0
Figure 2.7
Figure 2.7 illustrates the control method of external interrupt. Note that
the signal source comes from GATE4. The INV0 is used to invert/non-invert the
trigger signal source and EN0 is used to disable/enable the timer interrupt
(Pin13 of CN5) (Refer to Sec. 2.5 for the source of interrupt signal). The
INT_CHAN_0 must be fixed in low level state normally and generated a
high_pulse to interrupt the PC.
1. The EN0 can be used to enable/disable the INT_CHAN_0 as follows: (refer
to Figure 2.7 and Sec. 3.1.4)
EN0=0 INT_CHAN_0=disable
EN0=1 INT_CHAN_0=enable
2. The INV0 can be used to invert/non-invert the EXTIRQ as follows: (Refer to
Figure 2.7 and Sec. 3.1.6)
INV0=0 INT_CHAN_0=inverted state of EXTIRQ
INV0=1 INT_CHAN_0=non-inverted state of EXTIRQ
NOTE: Refer to DEMO3.C in DOS operating system for more information.
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PIO-D64/PIO-D64U User’s Manual ( Ver.1.6, Mar. 2015, PMH-007-16 ) ----- 20
2.7.3 INT_CHAN_1
Figure 2.8
Figure 2.8 illustrates the control method of event interrupt. Note that the
signal source comes from OUT3. The INV1 is used to invert/non-invert the
trigger signal source and EN1 is used to disable/enable the timer interrupt
(Refer to Sec. 2.5 for the source of interrupt signal). User can use Counter3 as
event counter to count the event signal that comes from Pin7 of CN5. When the
amount of event is the same as counter3 setting, the interrupt of INT_CHAN_1
will be trigger. The INT_CHAN_1 must be fixed in low level state normally
and generated a high_pulse to interrupt the PC.
1. The EN1 can be used to enable/disable the INT_CHAN_1 as follows: (refer
to Figure 2.8 and Sec. 3.1.4)
EN1=0 INT_CHAN_1=disable
EN1=1 INT_CHAN_1=enable
2. The INV1 can be used to invert/non-invert the EVTIRQ as follows: (Refer to
Figure 2.8 and Sec. 3.1.6)
INV1=0 INT_CHAN_1=inverted state of EVTIRQ
INV1=1 INT_CHAN_1=non-inverted state of EVTIRQ
NOTE: Refer to DEMO4.C in DOS operating system for more information.
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