SONIX SN8P2977 User manual

SN8P2977
8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC
SONiX TECHNOLOGY CO., LTD Page 1 V1.7
SN8P2977
USER’S MANUAL
Specification V1.7
S
SO ON Ni iX X 8 8- -B Bi it t M Mi ic cr ro o- -C Co on nt tr ro ol ll le er r
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.

SN8P2977
8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC
SONiX TECHNOLOGY CO., LTD Page 2 V1.7
AMENDENT HISTORY
Version
Date
Description
Ver1.0
2016.12
New Version start.
Ver1.1
2017.01
Modify BZRM & ROMDAH & ROMDAL register only write.
Ver1.2
2017.01
1. Modify 1.2 MIGRATION TABLEUART Total Capacitors descriptions.
2. Modify 1.1 SELECTION TABLE descriptions.
3. Modify 1.6 PIN DESCRIPTIONS descriptions.
4. Modify 2.1.3 CODE OPTION TABLE Low_power descriptions.
5. Modify 2.1.5.3 BIT DEFINITION of SYSTEM REGISTER descriptions.
6. Modify 5.1 Operating mode description.
7. Modify 11.5 C-TYPE LCD DRIVER MODE description.
8. Modify 12.1 ROMADRH/ROMADRL REGISTER description.
9. Modify 13 Regulator, PGIA and ADC description.
10. Add AMPCKS[2:0]: PGIA chopper selection.(Always set “7.8k Hz”) description.
11. Add 13.4.2 AMPM- Amplifier Mode Control Register Note_2: When PGIA Gain set 1x
(GS[2:0]=111) application, the AI+/AI- signal input buffer of PGIA mustbe enabled
(AMPENB=1) for input high impedance characteristic of ADC.
12. Modify 13.5 Temperature Sensor (TS) description.
13. Modify 13.6 24-Bit Analog to Digital Converter (ADC) description.
14. Modify 13.6.5 ADCM1- ADC Mode1 Register Bit 0 ADCENB description.
15. Modify 13.6.7 ADC Data Register Note description.
16. Modify 14 APPLICATION CIRCUIT.
17. Modify 17 ELECTRICAL CHARACTERISTIC.
Ver1.3
2017.02
1. Modify 13.4.1CHS- Analog input signal channel selection Register note 4.
(GS[2:0]=000)
2. Modify 13.4.2AMPM- Amplifier Mode Control Register note1 & note2. (GS[2:0]=000)
3. Modify 12.2 ROMADRH/ROMADRL REGISTER
Ver1.4
2017.02
1. Add ROMADR[15] : ISP ROM Programming selection control bit. (Always set “0”)
2. Modify ROMADR[11:0] : ISP ROM Programming Address.
3. Modify ELECTRICAL CHARACTERISTIC P0 IoH Min value 7mA.
4. Modify ELECTRICAL CHARACTERISTIC P1 IoH Min value 15mA,Typ value 20mA
5. Modify ELECTRICAL CHARACTERISTIC P3 IoH Min value 12mA.
6. Modify ELECTRICAL CHARACTERISTIC P2 IoL Min value 45mA,Typ value 60mA
7. ADD ELECTRICAL CHARACTERISTIC P1,P3 IoL Min value 45mA
8. ADD ELECTRICAL CHARACTERISTIC LBT 3.0V Min = 2.8V,Typ=3.0V,Max=3.2V
9. ADD ELECTRICAL CHARACTERISTIC LBT 3.6V Min = 3.4V,Typ=3.6V,Max=3.8V
Ver1.5
2017.06
Add package information(QFN32、TSSOP28、SSOP20、SOP16)
Ver1.6
2017.09
1.Modify the ceramic capacitor configuration of the application circuit.(page125,126)
2.Modify QFN32 symbols table.(A Typical→0.8mm, A Max→0.9mm)(page 139)
3.Add Package information(Ver1.5) to FEATURES(Chapter 1.3)
4.Modify QFN32 package type of name to 2975 from 2977.(page 14)
Ver1.7
2017.09
1.Modify the name of package type in SSOP20 from SN8P2972 to SN8P2973.(page14)

SN8P2977
8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC
SONiX TECHNOLOGY CO., LTD Page 3 V1.7
Table of Content
AMENDENT HISTORY........................................................................................................................................ 2
1
1
1
PRODUCT OVERVIEW...............................................................................................................................8
1.1 SELECTION TABLE ................................................................................................................................ 8
1.2 MIGRATION TABLEUART..................................................................................................................... 8
1.3 FEATURES ............................................................................................................................................... 9
1.4 SYSTEM BLOCK DIAGRAM................................................................................................................ 10
1.5 PIN ASSIGNMENT................................................................................................................................. 11
1.6 PIN DESCRIPTIONS .............................................................................................................................. 15
1.7 PIN CIRCUIT DIAGRAMS..................................................................................................................... 16
2
2
2
CENTRAL PROCESSOR UNIT (CPU) ......................................................................................................17
2.1 MEMORY MAP ...................................................................................................................................... 17
2.1.1 PROGRAM MEMORY (ROM) .......................................................................................................... 17
2.1.2 RESET VECTOR (0000H).................................................................................................................. 18
2.1.3 CODE OPTION TABLE.......................................................................................................................... 26
2.1.4 DATA MEMORY (RAM) ....................................................................................................................... 27
2.1.5 SYSTEM REGISTER.......................................................................................................................... 28
2.1.6 ACCUMULATOR............................................................................................................................... 31
2.1.7 PROGRAM FLAG .............................................................................................................................. 32
2.1.8 PROGRAM COUNTER...................................................................................................................... 33
2.1.9 MULTI-ADDRESS JUMPING ........................................................................................................... 35
2.1.10 Y, Z REGISTERS ........................................................................................................................... 36
2.1.11 H, L REGISTERS ........................................................................................................................... 37
2.1.12 R REGISTERS ................................................................................................................................ 38
2.2 ADDRESSING MODE............................................................................................................................ 39
2.2.1 IMMEDIATE ADDRESSING MODE ................................................................................................ 39
2.2.2 DIRECTLY ADDRESSING MODE ................................................................................................... 39
2.2.3 INDIRECTLY ADDRESSING MODE............................................................................................... 39
2.3 STACK OPERATION ............................................................................................................................. 40
2.3.1 OVERVIEW ........................................................................................................................................ 40
2.3.2 STACK REGISTERS .......................................................................................................................... 41
2.3.3 STACK OPERATION EXAMPLE ..................................................................................................... 42
3
3
3
RESET........................................................................................................................................................43
3.1 OVERVIEW ............................................................................................................................................ 43
3.2 POWER ON RESET ................................................................................................................................ 43
3.3 WATCHDOG RESET ............................................................................................................................. 44
3.4 BROWN OUT RESET............................................................................................................................. 44
3.4.1 BROWN OUT DESCRIPTION........................................................................................................... 44
3.4.2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION ............................................................... 45
3.4.3 BROWN OUT RESET IMPROVEMENT .......................................................................................... 45
4
4
4
SYSTEM CLOCK.......................................................................................................................................47

SN8P2977
8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC
SONiX TECHNOLOGY CO., LTD Page 4 V1.7
4.1 OVERVIEW ............................................................................................................................................ 47
4.2 CLOCK BLOCK DIAGRAM .................................................................................................................. 47
4.3 OSCM REGISTER .................................................................................................................................. 48
4.4 SYSTEM HIGH CLOCK......................................................................................................................... 49
4.5 SYSTEM LOW CLOCK.......................................................................................................................... 49
4.5.1 SYSTEM CLOCK MEASUREMENT ................................................................................................ 50
5
5
5
SYSTEM OPERATION MODE..................................................................................................................51
5.1 OVERVIEW ............................................................................................................................................ 51
5.2 SYSTEM MODE SWITCHING .............................................................................................................. 52
5.3 WAKEUP ................................................................................................................................................ 54
5.3.1 OVERVIEW ........................................................................................................................................ 54
5.3.2 WAKEUP TIME.................................................................................................................................. 54
6
6
6
INTERRUPT ..............................................................................................................................................55
6.1 OVERVIEW ............................................................................................................................................ 55
6.2 INTEN INTERRUPT ENABLE REGISTER ........................................................................................... 56
6.3 INTRQ INTERRUPT REQUEST REGISTER......................................................................................... 56
6.4 GIE GLOBAL INTERRUPT OPERATION ............................................................................................ 57
6.5 PUSH, POP ROUTINE............................................................................................................................ 58
6.6 EXTERNAL INTERRUPT OPERATION............................................................................................... 59
6.7 MULTI-INTERRUPT OPERATION....................................................................................................... 60
7
7
7
I/O PORT....................................................................................................................................................62
7.1 I/O PORT MODE..................................................................................................................................... 62
7.2 I/O PIN SHARE WITH LCD FUNCTION............................................................................................... 62
7.3 I/O PULL UP REGISTER........................................................................................................................ 64
7.4 I/O PORT DATA REGISTER.................................................................................................................. 65
7.5 HIGH-SINK CURRENT I/O PORT................................................................................................................ 66
8
8
8
TIMERS .....................................................................................................................................................67
8.1 WATCHDOG TIMER ............................................................................................................................. 67
8.2 TIMER 0(T0) .......................................................................................................................................... 69
8.2.1 OVERVIEW ........................................................................................................................................ 69
8.2.2 T0M MODE REGISTER..................................................................................................................... 69
8.2.3 T0C COUNTING REGISTER............................................................................................................. 71
8.2.4 T0 TIMER OPERATION SEQUENCE (High_Clk = IHRC).............................................................. 72
8.2.5 RTC OPERATION SEQUENCE (High_Clk =“IHRC_RTC” and “T0TB = 1”)....................... 73
8.3 TIMER/COUNTER 0(TC0) .................................................................................................................... 75
8.3.1 OVERVIEW ........................................................................................................................................ 75
8.3.2 TC0M MODE REGISTER .................................................................................................................. 76
8.3.3 TC0X8, TC0GN FLAGS..................................................................................................................... 77
8.3.4 TC0C COUNTING REGISTER .......................................................................................................... 78
8.3.5 TC0R AUTO-LOAD REGISTER ....................................................................................................... 80
8.3.6 TC0 CLOCK FREQUENCY OUTPUT (BUZZER)............................................................................ 81
8.3.7 TC0 TIMER OPERATION SEQUENCE............................................................................................ 82

SN8P2977
8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC
SONiX TECHNOLOGY CO., LTD Page 5 V1.7
8.4 PWM0 MODE ......................................................................................................................................... 83
8.4.1 OVERVIEW ........................................................................................................................................ 83
8.4.2 TC0IRQ AND PWM DUTY ............................................................................................................... 84
8.4.3 PWM PROGRAM EXAMPLE............................................................................................................ 84
8.4.4 PWM0 DUTY CHANGING NOTICE ................................................................................................ 85
9
9
9
UART.........................................................................................................................................................86
9.1 OVERVIEW ............................................................................................................................................ 86
9.2 UART OPERATION ............................................................................................................................... 86
9.3 UART TRANSFER FORMAT ................................................................................................................ 87
9.4 ABNORMAL POCKET........................................................................................................................... 88
9.5 UART BAUD RATE ............................................................................................................................... 88
9.6 UART RECEIVER CONTROL REGISTER............................................................................................ 90
9.7 UART TRANSMITTER CONTROL REGISTER ................................................................................... 90
9.8 UART TRANSMITTER CONTROL REGISTER ................................................................................... 91
9.9 UART OPERATION EXAMLPE ............................................................................................................ 92
1
1
10
0
0
BUZZER FUNCTION ................................................................................................................................93
10.1 OVERVIEW ............................................................................................................................................ 93
10.2 BUZZER CONTROL REGISTER........................................................................................................... 93
1
1
11
1
1
LCD DRIVER.............................................................................................................................................94
11.1 OVERVIEW ............................................................................................................................................ 94
11.2 LCD TIMING .......................................................................................................................................... 94
11.3 LCDM1 REGISTER ................................................................................................................................ 96
11.4 LCDM2 REGISTER ................................................................................................................................ 96
11.5 C-TYPE LCD DRIVER MODE............................................................................................................... 98
11.6 R-TYPE LCD DRIVER MODE............................................................................................................... 99
11.7 LCD RAM LOCATION......................................................................................................................... 101
1
1
12
2
2
IN SYSTEM PROGRAM ROM ................................................................................................................102
12.1 OVERVIEW .......................................................................................................................................... 102
12.2 ROMADRH/ROMADRL REGISTER................................................................................................... 102
12.3 ROMDAH/ROMADL REGISTERS...................................................................................................... 102
12.4 ISP ROM ROUTINE EXAMPLE .......................................................................................................... 103
1
1
13
3
3
REGULATOR, PGIA AND ADC .............................................................................................................104
13.1 OVERVIEW .......................................................................................................................................... 104
13.2 ANALOG INPUT .................................................................................................................................. 104
13.3 VOLTAGE REGULATOR............................................................................................................................ 105
13.3.1 Voltage Regulator Control Register............................................................................................... 105
13.4 PGIA -PROGRAMMABLE GAIN INSTRUMENTATION AMPLIFIER ............................................................... 106
13.4.1 CHS- Analog input signal channel selection Register ................................................................... 106
13.4.2 AMPM- Amplifier Mode Control Register.................................................................................... 108
13.5 TEMPERATURE SENSOR (TS)................................................................................................................... 109
13.6 24-BIT ANALOG TO DIGITAL CONVERTER (ADC) ................................................................................... 111
13.6.1 Analog Inputs and Voltage Operation Range ................................................................................ 111

SN8P2977
8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC
SONiX TECHNOLOGY CO., LTD Page 6 V1.7
13.6.2 Reference Voltage ......................................................................................................................... 111
13.6.3 ADC Gain and Offset .................................................................................................................... 112
13.6.4 Output Word Rate.......................................................................................................................... 113
13.6.5 ADCM1- ADC Mode1 Register .................................................................................................... 113
13.6.6 ADCM2- ADC Mode2 Register .................................................................................................... 114
13.6.7 ADC Data Register........................................................................................................................ 115
13.7 LBTM: LOW BATTERY DETECT.............................................................................................................. 121
13.7.1 LBTM: Low Battery Detect Register ............................................................................................ 121
13.8 ANALOG SETTING AND APPLICATION ...................................................................................................... 123
1
1
14
4
4
APPLICATION CIRCUIT ........................................................................................................................125
14.1 SCALE (LOAD CELL)APPLICATION CIRCUIT............................................................................................ 125
14.2 THERMOMETER APPLICATION CIRCUIT..................................................................................................... 126
1
1
15
5
5
INSTRUCTION SET TABLE ...................................................................................................................127
1
1
16
6
6
DEVELOPMENT TOOLS ........................................................................................................................128
16.1 DEVELOPMENT TOOL VERSION ............................................................................................................... 128
16.1.1 ICE (IN CIRCUIT EMULATION) ............................................................................................................. 128
16.1.2 OTP WRITER ...................................................................................................................................... 128
16.1.3 IDE (INTEGRATED DEVELOPMENT ENVIRONMENT)............................................................................. 128
16.2 OTP PROGRAMMING PIN TO TRANSITION BOARD MAPPING.................................................................... 129
16.3 APPENDIX A: EV-KIT BOARD CIRCUIT.......................................................................................... 130
16.4 SN8P2977 EMULATION .......................................................................................................................... 131
16.4.1 INTRODUCTION ......................................................................................................................... 131
16.4.2 SN8ICE2K_Plus_II Hardware Setting Notice for SN2977 EV-Kit ............................................... 131
16.4.3 SN8P2977 EV Board DESCRIPTION .......................................................................................... 132
16.4.4 EV BOARD SETTING ................................................................................................................. 133
16.4.5 Notice for EV Emulation............................................................................................................... 133
1
1
17
7
7
ELECTRICAL CHARACTERISTIC.........................................................................................................134
17.1 ABSOLUTE MAXIMUM RATING...................................................................................................... 134
17.2 ELECTRICAL CHARACTERISTIC..................................................................................................... 134
1
1
18
8
8
PACKAGE INFORMATION ....................................................................................................................136
18.1 DIP 48 PIN............................................................................................................................................. 136
18.2 SSOP 48 PIN.......................................................................................................................................... 137
18.3 LQFP 48 PIN.......................................................................................................................................... 138
18.4 QFN 32 PIN ........................................................................................................................................... 139
18.5 TSSOP28 PIN ........................................................................................................................................ 140
18.6 SSOP20 PIN........................................................................................................................................... 141
18.7 SOP 18 PIN............................................................................................................................................ 142
18.8 SOP 16 PIN............................................................................................................................................ 143
1
1
19
9
9
MARKING DEFINITION.........................................................................................................................144
19.1 INTRODUCTION ................................................................................................................................. 144
19.2 MARKING INDETIFICATION SYSTEM............................................................................................ 144

SN8P2977
8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC
SONiX TECHNOLOGY CO., LTD Page 7 V1.7
19.3 MARKING EXAMPLE ......................................................................................................................... 145
19.4 DATECODE SYSTEM.......................................................................................................................... 145

SN8P2977
8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC
SONiX TECHNOLOGY CO., LTD Page 8 V1.7
1
1
1
PRODUCT OVERVIEW
1.1 SELECTION TABLE
CHIP
ROM
RAM
Stack
LCD
Timer
I/O
ADC
PWM0/
Buzzer0
Buzzer
RTC
Wakeup
Pin no.
UART
Package
T0
TC0
TC1
SN8P2967
2K*16
192*8
8
4*12
V
V
-
10
20-bit
1
-
1
8
1
DIP48/SSOP48/LQFP48
SN8P2962
2K*16
192*8
8
-
V
V
-
10
20-bit
1
-
1
8
1
SOP18
SN8P2977
4K*16
256*8
8
4*16
V
V
-
26
24-bit
1
1
1
8
1
DIP48/SSOP48/LQFP48
SN8P2972
4K*16
256*8
8
-
V
V
-
26
24-bit
1
1
1
8
1
SOP18
Table 1-1 Selection table of SN8Px9x7 serial
1.2 MIGRATION TABLEUART
Table 1-2 SN8P29x7 Migration Table
Item
SN8P2967
SN8P2977
PGIA Gain setting
1x, 16x, 32x, 64x, 128x
(ADC Gain option ~ 2x)
1x, 16x, 32x, 64x, 128x, 200x
(ADC Gain option ~ 2x)
PGIA Temperature Drift
Good
Good
AVE+ Voltage
No
2.0V or 1.5V
/1V or 0.75V
AVE+ Capacitor
No Capacitor
1uf
ACM Voltage
No
No
ACM Capacitor
No Capacitor
No Capacitor
AVDDR
2.4V / 2.8V /3.2V
2.4V / 2.8V /3.2V
Load cell Power
AVDDR
AVDDR or AVE
ADC Input Channel
1 fully differential Input
2 fully differential Input
4 single-ended Input
ADC Reference External Voltage V(R+, R-)
No
Yes
ADC Reference Internal Voltage
0.36V ~ 1.2V
0.23V ~ 1.6V
ADC output Rate
7.6Hz~5.2kHz
7.6Hz~5.2kHz
ADC Interrupt
Yes
Yes
ADC Run in Green Mode
(with wake-up function)
Yes
Yes
Battery Detect Method
By Comparator or
By ADC
By Comparator or
By ADC
Temperature Sensor
Build In
Build In
Chopper clock frequency
31.25K
31.25K
AVDDR/AVE+ working in slow mode
Yes
Yes
Operating/Slow mode Current Consumption
Less
Less
INT Interrupt Channel
INT0
INT0/INT1
LCD Bias Voltage
1/3 or 1/2 Bias
1/3 or 1/2 Bias
LCD Type
R type / C type
R type / C type
VLCD Voltage
Adjustable (2.6V~3.3V)
Adjustable (2.6V~3.3V)
VLCD Capacitors
1-Cap (CVLCD)
1-Cap (CVLCD)
Timer
T0: base timer / RTC
TC0: timer/counter/buzzer/PWM
T0: base timer / RTC
TC0: timer/counter/buzzer/PWM
RTC
Yes
Yes
UART
Yes
Yes
OTP Programming Method
Serial Method
Serial Method
In-System Programmer ROM
Yes(Internal 7.5V)
Yes(Internal 6.5V)
Total Capacitors
5-Cap
5-Cap

SN8P2977
8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC
SONiX TECHNOLOGY CO., LTD Page 9 V1.7
1.3 FEATURES
◆
Memory configuration
◆
Five interrupt sources
OTP ROM size: 4K * 16 bits
Three internal interrupts: T0, TC0, ADC
RAM size: 256 * 8 bits
Three external interrupts: INT0 / INT1, UART(RX/TX)
8-levels stack buffer
LCD RAM size: 4*16 bits
◆
Single power supply: 2.4V ~ 3.6V (Analog Part)
2.0V ~ 3.6V (Digital Part)
◆
I/O pin configuration
◆
On-chip watchdog timer
Bi-directional: P0, P1, P2, P3
On-chip Regulator (AVDDR) with 2.4V voltage
Wakeup: P0
output and maximum 10mA driven current
Pull-up resistors: P0, P1
(Option:2.4V,2.8V,3.2V)
External interrupt: P0
High-Sink Current I/O: P2, P3
◆
On-chip Regulator AVE with selectable 2V/1.5V/0.75/1V
◆
On-chip 1.2V Band gap reference for battery monitor
◆
Powerful instructions
◆
Internal LBT 2.2V~3.6V; or external P10 input LBT
One clocks per instruction cycle
◆
Build in ADC reference voltage = 0.23V~1.6V
All instructions are one word length
◆
In-system Programmer ROM with Int. 6.5V generation
Most of instructions are 1 cycle only.
◆
One Temperature Sensor
Maximum instruction cycle is “2”.
◆
LCD driver:
JMP instruction jumps to all ROM area.
1/3 or 1/2 bias voltage.
All ROM area look-up table function (MOVC)
4 common * 16 segment
Fcpu : IHRC/4, /8, /16, /32
Both R type and C type LCD
1C-type LCD Voltage: 2.6 ~3.3V
R-type Mode
◆
Seven-segment display driver:
◆
Two 8-Bit Timer
P2/P3 are High Current Sink I/O and applied for LED display
T0: Basic Timer. Build in 0.5 sec RTC mode
◆
TC0:Auto-reload Timer/Counter/PWM0/Buzzer
◆
Dual clock system offers four operating modes
◆
One Buzzer output
Internal high clock: RC type up to 8 MHz
Buzzer Output P03: 0.98K / 1.96K / 3.9K/ 7.8K
Internal Low clock: RC type up to 32kHz
◆
Programmable Gain Instrumentation Amplifier
Normal mode: Both high and low clock active
PGIA Gain option: 1x/4x/8x/16x/32x/64x/128x
Slow mode: Low clock active and 32768 X’tal
/200x
Green mode: Low clock active and optional high clock
◆
20-bit Delta-Sigma ADC
Wakeup by P0/T0/TC0/ADC
ADC Gain selection: 1x, 2x
Sleep mode: Both high and low clock stop
ADC Offset selection: (-1/4, -2/4, -3/4) * Vref )
ADC Interrupt and Green Mode wakeup function
◆
Package
4-ADC channels configuration:
Dice/LQFP48/DIP48/SSOP48/QFN32
TSSOP28/SSOP20/SOP18/SOP16
- Two fully differential channels
- Four single channel

SN8P2977
8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC
SONiX TECHNOLOGY CO., LTD Page 10 V1.7
1.4 SYSTEM BLOCK DIAGRAM
INTERRUPT
CONTROL
ACC
TIMING GENERATOR
RAM
SYSTEM REGISTERS
LVD
WATCHDOG TIMER
TIMER & COUNTER
ALU
PC
FLAGS
IR OTP
ROM
AVDDR/AVE
Internal
High RC
oscillator
P0 P1
Internal
Low RC
oscillator
Regulator
PGIA
Low Battery
Comparator
Internal
Reference
20-BIT ADC
VLCD/VDD Detect
AI1~ AI4
LCD Driver
R/C-Type
COM0
COM3
SIG00
SIG15
……
20-BIT ADC
UART UTX,URX
P2 P3
Figure 1-1 Simplified system block diagram

SN8P2977
8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC
SONiX TECHNOLOGY CO., LTD Page 11 V1.7
1.5 PIN ASSIGNMENT
SN8P2977 DIP48/SSOP48
SEG6/P31
1
48
P30/SEG7
SEG5/P32
2
47
P27/SEG8
SEG4/P33
3
46
P26/SEG9
SEG3/P34
4
45
P25/SEG10
SEG2/P35
5
44
P24/SEG11
SEG1/P36
6
43
P23/SEG12
SEG0/P37
7
42
P22/SEG13
COM3
8
41
P21/SEG14
COM2
9
40
P20/SEG15
COM1
10
39
NC
COM0
11
38
NC
VLCD/VPP
12
37
DVDD
NC
13
36
DVSS
NC
14
35
P07/LXOUT
AVDDR
15
34
P06/LXIN
AVE
16
33
P05/RX
AVSS
17
32
P04/PDB/TX
AVDD
18
31
P03/SHIFTDATA/Buzzer
AI1
19
30
P02/OTPCLK
AI2
20
29
P01/INT1/PGCLK
R+/AI3
21
28
P00/INT0
R-/AI4
22
27
NC
NC
23
26
P11/PWM0
NC
24
25
P10/LBT

SN8P2977
8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC
SONiX TECHNOLOGY CO., LTD Page 12 V1.7
SN8P2977 LQFP48
SEG2/P35
SEG3/P34
SEG4/P33
SEG5/P32
SEG6/P31
SEG7/P30
SEG8/P27
SEG9/P26
SEG10/P25
SEG11/P24
SEG12/P23
SEG13/P22
48
47
46
45
44
43
42
41
40
39
38
37
P36/SEG1
1
O
36
SEG14/P21
P37/SEG0
2
35
SEG15/P20
COM3
3
34
NC
COM2
4
33
NC
COM1
5
32
DVDD
COM0
6
SN8P2977
31
DVSS
VLCD/VPP
7
30
P07/LXOUT
AVDDR
8
29
P06/LXIN
AVE
9
28
P05/RX
AVSS
10
27
P04/TX
AVDD
11
26
P03/Buzzer
NC
12
25
P02
13
14
15
16
17
18
19
20
21
22
23
24
AI1
AI2
R+/AI3
R-/AI4
NC
NC
NC
NC
LBT/P10
PWM0/P11
INT0/P00
INT1/P01

SN8P2977
8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC
SONiX TECHNOLOGY CO., LTD Page 13 V1.7
SN8P2975 QFN32
SN8P2974 TSSOP28
COM2
1
28
COM3
COM1
2
27
P37/SEG0
COM0
3
26
P36/SEG1
VLCD/VPP
4
25
P35/SEG2
AVDDR
5
24
P34/SEG3
AI1
6
23
P33/SEG4
AI2
7
22
P32/SEG5
VDD
8
21
P31/SEG6
VSS
9
20
P30/SEG7
INT1/P01
10
19
P27/SEG8
P02
11
18
P26/SEG9
Buzzer/P03
12
17
P25/SEG10
TX/P04
13
16
P24/SEG11
P22/SEG13
14
15
P23/SEG12
VLCD/VPP
AVDDR
AI1
AI2
VSS
VDD
INT1/P0.1
P0.2
1
2
3
4
5
6
7
8
P0.3/BZ
P0.4/TX
P0.6/LXIN
P0.7/LXOUT
SEG15/P20
SEG14/P21 SEG13/P22
SEG12/P23
9 10 11 12 13
14 15 16
24
23
22
21
20
19
18
17
32 31 30
29 28 27 26 25
SEG4/P33
SEG5/P32
SEG6/P31
SEG7/P30
SEG8/P27
SEG9/P26
SEG10/P25
SEG11/P24
COM0 COM1 COM2 COM3
SEG0/P37
SEG1/P36 SEG2/P35
SEG3/P34
2975

SN8P2977
8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC
SONiX TECHNOLOGY CO., LTD Page 14 V1.7
SN8P2973 SSOP20
VLCD/VPP
1
20
P27/SEG8
AVDDR
2
19
P26/SEG9
AVDD
3
18
P25/SEG10
AI1
4
17
P24/SEG11
AI2
5
16
P23/SEG12
INT1/P01
6
15
P22/SEG13
P02
7
14
P21/SEG14
Buzzer/P03
8
13
P20/SEG15
TX/P04
9
12
DVDD
RX/P05
10
11
DVSS
SN8P2972 SOP18
VLCD/VPP
1
18
DVDD
AVDDR
2
17
DVSS
AVSS
3
16
P07/LXOUT
AVDD
4
15
P06/LXIN
AI1
5
14
P05/RX
AI2
6
13
P04/TX
P10/LBT
7
12
P03/Buzzer
P11/PWM0
8
11
P02
P00/INT0
9
10
P01/INT1
SN8P2971 SOP16
VLCD/VPP
1
16
DVDD
AVDDR
2
15
DVSS
AI1
3
14
P07/LXOUT
AI2
4
13
P06/LXIN
P1.0/LBT
5
12
P05/RX
P1.1/PWM0
6
11
P04/TX
P0.0/INT0
7
10
P03/Buzzer
P0.1/INT1
8
9
P02

SN8P2977
8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC
SONiX TECHNOLOGY CO., LTD Page 15 V1.7
1.6PIN DESCRIPTIONS
PIN NAME
TYPE
DESCRIPTION
DVDD, AVDD
DVSS, AVSS
P
Power supply input pins for digital / Analog circuit
AVDDR
P
Regulator power output pin, Voltage = 2.4V, 2.8V, 3.2V
AVE
P
Regulator power output pin, Voltage = 0.75V/1V(sink only), 1.5V/2.0V
AI1 ~ AI4
P
Analog input channel of PGIA. (AI3/AI4 share with R+/R- function)
VLCD/VPP
P
VPP: OTP ROM programming pin only. (No reset function.)
VLCD: LCD driver power pin. (When R-Type LCD mode, VLCD = VDD auto
connection)
COM [3:0]
O
COM0~COM3 LCD driver common port
SEG0 ~ SEG15
O
LCD driver segment pins
P37/SEG0
I/O
P37 IO function share with LCD SEG0.
P36/SEG1
I/O
P36 IO function share with LCD SEG1.
P35/SEG2
I/O
P35 IO function share with LCD SEG2.
P34/SEG3
I/O
P34 IO function share with LCD SEG3.
P33/SEG4
I/O
P33 IO function share with LCD SEG4.
P32/SEG5
I/O
P32 IO function share with LCD SEG5.
P31/SEG6
I/O
P31 IO function share with LCD SEG6.
P30/SEG7
I/O
P30 IO function share with LCD SEG7.
P27/SEG8
I/O
P27 IO function share with LCD SEG8.
P26/SEG9
I/O
P26 IO function share with LCD SEG9.
P25/SEG10
I/O
P25 IO function share with LCD SEG10.
P24/SEG11
I/O
P24 IO function share with LCD SEG11.
P23/SEG12
I/O
P23 IO function share with LCD SEG12.
P22/SEG13
I/O
P22 IO function share with LCD SEG13.
P21/SEG14
I/O
P21 IO function share with LCD SEG14.
P20/SEG15
I/O
P20 IO function share with LCD SEG15.
P0 [7:0]
I/O
P00~P07 bi-direction pins / wakeup pins/ Built-in pull-up resisters
P00
I/O
IO share with INT0
P01
I/O
IO share with INT1
P03
I/O
IO share with Buzzer function
P04
I/O
IO share with UART-TX
P05
I/O
IO share with UART-RX
P06
I/O
IO share with LXIN 32768 Oscillator.
P07
I/O
IO share with LXOUT 32768 Oscillator.
P1 [1:0]
I/O
P10~P11 bi-direction pins / Built-in pull-up resisters (optional)
P10
I/O
I/O shire with LBT function (Low battery detect, comparator input)
P11
I/O
I/O shire with PWM0/TC0OUT.

SN8P2977
8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC
SONiX TECHNOLOGY CO., LTD Page 16 V1.7
1.7 PIN CIRCUIT DIAGRAMS
Port 0, Port 1 structure:
Port 2, Port 3 structure:
Pull-Up
Pin
Output
Latch
PnM, PnUR
Input Bus
PnM
Output Bus
PnSEG
LCD-SEG Function
Pull-Up
Pin
Output
Latch
PnM, PnUR
Input Bus
PnM
Output Bus

SN8P2977
8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC
SONiX TECHNOLOGY CO., LTD Page 17 V1.7
2
2
2
CENTRAL PROCESSOR UNIT (CPU)
2.1 MEMORY MAP
2.1.1 PROGRAM MEMORY (ROM)
4K words ROM
ROM
0000H
Reset vector
User reset vector
0001H
General purpose area
Jump to user start address
0002H
Jump to user start address
0003H
Jump to user start address
0004H
Reserved
0005H
0006H
0007H
0008H
Interrupt vector
User interrupt vector
0009H
General purpose area
User program
.
.
000FH
0010H
0011H
.
.
FFBH
End of user program
FFCH
.
FFFH
Reserved

SN8P2977
8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC
SONiX TECHNOLOGY CO., LTD Page 18 V1.7
2.1.2 RESET VECTOR (0000H)
A one-word vector address area is used to execute system reset.
Power On Reset
Watchdog Reset
After power on reset or watchdog timer overflow reset, then the chip will restart the program from address 0000h and
all system registers will be set as default values. The following example shows the way to define the reset vector in the
program memory.
Example: Defining Reset Vector
ORG
0
; 0000H
JMP
START
; Jump to user program address.
…
ORG
10H
START:
; 0010H, The head of user program.
…
; User program
…
ENDP
; End of program

SN8P2977
8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC
SONiX TECHNOLOGY CO., LTD Page 19 V1.7
2.1.2.1 INTERRUPT VECTOR (0008H)
A 1-word vector address area is used to execute interrupt request. If any interrupt service executes, the program
counter (PC) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt.
Users have to define the interrupt vector. The following example shows the way to define the interrupt vector in the
program memory.
Note: Users have to save and load ACC and PFLAG register by program as interrupt occurrence.
Example: Defining Interrupt Vector. The interrupt service routine is following ORG 8.
.DATA
ACCBUF
DS 1
; Define ACCBUF for store ACC data.
PFLAGBUF
DS 1
; Define PFLAGBUF for store PFLAG data.
.CODE
ORG
0
; 0000H
JMP
START
; Jump to user program address.
…
ORG
8
; Interrupt vector.
B0XCH
A, ACCBUF
; Save ACC in a buffer.
B0MOV
A, PFLAG
B0MOV
PFLAGBUF, A
; Save PFLAG register in a buffer.
…
…
B0MOV
A, PFLAGBUF
B0MOV
PFLAG, A
; Restore PFLAG register from buffer.
B0XCH
A, ACCBUF
; Restore ACC from buffer.
RETI
; End of interrupt service routine
…
START:
; The head of user program.
…
; User program
…
JMP
START
; End of user program
…
ENDP
; End of program

SN8P2977
8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC
SONiX TECHNOLOGY CO., LTD Page 20 V1.7
Example: Defining Interrupt Vector. The interrupt service routine is following user program.
.DATA
ACCBUF
DS 1
; Define ACCBUF for store ACC data.
PFLAGBUF
DS 1
; Define PFLAGBUF for store PFLAG data.
.CODE
ORG
0
; 0000H
JMP
START
; Jump to user program address.
…
ORG
8
; Interrupt vector.
JMP
MY_IRQ
; 0008H, Jump to interrupt service routine address.
ORG
10H
START:
; 0010H, The head of user program.
…
; User program.
…
…
JMP
START
; End of user program.
…
MY_IRQ:
;The head of interrupt service routine.
B0XCH
A, ACCBUF
; Save ACC in a buffer.
B0MOV
A, PFLAG
B0MOV
PFLAGBUF, A
; Save PFLAG register in a buffer.
…
…
B0MOV
A, PFLAGBUF
B0MOV
PFLAG, A
; Restore PFLAG register from buffer.
B0XCH
A, ACCBUF
; Restore ACC from buffer.
RETI
; End of interrupt service routine.
…
ENDP
; End of program.
Note: It is easy to understand the rules of SONIX program from demo programs given above. These points
are as following:
The address 0000H is a “JMP”instruction to make the program starts from the beginning.
The address 0008H is interrupt vector.
User’s program is a loop routine for main purpose application.